Viktor Zhezher / Mbed 2 deprecated SI570_VFO_F746NG

Library to control Silicon Labs SI570 10 MHZ TO 1.4 GHZ I2C PROGRAMMABLE XO/VCXO.

Dependencies:   mbed

Fork of SI570 by Gerrit Polder

BSP_F746NG/n25q128a.h@1:1556bcaaf759, 2016-03-27 (annotated)

Committer:
DL3LD
Date:
Sun Mar 27 06:55:59 2016 +0000
Revision:
1:1556bcaaf759
STM32F746NG SI570 VFO Test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
DL3LD 1:1556bcaaf759 1 /**
DL3LD 1:1556bcaaf759 2 ******************************************************************************
DL3LD 1:1556bcaaf759 3 * @file n25q128a.h
DL3LD 1:1556bcaaf759 4 * @author MCD Application Team
DL3LD 1:1556bcaaf759 5 * @version V1.0.0
DL3LD 1:1556bcaaf759 6 * @date 29-May-2015
DL3LD 1:1556bcaaf759 7 * @brief This file contains all the description of the N25Q128A QSPI memory.
DL3LD 1:1556bcaaf759 8 ******************************************************************************
DL3LD 1:1556bcaaf759 9 * @attention
DL3LD 1:1556bcaaf759 10 *
DL3LD 1:1556bcaaf759 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
DL3LD 1:1556bcaaf759 12 *
DL3LD 1:1556bcaaf759 13 * Redistribution and use in source and binary forms, with or without modification,
DL3LD 1:1556bcaaf759 14 * are permitted provided that the following conditions are met:
DL3LD 1:1556bcaaf759 15 * 1. Redistributions of source code must retain the above copyright notice,
DL3LD 1:1556bcaaf759 16 * this list of conditions and the following disclaimer.
DL3LD 1:1556bcaaf759 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
DL3LD 1:1556bcaaf759 18 * this list of conditions and the following disclaimer in the documentation
DL3LD 1:1556bcaaf759 19 * and/or other materials provided with the distribution.
DL3LD 1:1556bcaaf759 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
DL3LD 1:1556bcaaf759 21 * may be used to endorse or promote products derived from this software
DL3LD 1:1556bcaaf759 22 * without specific prior written permission.
DL3LD 1:1556bcaaf759 23 *
DL3LD 1:1556bcaaf759 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
DL3LD 1:1556bcaaf759 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
DL3LD 1:1556bcaaf759 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DL3LD 1:1556bcaaf759 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
DL3LD 1:1556bcaaf759 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DL3LD 1:1556bcaaf759 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
DL3LD 1:1556bcaaf759 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
DL3LD 1:1556bcaaf759 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
DL3LD 1:1556bcaaf759 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
DL3LD 1:1556bcaaf759 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
DL3LD 1:1556bcaaf759 34 *
DL3LD 1:1556bcaaf759 35 ******************************************************************************
DL3LD 1:1556bcaaf759 36 */
DL3LD 1:1556bcaaf759 37
DL3LD 1:1556bcaaf759 38 /* Define to prevent recursive inclusion -------------------------------------*/
DL3LD 1:1556bcaaf759 39 #ifndef __N25Q128A_H
DL3LD 1:1556bcaaf759 40 #define __N25Q128A_H
DL3LD 1:1556bcaaf759 41
DL3LD 1:1556bcaaf759 42 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 43 extern "C" {
DL3LD 1:1556bcaaf759 44 #endif
DL3LD 1:1556bcaaf759 45
DL3LD 1:1556bcaaf759 46 /* Includes ------------------------------------------------------------------*/
DL3LD 1:1556bcaaf759 47
DL3LD 1:1556bcaaf759 48 /** @addtogroup BSP
DL3LD 1:1556bcaaf759 49 * @{
DL3LD 1:1556bcaaf759 50 */
DL3LD 1:1556bcaaf759 51
DL3LD 1:1556bcaaf759 52 /** @addtogroup Components
DL3LD 1:1556bcaaf759 53 * @{
DL3LD 1:1556bcaaf759 54 */
DL3LD 1:1556bcaaf759 55
DL3LD 1:1556bcaaf759 56 /** @addtogroup n25q128a
DL3LD 1:1556bcaaf759 57 * @{
DL3LD 1:1556bcaaf759 58 */
DL3LD 1:1556bcaaf759 59
DL3LD 1:1556bcaaf759 60 /** @defgroup N25Q128A_Exported_Types
DL3LD 1:1556bcaaf759 61 * @{
DL3LD 1:1556bcaaf759 62 */
DL3LD 1:1556bcaaf759 63
DL3LD 1:1556bcaaf759 64 /**
DL3LD 1:1556bcaaf759 65 * @}
DL3LD 1:1556bcaaf759 66 */
DL3LD 1:1556bcaaf759 67
DL3LD 1:1556bcaaf759 68 /** @defgroup N25Q128A_Exported_Constants
DL3LD 1:1556bcaaf759 69 * @{
DL3LD 1:1556bcaaf759 70 */
DL3LD 1:1556bcaaf759 71
DL3LD 1:1556bcaaf759 72 /**
DL3LD 1:1556bcaaf759 73 * @brief N25Q128A Configuration
DL3LD 1:1556bcaaf759 74 */
DL3LD 1:1556bcaaf759 75 #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */
DL3LD 1:1556bcaaf759 76 #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */
DL3LD 1:1556bcaaf759 77 #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */
DL3LD 1:1556bcaaf759 78 #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */
DL3LD 1:1556bcaaf759 79
DL3LD 1:1556bcaaf759 80 #define N25Q128A_DUMMY_CYCLES_READ 8
DL3LD 1:1556bcaaf759 81 #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10
DL3LD 1:1556bcaaf759 82
DL3LD 1:1556bcaaf759 83 #define N25Q128A_BULK_ERASE_MAX_TIME 250000
DL3LD 1:1556bcaaf759 84 #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000
DL3LD 1:1556bcaaf759 85 #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800
DL3LD 1:1556bcaaf759 86
DL3LD 1:1556bcaaf759 87 /**
DL3LD 1:1556bcaaf759 88 * @brief N25Q128A Commands
DL3LD 1:1556bcaaf759 89 */
DL3LD 1:1556bcaaf759 90 /* Reset Operations */
DL3LD 1:1556bcaaf759 91 #define RESET_ENABLE_CMD 0x66
DL3LD 1:1556bcaaf759 92 #define RESET_MEMORY_CMD 0x99
DL3LD 1:1556bcaaf759 93
DL3LD 1:1556bcaaf759 94 /* Identification Operations */
DL3LD 1:1556bcaaf759 95 #define READ_ID_CMD 0x9E
DL3LD 1:1556bcaaf759 96 #define READ_ID_CMD2 0x9F
DL3LD 1:1556bcaaf759 97 #define MULTIPLE_IO_READ_ID_CMD 0xAF
DL3LD 1:1556bcaaf759 98 #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A
DL3LD 1:1556bcaaf759 99
DL3LD 1:1556bcaaf759 100 /* Read Operations */
DL3LD 1:1556bcaaf759 101 #define READ_CMD 0x03
DL3LD 1:1556bcaaf759 102 #define FAST_READ_CMD 0x0B
DL3LD 1:1556bcaaf759 103 #define DUAL_OUT_FAST_READ_CMD 0x3B
DL3LD 1:1556bcaaf759 104 #define DUAL_INOUT_FAST_READ_CMD 0xBB
DL3LD 1:1556bcaaf759 105 #define QUAD_OUT_FAST_READ_CMD 0x6B
DL3LD 1:1556bcaaf759 106 #define QUAD_INOUT_FAST_READ_CMD 0xEB
DL3LD 1:1556bcaaf759 107
DL3LD 1:1556bcaaf759 108 /* Write Operations */
DL3LD 1:1556bcaaf759 109 #define WRITE_ENABLE_CMD 0x06
DL3LD 1:1556bcaaf759 110 #define WRITE_DISABLE_CMD 0x04
DL3LD 1:1556bcaaf759 111
DL3LD 1:1556bcaaf759 112 /* Register Operations */
DL3LD 1:1556bcaaf759 113 #define READ_STATUS_REG_CMD 0x05
DL3LD 1:1556bcaaf759 114 #define WRITE_STATUS_REG_CMD 0x01
DL3LD 1:1556bcaaf759 115
DL3LD 1:1556bcaaf759 116 #define READ_LOCK_REG_CMD 0xE8
DL3LD 1:1556bcaaf759 117 #define WRITE_LOCK_REG_CMD 0xE5
DL3LD 1:1556bcaaf759 118
DL3LD 1:1556bcaaf759 119 #define READ_FLAG_STATUS_REG_CMD 0x70
DL3LD 1:1556bcaaf759 120 #define CLEAR_FLAG_STATUS_REG_CMD 0x50
DL3LD 1:1556bcaaf759 121
DL3LD 1:1556bcaaf759 122 #define READ_NONVOL_CFG_REG_CMD 0xB5
DL3LD 1:1556bcaaf759 123 #define WRITE_NONVOL_CFG_REG_CMD 0xB1
DL3LD 1:1556bcaaf759 124
DL3LD 1:1556bcaaf759 125 #define READ_VOL_CFG_REG_CMD 0x85
DL3LD 1:1556bcaaf759 126 #define WRITE_VOL_CFG_REG_CMD 0x81
DL3LD 1:1556bcaaf759 127
DL3LD 1:1556bcaaf759 128 #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65
DL3LD 1:1556bcaaf759 129 #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61
DL3LD 1:1556bcaaf759 130
DL3LD 1:1556bcaaf759 131 /* Program Operations */
DL3LD 1:1556bcaaf759 132 #define PAGE_PROG_CMD 0x02
DL3LD 1:1556bcaaf759 133 #define DUAL_IN_FAST_PROG_CMD 0xA2
DL3LD 1:1556bcaaf759 134 #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2
DL3LD 1:1556bcaaf759 135 #define QUAD_IN_FAST_PROG_CMD 0x32
DL3LD 1:1556bcaaf759 136 #define EXT_QUAD_IN_FAST_PROG_CMD 0x12
DL3LD 1:1556bcaaf759 137
DL3LD 1:1556bcaaf759 138 /* Erase Operations */
DL3LD 1:1556bcaaf759 139 #define SUBSECTOR_ERASE_CMD 0x20
DL3LD 1:1556bcaaf759 140 #define SECTOR_ERASE_CMD 0xD8
DL3LD 1:1556bcaaf759 141 #define BULK_ERASE_CMD 0xC7
DL3LD 1:1556bcaaf759 142
DL3LD 1:1556bcaaf759 143 #define PROG_ERASE_RESUME_CMD 0x7A
DL3LD 1:1556bcaaf759 144 #define PROG_ERASE_SUSPEND_CMD 0x75
DL3LD 1:1556bcaaf759 145
DL3LD 1:1556bcaaf759 146 /* One-Time Programmable Operations */
DL3LD 1:1556bcaaf759 147 #define READ_OTP_ARRAY_CMD 0x4B
DL3LD 1:1556bcaaf759 148 #define PROG_OTP_ARRAY_CMD 0x42
DL3LD 1:1556bcaaf759 149
DL3LD 1:1556bcaaf759 150 /**
DL3LD 1:1556bcaaf759 151 * @brief N25Q128A Registers
DL3LD 1:1556bcaaf759 152 */
DL3LD 1:1556bcaaf759 153 /* Status Register */
DL3LD 1:1556bcaaf759 154 #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */
DL3LD 1:1556bcaaf759 155 #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */
DL3LD 1:1556bcaaf759 156 #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */
DL3LD 1:1556bcaaf759 157 #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */
DL3LD 1:1556bcaaf759 158 #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */
DL3LD 1:1556bcaaf759 159
DL3LD 1:1556bcaaf759 160 /* Nonvolatile Configuration Register */
DL3LD 1:1556bcaaf759 161 #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */
DL3LD 1:1556bcaaf759 162 #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */
DL3LD 1:1556bcaaf759 163 #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */
DL3LD 1:1556bcaaf759 164 #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */
DL3LD 1:1556bcaaf759 165 #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */
DL3LD 1:1556bcaaf759 166 #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */
DL3LD 1:1556bcaaf759 167 #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */
DL3LD 1:1556bcaaf759 168
DL3LD 1:1556bcaaf759 169 /* Volatile Configuration Register */
DL3LD 1:1556bcaaf759 170 #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */
DL3LD 1:1556bcaaf759 171 #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */
DL3LD 1:1556bcaaf759 172 #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */
DL3LD 1:1556bcaaf759 173
DL3LD 1:1556bcaaf759 174 /* Enhanced Volatile Configuration Register */
DL3LD 1:1556bcaaf759 175 #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */
DL3LD 1:1556bcaaf759 176 #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */
DL3LD 1:1556bcaaf759 177 #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */
DL3LD 1:1556bcaaf759 178 #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */
DL3LD 1:1556bcaaf759 179 #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */
DL3LD 1:1556bcaaf759 180
DL3LD 1:1556bcaaf759 181 /* Flag Status Register */
DL3LD 1:1556bcaaf759 182 #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */
DL3LD 1:1556bcaaf759 183 #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */
DL3LD 1:1556bcaaf759 184 #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */
DL3LD 1:1556bcaaf759 185 #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */
DL3LD 1:1556bcaaf759 186 #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */
DL3LD 1:1556bcaaf759 187 #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */
DL3LD 1:1556bcaaf759 188 #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */
DL3LD 1:1556bcaaf759 189
DL3LD 1:1556bcaaf759 190 /**
DL3LD 1:1556bcaaf759 191 * @}
DL3LD 1:1556bcaaf759 192 */
DL3LD 1:1556bcaaf759 193
DL3LD 1:1556bcaaf759 194 /** @defgroup N25Q128A_Exported_Functions
DL3LD 1:1556bcaaf759 195 * @{
DL3LD 1:1556bcaaf759 196 */
DL3LD 1:1556bcaaf759 197 /**
DL3LD 1:1556bcaaf759 198 * @}
DL3LD 1:1556bcaaf759 199 */
DL3LD 1:1556bcaaf759 200
DL3LD 1:1556bcaaf759 201 /**
DL3LD 1:1556bcaaf759 202 * @}
DL3LD 1:1556bcaaf759 203 */
DL3LD 1:1556bcaaf759 204
DL3LD 1:1556bcaaf759 205 /**
DL3LD 1:1556bcaaf759 206 * @}
DL3LD 1:1556bcaaf759 207 */
DL3LD 1:1556bcaaf759 208
DL3LD 1:1556bcaaf759 209 /**
DL3LD 1:1556bcaaf759 210 * @}
DL3LD 1:1556bcaaf759 211 */
DL3LD 1:1556bcaaf759 212
DL3LD 1:1556bcaaf759 213 #ifdef __cplusplus
DL3LD 1:1556bcaaf759 214 }
DL3LD 1:1556bcaaf759 215 #endif
DL3LD 1:1556bcaaf759 216
DL3LD 1:1556bcaaf759 217 #endif /* __N25Q128A_H */
DL3LD 1:1556bcaaf759 218
DL3LD 1:1556bcaaf759 219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
DL3LD 1:1556bcaaf759 220