Roman Ciesarík / bluenrg_interface

bluenrg_interface

cube_hal_l4.c@0:fb1547f2354e, 2018-11-12 (annotated)

Committer:
Ciesarik3
Date:
Mon Nov 12 18:36:18 2018 +0000
Revision:
0:fb1547f2354e
crc;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Ciesarik3 0:fb1547f2354e 1 /**
Ciesarik3 0:fb1547f2354e 2 ******************************************************************************
Ciesarik3 0:fb1547f2354e 3 * @file cube_hal_l4.c
Ciesarik3 0:fb1547f2354e 4 * @author CL
Ciesarik3 0:fb1547f2354e 5 * @version V1.0.0
Ciesarik3 0:fb1547f2354e 6 * @date 13-July-2015
Ciesarik3 0:fb1547f2354e 7 * @brief
Ciesarik3 0:fb1547f2354e 8 ******************************************************************************
Ciesarik3 0:fb1547f2354e 9 * @attention
Ciesarik3 0:fb1547f2354e 10 *
Ciesarik3 0:fb1547f2354e 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Ciesarik3 0:fb1547f2354e 12 *
Ciesarik3 0:fb1547f2354e 13 * Redistribution and use in source and binary forms, with or without modification,
Ciesarik3 0:fb1547f2354e 14 * are permitted provided that the following conditions are met:
Ciesarik3 0:fb1547f2354e 15 * 1. Redistributions of source code must retain the above copyright notice,
Ciesarik3 0:fb1547f2354e 16 * this list of conditions and the following disclaimer.
Ciesarik3 0:fb1547f2354e 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Ciesarik3 0:fb1547f2354e 18 * this list of conditions and the following disclaimer in the documentation
Ciesarik3 0:fb1547f2354e 19 * and/or other materials provided with the distribution.
Ciesarik3 0:fb1547f2354e 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Ciesarik3 0:fb1547f2354e 21 * may be used to endorse or promote products derived from this software
Ciesarik3 0:fb1547f2354e 22 * without specific prior written permission.
Ciesarik3 0:fb1547f2354e 23 *
Ciesarik3 0:fb1547f2354e 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Ciesarik3 0:fb1547f2354e 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Ciesarik3 0:fb1547f2354e 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Ciesarik3 0:fb1547f2354e 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Ciesarik3 0:fb1547f2354e 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Ciesarik3 0:fb1547f2354e 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Ciesarik3 0:fb1547f2354e 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Ciesarik3 0:fb1547f2354e 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Ciesarik3 0:fb1547f2354e 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Ciesarik3 0:fb1547f2354e 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Ciesarik3 0:fb1547f2354e 34 *
Ciesarik3 0:fb1547f2354e 35 ******************************************************************************
Ciesarik3 0:fb1547f2354e 36 */
Ciesarik3 0:fb1547f2354e 37
Ciesarik3 0:fb1547f2354e 38 /* Includes ------------------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 39 #include "cube_hal.h"
Ciesarik3 0:fb1547f2354e 40
Ciesarik3 0:fb1547f2354e 41 /**
Ciesarik3 0:fb1547f2354e 42 * @brief System Clock Configuration
Ciesarik3 0:fb1547f2354e 43 * The system Clock is configured as follows :
Ciesarik3 0:fb1547f2354e 44 * System Clock source = PLL (MSI)
Ciesarik3 0:fb1547f2354e 45 * SYSCLK(Hz) = 80000000
Ciesarik3 0:fb1547f2354e 46 * HCLK(Hz) = 80000000
Ciesarik3 0:fb1547f2354e 47 * AHB Prescaler = 1
Ciesarik3 0:fb1547f2354e 48 * APB1 Prescaler = 1
Ciesarik3 0:fb1547f2354e 49 * APB2 Prescaler = 1
Ciesarik3 0:fb1547f2354e 50 * MSI Frequency(Hz) = 4000000
Ciesarik3 0:fb1547f2354e 51 * PLL_M = 1
Ciesarik3 0:fb1547f2354e 52 * PLL_N = 40
Ciesarik3 0:fb1547f2354e 53 * PLL_R = 2
Ciesarik3 0:fb1547f2354e 54 * PLL_P = 7
Ciesarik3 0:fb1547f2354e 55 * PLL_Q = 4
Ciesarik3 0:fb1547f2354e 56 * Flash Latency(WS) = 4
Ciesarik3 0:fb1547f2354e 57 * @param None
Ciesarik3 0:fb1547f2354e 58 * @retval None
Ciesarik3 0:fb1547f2354e 59 */
Ciesarik3 0:fb1547f2354e 60 void SystemClock_Config(void)
Ciesarik3 0:fb1547f2354e 61 {
Ciesarik3 0:fb1547f2354e 62 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Ciesarik3 0:fb1547f2354e 63 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Ciesarik3 0:fb1547f2354e 64
Ciesarik3 0:fb1547f2354e 65 /* MSI is enabled after System reset, activate PLL with MSI as source */
Ciesarik3 0:fb1547f2354e 66 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
Ciesarik3 0:fb1547f2354e 67 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
Ciesarik3 0:fb1547f2354e 68 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
Ciesarik3 0:fb1547f2354e 69 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
Ciesarik3 0:fb1547f2354e 70 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Ciesarik3 0:fb1547f2354e 71 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
Ciesarik3 0:fb1547f2354e 72 RCC_OscInitStruct.PLL.PLLM = 1;
Ciesarik3 0:fb1547f2354e 73 RCC_OscInitStruct.PLL.PLLN = 40;
Ciesarik3 0:fb1547f2354e 74 RCC_OscInitStruct.PLL.PLLR = 2;
Ciesarik3 0:fb1547f2354e 75 RCC_OscInitStruct.PLL.PLLP = 7;
Ciesarik3 0:fb1547f2354e 76 RCC_OscInitStruct.PLL.PLLQ = 4;
Ciesarik3 0:fb1547f2354e 77 if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
Ciesarik3 0:fb1547f2354e 78 {
Ciesarik3 0:fb1547f2354e 79 /* Initialization Error */
Ciesarik3 0:fb1547f2354e 80 while(1);
Ciesarik3 0:fb1547f2354e 81 }
Ciesarik3 0:fb1547f2354e 82
Ciesarik3 0:fb1547f2354e 83 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
Ciesarik3 0:fb1547f2354e 84 clocks dividers */
Ciesarik3 0:fb1547f2354e 85 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Ciesarik3 0:fb1547f2354e 86 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
Ciesarik3 0:fb1547f2354e 87 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Ciesarik3 0:fb1547f2354e 88 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
Ciesarik3 0:fb1547f2354e 89 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Ciesarik3 0:fb1547f2354e 90 if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
Ciesarik3 0:fb1547f2354e 91 {
Ciesarik3 0:fb1547f2354e 92 /* Initialization Error */
Ciesarik3 0:fb1547f2354e 93 while(1);
Ciesarik3 0:fb1547f2354e 94 }
Ciesarik3 0:fb1547f2354e 95 }
Ciesarik3 0:fb1547f2354e 96
Ciesarik3 0:fb1547f2354e 97 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/