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/**
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******************************************************************************
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* @file system_stm32l0xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l0xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l0xx_system
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* @{
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*/
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/** @addtogroup STM32L0xx_System_Private_Includes
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* @{
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*/
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#include "stm32l0xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (MSI_VALUE)
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#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 2000000U;
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L0xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/*!< Set MSION bit */
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RCC->CR |= (uint32_t)0x00000100U;
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/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
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RCC->CFGR &= (uint32_t) 0x88FF400CU;
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158
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/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFF6U;
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161
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/*!< Reset HSI48ON bit */
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RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
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/*!< Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFFU;
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/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
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RCC->CFGR &= (uint32_t)0xFF02FFFFU;
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170
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/*!< Disable all interrupts */
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RCC->CIER = 0x00000000U;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock according to Clock Register Values
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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0:fb1547f2354e
|
194
|
* constant and the selected clock source:
|
| Ciesarik3 |
0:fb1547f2354e
|
195
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
196
|
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
|
| Ciesarik3 |
0:fb1547f2354e
|
197
|
* value as defined by the MSI range.
|
| Ciesarik3 |
0:fb1547f2354e
|
198
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
199
|
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
| Ciesarik3 |
0:fb1547f2354e
|
200
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
201
|
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
| Ciesarik3 |
0:fb1547f2354e
|
202
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
203
|
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
| Ciesarik3 |
0:fb1547f2354e
|
204
|
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
| Ciesarik3 |
0:fb1547f2354e
|
205
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
206
|
* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
|
| Ciesarik3 |
0:fb1547f2354e
|
207
|
* 16 MHz) but the real value may vary depending on the variations
|
| Ciesarik3 |
0:fb1547f2354e
|
208
|
* in voltage and temperature.
|
| Ciesarik3 |
0:fb1547f2354e
|
209
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
210
|
* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
|
| Ciesarik3 |
0:fb1547f2354e
|
211
|
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
| Ciesarik3 |
0:fb1547f2354e
|
212
|
* frequency of the crystal used. Otherwise, this function may
|
| Ciesarik3 |
0:fb1547f2354e
|
213
|
* have wrong result.
|
| Ciesarik3 |
0:fb1547f2354e
|
214
|
*
|
| Ciesarik3 |
0:fb1547f2354e
|
215
|
* - The result of this function could be not correct when using fractional
|
| Ciesarik3 |
0:fb1547f2354e
|
216
|
* value for HSE crystal.
|
| Ciesarik3 |
0:fb1547f2354e
|
217
|
* @param None
|
| Ciesarik3 |
0:fb1547f2354e
|
218
|
* @retval None
|
| Ciesarik3 |
0:fb1547f2354e
|
219
|
*/
|
| Ciesarik3 |
0:fb1547f2354e
|
220
|
void SystemCoreClockUpdate (void)
|
| Ciesarik3 |
0:fb1547f2354e
|
221
|
{
|
| Ciesarik3 |
0:fb1547f2354e
|
222
|
uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U;
|
| Ciesarik3 |
0:fb1547f2354e
|
223
|
|
| Ciesarik3 |
0:fb1547f2354e
|
224
|
/* Get SYSCLK source -------------------------------------------------------*/
|
| Ciesarik3 |
0:fb1547f2354e
|
225
|
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
| Ciesarik3 |
0:fb1547f2354e
|
226
|
|
| Ciesarik3 |
0:fb1547f2354e
|
227
|
switch (tmp)
|
| Ciesarik3 |
0:fb1547f2354e
|
228
|
{
|
| Ciesarik3 |
0:fb1547f2354e
|
229
|
case 0x00U: /* MSI used as system clock */
|
| Ciesarik3 |
0:fb1547f2354e
|
230
|
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
|
| Ciesarik3 |
0:fb1547f2354e
|
231
|
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
|
| Ciesarik3 |
0:fb1547f2354e
|
232
|
break;
|
| Ciesarik3 |
0:fb1547f2354e
|
233
|
case 0x04U: /* HSI used as system clock */
|
| Ciesarik3 |
0:fb1547f2354e
|
234
|
SystemCoreClock = HSI_VALUE;
|
| Ciesarik3 |
0:fb1547f2354e
|
235
|
break;
|
| Ciesarik3 |
0:fb1547f2354e
|
236
|
case 0x08U: /* HSE used as system clock */
|
| Ciesarik3 |
0:fb1547f2354e
|
237
|
SystemCoreClock = HSE_VALUE;
|
| Ciesarik3 |
0:fb1547f2354e
|
238
|
break;
|
| Ciesarik3 |
0:fb1547f2354e
|
239
|
case 0x0CU: /* PLL used as system clock */
|
| Ciesarik3 |
0:fb1547f2354e
|
240
|
/* Get PLL clock source and multiplication factor ----------------------*/
|
| Ciesarik3 |
0:fb1547f2354e
|
241
|
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
|
| Ciesarik3 |
0:fb1547f2354e
|
242
|
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
|
| Ciesarik3 |
0:fb1547f2354e
|
243
|
pllmul = PLLMulTable[(pllmul >> 18U)];
|
| Ciesarik3 |
0:fb1547f2354e
|
244
|
plldiv = (plldiv >> 22U) + 1U;
|
| Ciesarik3 |
0:fb1547f2354e
|
245
|
|
| Ciesarik3 |
0:fb1547f2354e
|
246
|
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
| Ciesarik3 |
0:fb1547f2354e
|
247
|
|
| Ciesarik3 |
0:fb1547f2354e
|
248
|
if (pllsource == 0x00U)
|
| Ciesarik3 |
0:fb1547f2354e
|
249
|
{
|
| Ciesarik3 |
0:fb1547f2354e
|
250
|
/* HSI oscillator clock selected as PLL clock entry */
|
| Ciesarik3 |
0:fb1547f2354e
|
251
|
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
|
| Ciesarik3 |
0:fb1547f2354e
|
252
|
}
|
| Ciesarik3 |
0:fb1547f2354e
|
253
|
else
|
| Ciesarik3 |
0:fb1547f2354e
|
254
|
{
|
| Ciesarik3 |
0:fb1547f2354e
|
255
|
/* HSE selected as PLL clock entry */
|
| Ciesarik3 |
0:fb1547f2354e
|
256
|
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
|
| Ciesarik3 |
0:fb1547f2354e
|
257
|
}
|
| Ciesarik3 |
0:fb1547f2354e
|
258
|
break;
|
| Ciesarik3 |
0:fb1547f2354e
|
259
|
default: /* MSI used as system clock */
|
| Ciesarik3 |
0:fb1547f2354e
|
260
|
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U;
|
| Ciesarik3 |
0:fb1547f2354e
|
261
|
SystemCoreClock = (32768U * (1U << (msirange + 1U)));
|
| Ciesarik3 |
0:fb1547f2354e
|
262
|
break;
|
| Ciesarik3 |
0:fb1547f2354e
|
263
|
}
|
| Ciesarik3 |
0:fb1547f2354e
|
264
|
/* Compute HCLK clock frequency --------------------------------------------*/
|
| Ciesarik3 |
0:fb1547f2354e
|
265
|
/* Get HCLK prescaler */
|
| Ciesarik3 |
0:fb1547f2354e
|
266
|
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)];
|
| Ciesarik3 |
0:fb1547f2354e
|
267
|
/* HCLK clock frequency */
|
| Ciesarik3 |
0:fb1547f2354e
|
268
|
SystemCoreClock >>= tmp;
|
| Ciesarik3 |
0:fb1547f2354e
|
269
|
}
|
| Ciesarik3 |
0:fb1547f2354e
|
270
|
|
| Ciesarik3 |
0:fb1547f2354e
|
271
|
|
| Ciesarik3 |
0:fb1547f2354e
|
272
|
|
| Ciesarik3 |
0:fb1547f2354e
|
273
|
/**
|
| Ciesarik3 |
0:fb1547f2354e
|
274
|
* @}
|
| Ciesarik3 |
0:fb1547f2354e
|
275
|
*/
|
| Ciesarik3 |
0:fb1547f2354e
|
276
|
|
| Ciesarik3 |
0:fb1547f2354e
|
277
|
/**
|
| Ciesarik3 |
0:fb1547f2354e
|
278
|
* @}
|
| Ciesarik3 |
0:fb1547f2354e
|
279
|
*/
|
| Ciesarik3 |
0:fb1547f2354e
|
280
|
|
| Ciesarik3 |
0:fb1547f2354e
|
281
|
/**
|
| Ciesarik3 |
0:fb1547f2354e
|
282
|
* @}
|
| Ciesarik3 |
0:fb1547f2354e
|
283
|
*/
|
| Ciesarik3 |
0:fb1547f2354e
|
284
|
|
| Ciesarik3 |
0:fb1547f2354e
|
285
|
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|