Roman Ciesarík
bluenrg_interface
system_stm32f4xx.c@0:fb1547f2354e, 2018-11-12 (annotated)
- Committer:
- Ciesarik3
- Date:
- Mon Nov 12 18:36:18 2018 +0000
- Revision:
- 0:fb1547f2354e
crc;
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Ciesarik3 | 0:fb1547f2354e | 1 | /** |
| Ciesarik3 | 0:fb1547f2354e | 2 | ****************************************************************************** |
| Ciesarik3 | 0:fb1547f2354e | 3 | * @file system_stm32f4xx.c |
| Ciesarik3 | 0:fb1547f2354e | 4 | * @author MCD Application Team |
| Ciesarik3 | 0:fb1547f2354e | 5 | * @version V2.6.1 |
| Ciesarik3 | 0:fb1547f2354e | 6 | * @date 14-February-2017 |
| Ciesarik3 | 0:fb1547f2354e | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| Ciesarik3 | 0:fb1547f2354e | 8 | * |
| Ciesarik3 | 0:fb1547f2354e | 9 | * This file provides two functions and one global variable to be called from |
| Ciesarik3 | 0:fb1547f2354e | 10 | * user application: |
| Ciesarik3 | 0:fb1547f2354e | 11 | * - SystemInit(): This function is called at startup just after reset and |
| Ciesarik3 | 0:fb1547f2354e | 12 | * before branch to main program. This call is made inside |
| Ciesarik3 | 0:fb1547f2354e | 13 | * the "startup_stm32f4xx.s" file. |
| Ciesarik3 | 0:fb1547f2354e | 14 | * |
| Ciesarik3 | 0:fb1547f2354e | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| Ciesarik3 | 0:fb1547f2354e | 16 | * by the user application to setup the SysTick |
| Ciesarik3 | 0:fb1547f2354e | 17 | * timer or configure other parameters. |
| Ciesarik3 | 0:fb1547f2354e | 18 | * |
| Ciesarik3 | 0:fb1547f2354e | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| Ciesarik3 | 0:fb1547f2354e | 20 | * be called whenever the core clock is changed |
| Ciesarik3 | 0:fb1547f2354e | 21 | * during program execution. |
| Ciesarik3 | 0:fb1547f2354e | 22 | * |
| Ciesarik3 | 0:fb1547f2354e | 23 | * |
| Ciesarik3 | 0:fb1547f2354e | 24 | ****************************************************************************** |
| Ciesarik3 | 0:fb1547f2354e | 25 | * @attention |
| Ciesarik3 | 0:fb1547f2354e | 26 | * |
| Ciesarik3 | 0:fb1547f2354e | 27 | * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> |
| Ciesarik3 | 0:fb1547f2354e | 28 | * |
| Ciesarik3 | 0:fb1547f2354e | 29 | * Redistribution and use in source and binary forms, with or without modification, |
| Ciesarik3 | 0:fb1547f2354e | 30 | * are permitted provided that the following conditions are met: |
| Ciesarik3 | 0:fb1547f2354e | 31 | * 1. Redistributions of source code must retain the above copyright notice, |
| Ciesarik3 | 0:fb1547f2354e | 32 | * this list of conditions and the following disclaimer. |
| Ciesarik3 | 0:fb1547f2354e | 33 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Ciesarik3 | 0:fb1547f2354e | 34 | * this list of conditions and the following disclaimer in the documentation |
| Ciesarik3 | 0:fb1547f2354e | 35 | * and/or other materials provided with the distribution. |
| Ciesarik3 | 0:fb1547f2354e | 36 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Ciesarik3 | 0:fb1547f2354e | 37 | * may be used to endorse or promote products derived from this software |
| Ciesarik3 | 0:fb1547f2354e | 38 | * without specific prior written permission. |
| Ciesarik3 | 0:fb1547f2354e | 39 | * |
| Ciesarik3 | 0:fb1547f2354e | 40 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Ciesarik3 | 0:fb1547f2354e | 41 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Ciesarik3 | 0:fb1547f2354e | 42 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Ciesarik3 | 0:fb1547f2354e | 43 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Ciesarik3 | 0:fb1547f2354e | 44 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Ciesarik3 | 0:fb1547f2354e | 45 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Ciesarik3 | 0:fb1547f2354e | 46 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Ciesarik3 | 0:fb1547f2354e | 47 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Ciesarik3 | 0:fb1547f2354e | 48 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Ciesarik3 | 0:fb1547f2354e | 49 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Ciesarik3 | 0:fb1547f2354e | 50 | * |
| Ciesarik3 | 0:fb1547f2354e | 51 | ****************************************************************************** |
| Ciesarik3 | 0:fb1547f2354e | 52 | */ |
| Ciesarik3 | 0:fb1547f2354e | 53 | |
| Ciesarik3 | 0:fb1547f2354e | 54 | /** @addtogroup CMSIS |
| Ciesarik3 | 0:fb1547f2354e | 55 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 56 | */ |
| Ciesarik3 | 0:fb1547f2354e | 57 | |
| Ciesarik3 | 0:fb1547f2354e | 58 | /** @addtogroup stm32f4xx_system |
| Ciesarik3 | 0:fb1547f2354e | 59 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 60 | */ |
| Ciesarik3 | 0:fb1547f2354e | 61 | |
| Ciesarik3 | 0:fb1547f2354e | 62 | /** @addtogroup STM32F4xx_System_Private_Includes |
| Ciesarik3 | 0:fb1547f2354e | 63 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 64 | */ |
| Ciesarik3 | 0:fb1547f2354e | 65 | |
| Ciesarik3 | 0:fb1547f2354e | 66 | |
| Ciesarik3 | 0:fb1547f2354e | 67 | #include "stm32f4xx.h" |
| Ciesarik3 | 0:fb1547f2354e | 68 | |
| Ciesarik3 | 0:fb1547f2354e | 69 | #if !defined (HSE_VALUE) |
| Ciesarik3 | 0:fb1547f2354e | 70 | #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ |
| Ciesarik3 | 0:fb1547f2354e | 71 | #endif /* HSE_VALUE */ |
| Ciesarik3 | 0:fb1547f2354e | 72 | |
| Ciesarik3 | 0:fb1547f2354e | 73 | #if !defined (HSI_VALUE) |
| Ciesarik3 | 0:fb1547f2354e | 74 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| Ciesarik3 | 0:fb1547f2354e | 75 | #endif /* HSI_VALUE */ |
| Ciesarik3 | 0:fb1547f2354e | 76 | |
| Ciesarik3 | 0:fb1547f2354e | 77 | /** |
| Ciesarik3 | 0:fb1547f2354e | 78 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 79 | */ |
| Ciesarik3 | 0:fb1547f2354e | 80 | |
| Ciesarik3 | 0:fb1547f2354e | 81 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| Ciesarik3 | 0:fb1547f2354e | 82 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 83 | */ |
| Ciesarik3 | 0:fb1547f2354e | 84 | |
| Ciesarik3 | 0:fb1547f2354e | 85 | /** |
| Ciesarik3 | 0:fb1547f2354e | 86 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 87 | */ |
| Ciesarik3 | 0:fb1547f2354e | 88 | |
| Ciesarik3 | 0:fb1547f2354e | 89 | /** @addtogroup STM32F4xx_System_Private_Defines |
| Ciesarik3 | 0:fb1547f2354e | 90 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 91 | */ |
| Ciesarik3 | 0:fb1547f2354e | 92 | |
| Ciesarik3 | 0:fb1547f2354e | 93 | /************************* Miscellaneous Configuration ************************/ |
| Ciesarik3 | 0:fb1547f2354e | 94 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
| Ciesarik3 | 0:fb1547f2354e | 95 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 96 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 97 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Ciesarik3 | 0:fb1547f2354e | 98 | /* #define DATA_IN_ExtSRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 99 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ |
| Ciesarik3 | 0:fb1547f2354e | 100 | STM32F412Zx || STM32F412Vx */ |
| Ciesarik3 | 0:fb1547f2354e | 101 | |
| Ciesarik3 | 0:fb1547f2354e | 102 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 103 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 104 | /* #define DATA_IN_ExtSDRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 105 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
| Ciesarik3 | 0:fb1547f2354e | 106 | STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 107 | |
| Ciesarik3 | 0:fb1547f2354e | 108 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| Ciesarik3 | 0:fb1547f2354e | 109 | Internal SRAM. */ |
| Ciesarik3 | 0:fb1547f2354e | 110 | /* #define VECT_TAB_SRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 111 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| Ciesarik3 | 0:fb1547f2354e | 112 | This value must be a multiple of 0x200. */ |
| Ciesarik3 | 0:fb1547f2354e | 113 | /******************************************************************************/ |
| Ciesarik3 | 0:fb1547f2354e | 114 | |
| Ciesarik3 | 0:fb1547f2354e | 115 | /** |
| Ciesarik3 | 0:fb1547f2354e | 116 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 117 | */ |
| Ciesarik3 | 0:fb1547f2354e | 118 | |
| Ciesarik3 | 0:fb1547f2354e | 119 | /** @addtogroup STM32F4xx_System_Private_Macros |
| Ciesarik3 | 0:fb1547f2354e | 120 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 121 | */ |
| Ciesarik3 | 0:fb1547f2354e | 122 | |
| Ciesarik3 | 0:fb1547f2354e | 123 | /** |
| Ciesarik3 | 0:fb1547f2354e | 124 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 125 | */ |
| Ciesarik3 | 0:fb1547f2354e | 126 | |
| Ciesarik3 | 0:fb1547f2354e | 127 | /** @addtogroup STM32F4xx_System_Private_Variables |
| Ciesarik3 | 0:fb1547f2354e | 128 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 129 | */ |
| Ciesarik3 | 0:fb1547f2354e | 130 | /* This variable is updated in three ways: |
| Ciesarik3 | 0:fb1547f2354e | 131 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| Ciesarik3 | 0:fb1547f2354e | 132 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| Ciesarik3 | 0:fb1547f2354e | 133 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| Ciesarik3 | 0:fb1547f2354e | 134 | Note: If you use this function to configure the system clock; then there |
| Ciesarik3 | 0:fb1547f2354e | 135 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| Ciesarik3 | 0:fb1547f2354e | 136 | variable is updated automatically. |
| Ciesarik3 | 0:fb1547f2354e | 137 | */ |
| Ciesarik3 | 0:fb1547f2354e | 138 | uint32_t SystemCoreClock = 16000000; |
| Ciesarik3 | 0:fb1547f2354e | 139 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| Ciesarik3 | 0:fb1547f2354e | 140 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; |
| Ciesarik3 | 0:fb1547f2354e | 141 | /** |
| Ciesarik3 | 0:fb1547f2354e | 142 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 143 | */ |
| Ciesarik3 | 0:fb1547f2354e | 144 | |
| Ciesarik3 | 0:fb1547f2354e | 145 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| Ciesarik3 | 0:fb1547f2354e | 146 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 147 | */ |
| Ciesarik3 | 0:fb1547f2354e | 148 | |
| Ciesarik3 | 0:fb1547f2354e | 149 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 150 | static void SystemInit_ExtMemCtl(void); |
| Ciesarik3 | 0:fb1547f2354e | 151 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 152 | |
| Ciesarik3 | 0:fb1547f2354e | 153 | /** |
| Ciesarik3 | 0:fb1547f2354e | 154 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 155 | */ |
| Ciesarik3 | 0:fb1547f2354e | 156 | |
| Ciesarik3 | 0:fb1547f2354e | 157 | /** @addtogroup STM32F4xx_System_Private_Functions |
| Ciesarik3 | 0:fb1547f2354e | 158 | * @{ |
| Ciesarik3 | 0:fb1547f2354e | 159 | */ |
| Ciesarik3 | 0:fb1547f2354e | 160 | |
| Ciesarik3 | 0:fb1547f2354e | 161 | /** |
| Ciesarik3 | 0:fb1547f2354e | 162 | * @brief Setup the microcontroller system |
| Ciesarik3 | 0:fb1547f2354e | 163 | * Initialize the FPU setting, vector table location and External memory |
| Ciesarik3 | 0:fb1547f2354e | 164 | * configuration. |
| Ciesarik3 | 0:fb1547f2354e | 165 | * @param None |
| Ciesarik3 | 0:fb1547f2354e | 166 | * @retval None |
| Ciesarik3 | 0:fb1547f2354e | 167 | */ |
| Ciesarik3 | 0:fb1547f2354e | 168 | void SystemInit(void) |
| Ciesarik3 | 0:fb1547f2354e | 169 | { |
| Ciesarik3 | 0:fb1547f2354e | 170 | /* FPU settings ------------------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 171 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| Ciesarik3 | 0:fb1547f2354e | 172 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| Ciesarik3 | 0:fb1547f2354e | 173 | #endif |
| Ciesarik3 | 0:fb1547f2354e | 174 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 175 | /* Set HSION bit */ |
| Ciesarik3 | 0:fb1547f2354e | 176 | RCC->CR |= (uint32_t)0x00000001; |
| Ciesarik3 | 0:fb1547f2354e | 177 | |
| Ciesarik3 | 0:fb1547f2354e | 178 | /* Reset CFGR register */ |
| Ciesarik3 | 0:fb1547f2354e | 179 | RCC->CFGR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 180 | |
| Ciesarik3 | 0:fb1547f2354e | 181 | /* Reset HSEON, CSSON and PLLON bits */ |
| Ciesarik3 | 0:fb1547f2354e | 182 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| Ciesarik3 | 0:fb1547f2354e | 183 | |
| Ciesarik3 | 0:fb1547f2354e | 184 | /* Reset PLLCFGR register */ |
| Ciesarik3 | 0:fb1547f2354e | 185 | RCC->PLLCFGR = 0x24003010; |
| Ciesarik3 | 0:fb1547f2354e | 186 | |
| Ciesarik3 | 0:fb1547f2354e | 187 | /* Reset HSEBYP bit */ |
| Ciesarik3 | 0:fb1547f2354e | 188 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 189 | |
| Ciesarik3 | 0:fb1547f2354e | 190 | /* Disable all interrupts */ |
| Ciesarik3 | 0:fb1547f2354e | 191 | RCC->CIR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 192 | |
| Ciesarik3 | 0:fb1547f2354e | 193 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 194 | SystemInit_ExtMemCtl(); |
| Ciesarik3 | 0:fb1547f2354e | 195 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 196 | |
| Ciesarik3 | 0:fb1547f2354e | 197 | /* Configure the Vector Table location add offset address ------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 198 | #ifdef VECT_TAB_SRAM |
| Ciesarik3 | 0:fb1547f2354e | 199 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 200 | #else |
| Ciesarik3 | 0:fb1547f2354e | 201 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| Ciesarik3 | 0:fb1547f2354e | 202 | #endif |
| Ciesarik3 | 0:fb1547f2354e | 203 | } |
| Ciesarik3 | 0:fb1547f2354e | 204 | |
| Ciesarik3 | 0:fb1547f2354e | 205 | /** |
| Ciesarik3 | 0:fb1547f2354e | 206 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| Ciesarik3 | 0:fb1547f2354e | 207 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| Ciesarik3 | 0:fb1547f2354e | 208 | * be used by the user application to setup the SysTick timer or configure |
| Ciesarik3 | 0:fb1547f2354e | 209 | * other parameters. |
| Ciesarik3 | 0:fb1547f2354e | 210 | * |
| Ciesarik3 | 0:fb1547f2354e | 211 | * @note Each time the core clock (HCLK) changes, this function must be called |
| Ciesarik3 | 0:fb1547f2354e | 212 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| Ciesarik3 | 0:fb1547f2354e | 213 | * based on this variable will be incorrect. |
| Ciesarik3 | 0:fb1547f2354e | 214 | * |
| Ciesarik3 | 0:fb1547f2354e | 215 | * @note - The system frequency computed by this function is not the real |
| Ciesarik3 | 0:fb1547f2354e | 216 | * frequency in the chip. It is calculated based on the predefined |
| Ciesarik3 | 0:fb1547f2354e | 217 | * constant and the selected clock source: |
| Ciesarik3 | 0:fb1547f2354e | 218 | * |
| Ciesarik3 | 0:fb1547f2354e | 219 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| Ciesarik3 | 0:fb1547f2354e | 220 | * |
| Ciesarik3 | 0:fb1547f2354e | 221 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| Ciesarik3 | 0:fb1547f2354e | 222 | * |
| Ciesarik3 | 0:fb1547f2354e | 223 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| Ciesarik3 | 0:fb1547f2354e | 224 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| Ciesarik3 | 0:fb1547f2354e | 225 | * |
| Ciesarik3 | 0:fb1547f2354e | 226 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| Ciesarik3 | 0:fb1547f2354e | 227 | * 16 MHz) but the real value may vary depending on the variations |
| Ciesarik3 | 0:fb1547f2354e | 228 | * in voltage and temperature. |
| Ciesarik3 | 0:fb1547f2354e | 229 | * |
| Ciesarik3 | 0:fb1547f2354e | 230 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| Ciesarik3 | 0:fb1547f2354e | 231 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| Ciesarik3 | 0:fb1547f2354e | 232 | * is same as the real frequency of the crystal used. Otherwise, this function |
| Ciesarik3 | 0:fb1547f2354e | 233 | * may have wrong result. |
| Ciesarik3 | 0:fb1547f2354e | 234 | * |
| Ciesarik3 | 0:fb1547f2354e | 235 | * - The result of this function could be not correct when using fractional |
| Ciesarik3 | 0:fb1547f2354e | 236 | * value for HSE crystal. |
| Ciesarik3 | 0:fb1547f2354e | 237 | * |
| Ciesarik3 | 0:fb1547f2354e | 238 | * @param None |
| Ciesarik3 | 0:fb1547f2354e | 239 | * @retval None |
| Ciesarik3 | 0:fb1547f2354e | 240 | */ |
| Ciesarik3 | 0:fb1547f2354e | 241 | void SystemCoreClockUpdate(void) |
| Ciesarik3 | 0:fb1547f2354e | 242 | { |
| Ciesarik3 | 0:fb1547f2354e | 243 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| Ciesarik3 | 0:fb1547f2354e | 244 | |
| Ciesarik3 | 0:fb1547f2354e | 245 | /* Get SYSCLK source -------------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 246 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| Ciesarik3 | 0:fb1547f2354e | 247 | |
| Ciesarik3 | 0:fb1547f2354e | 248 | switch (tmp) |
| Ciesarik3 | 0:fb1547f2354e | 249 | { |
| Ciesarik3 | 0:fb1547f2354e | 250 | case 0x00: /* HSI used as system clock source */ |
| Ciesarik3 | 0:fb1547f2354e | 251 | SystemCoreClock = HSI_VALUE; |
| Ciesarik3 | 0:fb1547f2354e | 252 | break; |
| Ciesarik3 | 0:fb1547f2354e | 253 | case 0x04: /* HSE used as system clock source */ |
| Ciesarik3 | 0:fb1547f2354e | 254 | SystemCoreClock = HSE_VALUE; |
| Ciesarik3 | 0:fb1547f2354e | 255 | break; |
| Ciesarik3 | 0:fb1547f2354e | 256 | case 0x08: /* PLL used as system clock source */ |
| Ciesarik3 | 0:fb1547f2354e | 257 | |
| Ciesarik3 | 0:fb1547f2354e | 258 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| Ciesarik3 | 0:fb1547f2354e | 259 | SYSCLK = PLL_VCO / PLL_P |
| Ciesarik3 | 0:fb1547f2354e | 260 | */ |
| Ciesarik3 | 0:fb1547f2354e | 261 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| Ciesarik3 | 0:fb1547f2354e | 262 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| Ciesarik3 | 0:fb1547f2354e | 263 | |
| Ciesarik3 | 0:fb1547f2354e | 264 | if (pllsource != 0) |
| Ciesarik3 | 0:fb1547f2354e | 265 | { |
| Ciesarik3 | 0:fb1547f2354e | 266 | /* HSE used as PLL clock source */ |
| Ciesarik3 | 0:fb1547f2354e | 267 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| Ciesarik3 | 0:fb1547f2354e | 268 | } |
| Ciesarik3 | 0:fb1547f2354e | 269 | else |
| Ciesarik3 | 0:fb1547f2354e | 270 | { |
| Ciesarik3 | 0:fb1547f2354e | 271 | /* HSI used as PLL clock source */ |
| Ciesarik3 | 0:fb1547f2354e | 272 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| Ciesarik3 | 0:fb1547f2354e | 273 | } |
| Ciesarik3 | 0:fb1547f2354e | 274 | |
| Ciesarik3 | 0:fb1547f2354e | 275 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| Ciesarik3 | 0:fb1547f2354e | 276 | SystemCoreClock = pllvco/pllp; |
| Ciesarik3 | 0:fb1547f2354e | 277 | break; |
| Ciesarik3 | 0:fb1547f2354e | 278 | default: |
| Ciesarik3 | 0:fb1547f2354e | 279 | SystemCoreClock = HSI_VALUE; |
| Ciesarik3 | 0:fb1547f2354e | 280 | break; |
| Ciesarik3 | 0:fb1547f2354e | 281 | } |
| Ciesarik3 | 0:fb1547f2354e | 282 | /* Compute HCLK frequency --------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 283 | /* Get HCLK prescaler */ |
| Ciesarik3 | 0:fb1547f2354e | 284 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| Ciesarik3 | 0:fb1547f2354e | 285 | /* HCLK frequency */ |
| Ciesarik3 | 0:fb1547f2354e | 286 | SystemCoreClock >>= tmp; |
| Ciesarik3 | 0:fb1547f2354e | 287 | } |
| Ciesarik3 | 0:fb1547f2354e | 288 | |
| Ciesarik3 | 0:fb1547f2354e | 289 | #if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 290 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 291 | || defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 292 | /** |
| Ciesarik3 | 0:fb1547f2354e | 293 | * @brief Setup the external memory controller. |
| Ciesarik3 | 0:fb1547f2354e | 294 | * Called in startup_stm32f4xx.s before jump to main. |
| Ciesarik3 | 0:fb1547f2354e | 295 | * This function configures the external memories (SRAM/SDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 296 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| Ciesarik3 | 0:fb1547f2354e | 297 | * @param None |
| Ciesarik3 | 0:fb1547f2354e | 298 | * @retval None |
| Ciesarik3 | 0:fb1547f2354e | 299 | */ |
| Ciesarik3 | 0:fb1547f2354e | 300 | void SystemInit_ExtMemCtl(void) |
| Ciesarik3 | 0:fb1547f2354e | 301 | { |
| Ciesarik3 | 0:fb1547f2354e | 302 | __IO uint32_t tmp = 0x00; |
| Ciesarik3 | 0:fb1547f2354e | 303 | |
| Ciesarik3 | 0:fb1547f2354e | 304 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 305 | register __IO uint32_t index; |
| Ciesarik3 | 0:fb1547f2354e | 306 | |
| Ciesarik3 | 0:fb1547f2354e | 307 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ |
| Ciesarik3 | 0:fb1547f2354e | 308 | RCC->AHB1ENR |= 0x000001F8; |
| Ciesarik3 | 0:fb1547f2354e | 309 | |
| Ciesarik3 | 0:fb1547f2354e | 310 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 311 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| Ciesarik3 | 0:fb1547f2354e | 312 | |
| Ciesarik3 | 0:fb1547f2354e | 313 | /* Connect PDx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 314 | GPIOD->AFR[0] = 0x00CCC0CC; |
| Ciesarik3 | 0:fb1547f2354e | 315 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 316 | /* Configure PDx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 317 | GPIOD->MODER = 0xAAAA0A8A; |
| Ciesarik3 | 0:fb1547f2354e | 318 | /* Configure PDx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 319 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| Ciesarik3 | 0:fb1547f2354e | 320 | /* Configure PDx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 321 | GPIOD->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 322 | /* No pull-up, pull-down for PDx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 323 | GPIOD->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 324 | |
| Ciesarik3 | 0:fb1547f2354e | 325 | /* Connect PEx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 326 | GPIOE->AFR[0] = 0xC00CC0CC; |
| Ciesarik3 | 0:fb1547f2354e | 327 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 328 | /* Configure PEx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 329 | GPIOE->MODER = 0xAAAA828A; |
| Ciesarik3 | 0:fb1547f2354e | 330 | /* Configure PEx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 331 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| Ciesarik3 | 0:fb1547f2354e | 332 | /* Configure PEx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 333 | GPIOE->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 334 | /* No pull-up, pull-down for PEx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 335 | GPIOE->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 336 | |
| Ciesarik3 | 0:fb1547f2354e | 337 | /* Connect PFx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 338 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 339 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 340 | /* Configure PFx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 341 | GPIOF->MODER = 0xAA800AAA; |
| Ciesarik3 | 0:fb1547f2354e | 342 | /* Configure PFx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 343 | GPIOF->OSPEEDR = 0xAA800AAA; |
| Ciesarik3 | 0:fb1547f2354e | 344 | /* Configure PFx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 345 | GPIOF->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 346 | /* No pull-up, pull-down for PFx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 347 | GPIOF->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 348 | |
| Ciesarik3 | 0:fb1547f2354e | 349 | /* Connect PGx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 350 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 351 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 352 | /* Configure PGx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 353 | GPIOG->MODER = 0xAAAAAAAA; |
| Ciesarik3 | 0:fb1547f2354e | 354 | /* Configure PGx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 355 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| Ciesarik3 | 0:fb1547f2354e | 356 | /* Configure PGx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 357 | GPIOG->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 358 | /* No pull-up, pull-down for PGx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 359 | GPIOG->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 360 | |
| Ciesarik3 | 0:fb1547f2354e | 361 | /* Connect PHx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 362 | GPIOH->AFR[0] = 0x00C0CC00; |
| Ciesarik3 | 0:fb1547f2354e | 363 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 364 | /* Configure PHx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 365 | GPIOH->MODER = 0xAAAA08A0; |
| Ciesarik3 | 0:fb1547f2354e | 366 | /* Configure PHx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 367 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| Ciesarik3 | 0:fb1547f2354e | 368 | /* Configure PHx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 369 | GPIOH->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 370 | /* No pull-up, pull-down for PHx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 371 | GPIOH->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 372 | |
| Ciesarik3 | 0:fb1547f2354e | 373 | /* Connect PIx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 374 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 375 | GPIOI->AFR[1] = 0x00000CC0; |
| Ciesarik3 | 0:fb1547f2354e | 376 | /* Configure PIx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 377 | GPIOI->MODER = 0x0028AAAA; |
| Ciesarik3 | 0:fb1547f2354e | 378 | /* Configure PIx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 379 | GPIOI->OSPEEDR = 0x0028AAAA; |
| Ciesarik3 | 0:fb1547f2354e | 380 | /* Configure PIx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 381 | GPIOI->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 382 | /* No pull-up, pull-down for PIx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 383 | GPIOI->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 384 | |
| Ciesarik3 | 0:fb1547f2354e | 385 | /*-- FMC Configuration -------------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 386 | /* Enable the FMC interface clock */ |
| Ciesarik3 | 0:fb1547f2354e | 387 | RCC->AHB3ENR |= 0x00000001; |
| Ciesarik3 | 0:fb1547f2354e | 388 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 389 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Ciesarik3 | 0:fb1547f2354e | 390 | |
| Ciesarik3 | 0:fb1547f2354e | 391 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| Ciesarik3 | 0:fb1547f2354e | 392 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| Ciesarik3 | 0:fb1547f2354e | 393 | |
| Ciesarik3 | 0:fb1547f2354e | 394 | /* SDRAM initialization sequence */ |
| Ciesarik3 | 0:fb1547f2354e | 395 | /* Clock enable command */ |
| Ciesarik3 | 0:fb1547f2354e | 396 | FMC_Bank5_6->SDCMR = 0x00000011; |
| Ciesarik3 | 0:fb1547f2354e | 397 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 398 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 399 | { |
| Ciesarik3 | 0:fb1547f2354e | 400 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 401 | } |
| Ciesarik3 | 0:fb1547f2354e | 402 | |
| Ciesarik3 | 0:fb1547f2354e | 403 | /* Delay */ |
| Ciesarik3 | 0:fb1547f2354e | 404 | for (index = 0; index<1000; index++); |
| Ciesarik3 | 0:fb1547f2354e | 405 | |
| Ciesarik3 | 0:fb1547f2354e | 406 | /* PALL command */ |
| Ciesarik3 | 0:fb1547f2354e | 407 | FMC_Bank5_6->SDCMR = 0x00000012; |
| Ciesarik3 | 0:fb1547f2354e | 408 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 409 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 410 | { |
| Ciesarik3 | 0:fb1547f2354e | 411 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 412 | } |
| Ciesarik3 | 0:fb1547f2354e | 413 | |
| Ciesarik3 | 0:fb1547f2354e | 414 | /* Auto refresh command */ |
| Ciesarik3 | 0:fb1547f2354e | 415 | FMC_Bank5_6->SDCMR = 0x00000073; |
| Ciesarik3 | 0:fb1547f2354e | 416 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 417 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 418 | { |
| Ciesarik3 | 0:fb1547f2354e | 419 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 420 | } |
| Ciesarik3 | 0:fb1547f2354e | 421 | |
| Ciesarik3 | 0:fb1547f2354e | 422 | /* MRD register program */ |
| Ciesarik3 | 0:fb1547f2354e | 423 | FMC_Bank5_6->SDCMR = 0x00046014; |
| Ciesarik3 | 0:fb1547f2354e | 424 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 425 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 426 | { |
| Ciesarik3 | 0:fb1547f2354e | 427 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 428 | } |
| Ciesarik3 | 0:fb1547f2354e | 429 | |
| Ciesarik3 | 0:fb1547f2354e | 430 | /* Set refresh count */ |
| Ciesarik3 | 0:fb1547f2354e | 431 | tmpreg = FMC_Bank5_6->SDRTR; |
| Ciesarik3 | 0:fb1547f2354e | 432 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| Ciesarik3 | 0:fb1547f2354e | 433 | |
| Ciesarik3 | 0:fb1547f2354e | 434 | /* Disable write protection */ |
| Ciesarik3 | 0:fb1547f2354e | 435 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| Ciesarik3 | 0:fb1547f2354e | 436 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| Ciesarik3 | 0:fb1547f2354e | 437 | |
| Ciesarik3 | 0:fb1547f2354e | 438 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| Ciesarik3 | 0:fb1547f2354e | 439 | /* Configure and enable Bank1_SRAM2 */ |
| Ciesarik3 | 0:fb1547f2354e | 440 | FMC_Bank1->BTCR[2] = 0x00001011; |
| Ciesarik3 | 0:fb1547f2354e | 441 | FMC_Bank1->BTCR[3] = 0x00000201; |
| Ciesarik3 | 0:fb1547f2354e | 442 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Ciesarik3 | 0:fb1547f2354e | 443 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| Ciesarik3 | 0:fb1547f2354e | 444 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 445 | /* Configure and enable Bank1_SRAM2 */ |
| Ciesarik3 | 0:fb1547f2354e | 446 | FMC_Bank1->BTCR[2] = 0x00001091; |
| Ciesarik3 | 0:fb1547f2354e | 447 | FMC_Bank1->BTCR[3] = 0x00110212; |
| Ciesarik3 | 0:fb1547f2354e | 448 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Ciesarik3 | 0:fb1547f2354e | 449 | #endif /* STM32F469xx || STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 450 | |
| Ciesarik3 | 0:fb1547f2354e | 451 | (void)(tmp); |
| Ciesarik3 | 0:fb1547f2354e | 452 | } |
| Ciesarik3 | 0:fb1547f2354e | 453 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 454 | #elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 455 | /** |
| Ciesarik3 | 0:fb1547f2354e | 456 | * @brief Setup the external memory controller. |
| Ciesarik3 | 0:fb1547f2354e | 457 | * Called in startup_stm32f4xx.s before jump to main. |
| Ciesarik3 | 0:fb1547f2354e | 458 | * This function configures the external memories (SRAM/SDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 459 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| Ciesarik3 | 0:fb1547f2354e | 460 | * @param None |
| Ciesarik3 | 0:fb1547f2354e | 461 | * @retval None |
| Ciesarik3 | 0:fb1547f2354e | 462 | */ |
| Ciesarik3 | 0:fb1547f2354e | 463 | void SystemInit_ExtMemCtl(void) |
| Ciesarik3 | 0:fb1547f2354e | 464 | { |
| Ciesarik3 | 0:fb1547f2354e | 465 | __IO uint32_t tmp = 0x00; |
| Ciesarik3 | 0:fb1547f2354e | 466 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 467 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 468 | #if defined (DATA_IN_ExtSDRAM) |
| Ciesarik3 | 0:fb1547f2354e | 469 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 470 | register __IO uint32_t index; |
| Ciesarik3 | 0:fb1547f2354e | 471 | |
| Ciesarik3 | 0:fb1547f2354e | 472 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 473 | /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface |
| Ciesarik3 | 0:fb1547f2354e | 474 | clock */ |
| Ciesarik3 | 0:fb1547f2354e | 475 | RCC->AHB1ENR |= 0x0000007D; |
| Ciesarik3 | 0:fb1547f2354e | 476 | #else |
| Ciesarik3 | 0:fb1547f2354e | 477 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| Ciesarik3 | 0:fb1547f2354e | 478 | clock */ |
| Ciesarik3 | 0:fb1547f2354e | 479 | RCC->AHB1ENR |= 0x000001F8; |
| Ciesarik3 | 0:fb1547f2354e | 480 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 481 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 482 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); |
| Ciesarik3 | 0:fb1547f2354e | 483 | |
| Ciesarik3 | 0:fb1547f2354e | 484 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 485 | /* Connect PAx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 486 | GPIOA->AFR[0] |= 0xC0000000; |
| Ciesarik3 | 0:fb1547f2354e | 487 | GPIOA->AFR[1] |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 488 | /* Configure PDx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 489 | GPIOA->MODER |= 0x00008000; |
| Ciesarik3 | 0:fb1547f2354e | 490 | /* Configure PDx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 491 | GPIOA->OSPEEDR |= 0x00008000; |
| Ciesarik3 | 0:fb1547f2354e | 492 | /* Configure PDx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 493 | GPIOA->OTYPER |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 494 | /* No pull-up, pull-down for PDx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 495 | GPIOA->PUPDR |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 496 | |
| Ciesarik3 | 0:fb1547f2354e | 497 | /* Connect PCx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 498 | GPIOC->AFR[0] |= 0x00CC0000; |
| Ciesarik3 | 0:fb1547f2354e | 499 | GPIOC->AFR[1] |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 500 | /* Configure PDx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 501 | GPIOC->MODER |= 0x00000A00; |
| Ciesarik3 | 0:fb1547f2354e | 502 | /* Configure PDx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 503 | GPIOC->OSPEEDR |= 0x00000A00; |
| Ciesarik3 | 0:fb1547f2354e | 504 | /* Configure PDx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 505 | GPIOC->OTYPER |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 506 | /* No pull-up, pull-down for PDx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 507 | GPIOC->PUPDR |= 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 508 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 509 | |
| Ciesarik3 | 0:fb1547f2354e | 510 | /* Connect PDx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 511 | GPIOD->AFR[0] = 0x000000CC; |
| Ciesarik3 | 0:fb1547f2354e | 512 | GPIOD->AFR[1] = 0xCC000CCC; |
| Ciesarik3 | 0:fb1547f2354e | 513 | /* Configure PDx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 514 | GPIOD->MODER = 0xA02A000A; |
| Ciesarik3 | 0:fb1547f2354e | 515 | /* Configure PDx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 516 | GPIOD->OSPEEDR = 0xA02A000A; |
| Ciesarik3 | 0:fb1547f2354e | 517 | /* Configure PDx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 518 | GPIOD->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 519 | /* No pull-up, pull-down for PDx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 520 | GPIOD->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 521 | |
| Ciesarik3 | 0:fb1547f2354e | 522 | /* Connect PEx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 523 | GPIOE->AFR[0] = 0xC00000CC; |
| Ciesarik3 | 0:fb1547f2354e | 524 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 525 | /* Configure PEx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 526 | GPIOE->MODER = 0xAAAA800A; |
| Ciesarik3 | 0:fb1547f2354e | 527 | /* Configure PEx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 528 | GPIOE->OSPEEDR = 0xAAAA800A; |
| Ciesarik3 | 0:fb1547f2354e | 529 | /* Configure PEx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 530 | GPIOE->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 531 | /* No pull-up, pull-down for PEx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 532 | GPIOE->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 533 | |
| Ciesarik3 | 0:fb1547f2354e | 534 | /* Connect PFx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 535 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 536 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 537 | /* Configure PFx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 538 | GPIOF->MODER = 0xAA800AAA; |
| Ciesarik3 | 0:fb1547f2354e | 539 | /* Configure PFx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 540 | GPIOF->OSPEEDR = 0xAA800AAA; |
| Ciesarik3 | 0:fb1547f2354e | 541 | /* Configure PFx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 542 | GPIOF->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 543 | /* No pull-up, pull-down for PFx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 544 | GPIOF->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 545 | |
| Ciesarik3 | 0:fb1547f2354e | 546 | /* Connect PGx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 547 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 548 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 549 | /* Configure PGx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 550 | GPIOG->MODER = 0xAAAAAAAA; |
| Ciesarik3 | 0:fb1547f2354e | 551 | /* Configure PGx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 552 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| Ciesarik3 | 0:fb1547f2354e | 553 | /* Configure PGx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 554 | GPIOG->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 555 | /* No pull-up, pull-down for PGx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 556 | GPIOG->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 557 | |
| Ciesarik3 | 0:fb1547f2354e | 558 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 559 | || defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 560 | /* Connect PHx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 561 | GPIOH->AFR[0] = 0x00C0CC00; |
| Ciesarik3 | 0:fb1547f2354e | 562 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 563 | /* Configure PHx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 564 | GPIOH->MODER = 0xAAAA08A0; |
| Ciesarik3 | 0:fb1547f2354e | 565 | /* Configure PHx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 566 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| Ciesarik3 | 0:fb1547f2354e | 567 | /* Configure PHx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 568 | GPIOH->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 569 | /* No pull-up, pull-down for PHx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 570 | GPIOH->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 571 | |
| Ciesarik3 | 0:fb1547f2354e | 572 | /* Connect PIx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 573 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 574 | GPIOI->AFR[1] = 0x00000CC0; |
| Ciesarik3 | 0:fb1547f2354e | 575 | /* Configure PIx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 576 | GPIOI->MODER = 0x0028AAAA; |
| Ciesarik3 | 0:fb1547f2354e | 577 | /* Configure PIx pins speed to 50 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 578 | GPIOI->OSPEEDR = 0x0028AAAA; |
| Ciesarik3 | 0:fb1547f2354e | 579 | /* Configure PIx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 580 | GPIOI->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 581 | /* No pull-up, pull-down for PIx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 582 | GPIOI->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 583 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 584 | |
| Ciesarik3 | 0:fb1547f2354e | 585 | /*-- FMC Configuration -------------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 586 | /* Enable the FMC interface clock */ |
| Ciesarik3 | 0:fb1547f2354e | 587 | RCC->AHB3ENR |= 0x00000001; |
| Ciesarik3 | 0:fb1547f2354e | 588 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 589 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Ciesarik3 | 0:fb1547f2354e | 590 | |
| Ciesarik3 | 0:fb1547f2354e | 591 | /* Configure and enable SDRAM bank1 */ |
| Ciesarik3 | 0:fb1547f2354e | 592 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 593 | FMC_Bank5_6->SDCR[0] = 0x00001954; |
| Ciesarik3 | 0:fb1547f2354e | 594 | #else |
| Ciesarik3 | 0:fb1547f2354e | 595 | FMC_Bank5_6->SDCR[0] = 0x000019E4; |
| Ciesarik3 | 0:fb1547f2354e | 596 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 597 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| Ciesarik3 | 0:fb1547f2354e | 598 | |
| Ciesarik3 | 0:fb1547f2354e | 599 | /* SDRAM initialization sequence */ |
| Ciesarik3 | 0:fb1547f2354e | 600 | /* Clock enable command */ |
| Ciesarik3 | 0:fb1547f2354e | 601 | FMC_Bank5_6->SDCMR = 0x00000011; |
| Ciesarik3 | 0:fb1547f2354e | 602 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 603 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 604 | { |
| Ciesarik3 | 0:fb1547f2354e | 605 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 606 | } |
| Ciesarik3 | 0:fb1547f2354e | 607 | |
| Ciesarik3 | 0:fb1547f2354e | 608 | /* Delay */ |
| Ciesarik3 | 0:fb1547f2354e | 609 | for (index = 0; index<1000; index++); |
| Ciesarik3 | 0:fb1547f2354e | 610 | |
| Ciesarik3 | 0:fb1547f2354e | 611 | /* PALL command */ |
| Ciesarik3 | 0:fb1547f2354e | 612 | FMC_Bank5_6->SDCMR = 0x00000012; |
| Ciesarik3 | 0:fb1547f2354e | 613 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 614 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 615 | { |
| Ciesarik3 | 0:fb1547f2354e | 616 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 617 | } |
| Ciesarik3 | 0:fb1547f2354e | 618 | |
| Ciesarik3 | 0:fb1547f2354e | 619 | /* Auto refresh command */ |
| Ciesarik3 | 0:fb1547f2354e | 620 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 621 | FMC_Bank5_6->SDCMR = 0x000000F3; |
| Ciesarik3 | 0:fb1547f2354e | 622 | #else |
| Ciesarik3 | 0:fb1547f2354e | 623 | FMC_Bank5_6->SDCMR = 0x00000073; |
| Ciesarik3 | 0:fb1547f2354e | 624 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 625 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 626 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 627 | { |
| Ciesarik3 | 0:fb1547f2354e | 628 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 629 | } |
| Ciesarik3 | 0:fb1547f2354e | 630 | |
| Ciesarik3 | 0:fb1547f2354e | 631 | /* MRD register program */ |
| Ciesarik3 | 0:fb1547f2354e | 632 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 633 | FMC_Bank5_6->SDCMR = 0x00044014; |
| Ciesarik3 | 0:fb1547f2354e | 634 | #else |
| Ciesarik3 | 0:fb1547f2354e | 635 | FMC_Bank5_6->SDCMR = 0x00046014; |
| Ciesarik3 | 0:fb1547f2354e | 636 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 637 | timeout = 0xFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 638 | while((tmpreg != 0) && (timeout-- > 0)) |
| Ciesarik3 | 0:fb1547f2354e | 639 | { |
| Ciesarik3 | 0:fb1547f2354e | 640 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| Ciesarik3 | 0:fb1547f2354e | 641 | } |
| Ciesarik3 | 0:fb1547f2354e | 642 | |
| Ciesarik3 | 0:fb1547f2354e | 643 | /* Set refresh count */ |
| Ciesarik3 | 0:fb1547f2354e | 644 | tmpreg = FMC_Bank5_6->SDRTR; |
| Ciesarik3 | 0:fb1547f2354e | 645 | #if defined(STM32F446xx) |
| Ciesarik3 | 0:fb1547f2354e | 646 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); |
| Ciesarik3 | 0:fb1547f2354e | 647 | #else |
| Ciesarik3 | 0:fb1547f2354e | 648 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| Ciesarik3 | 0:fb1547f2354e | 649 | #endif /* STM32F446xx */ |
| Ciesarik3 | 0:fb1547f2354e | 650 | |
| Ciesarik3 | 0:fb1547f2354e | 651 | /* Disable write protection */ |
| Ciesarik3 | 0:fb1547f2354e | 652 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| Ciesarik3 | 0:fb1547f2354e | 653 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| Ciesarik3 | 0:fb1547f2354e | 654 | #endif /* DATA_IN_ExtSDRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 655 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 656 | |
| Ciesarik3 | 0:fb1547f2354e | 657 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 658 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 659 | || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Ciesarik3 | 0:fb1547f2354e | 660 | |
| Ciesarik3 | 0:fb1547f2354e | 661 | #if defined(DATA_IN_ExtSRAM) |
| Ciesarik3 | 0:fb1547f2354e | 662 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 663 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| Ciesarik3 | 0:fb1547f2354e | 664 | RCC->AHB1ENR |= 0x00000078; |
| Ciesarik3 | 0:fb1547f2354e | 665 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 666 | tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); |
| Ciesarik3 | 0:fb1547f2354e | 667 | |
| Ciesarik3 | 0:fb1547f2354e | 668 | /* Connect PDx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 669 | GPIOD->AFR[0] = 0x00CCC0CC; |
| Ciesarik3 | 0:fb1547f2354e | 670 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 671 | /* Configure PDx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 672 | GPIOD->MODER = 0xAAAA0A8A; |
| Ciesarik3 | 0:fb1547f2354e | 673 | /* Configure PDx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 674 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| Ciesarik3 | 0:fb1547f2354e | 675 | /* Configure PDx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 676 | GPIOD->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 677 | /* No pull-up, pull-down for PDx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 678 | GPIOD->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 679 | |
| Ciesarik3 | 0:fb1547f2354e | 680 | /* Connect PEx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 681 | GPIOE->AFR[0] = 0xC00CC0CC; |
| Ciesarik3 | 0:fb1547f2354e | 682 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 683 | /* Configure PEx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 684 | GPIOE->MODER = 0xAAAA828A; |
| Ciesarik3 | 0:fb1547f2354e | 685 | /* Configure PEx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 686 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| Ciesarik3 | 0:fb1547f2354e | 687 | /* Configure PEx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 688 | GPIOE->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 689 | /* No pull-up, pull-down for PEx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 690 | GPIOE->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 691 | |
| Ciesarik3 | 0:fb1547f2354e | 692 | /* Connect PFx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 693 | GPIOF->AFR[0] = 0x00CCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 694 | GPIOF->AFR[1] = 0xCCCC0000; |
| Ciesarik3 | 0:fb1547f2354e | 695 | /* Configure PFx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 696 | GPIOF->MODER = 0xAA000AAA; |
| Ciesarik3 | 0:fb1547f2354e | 697 | /* Configure PFx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 698 | GPIOF->OSPEEDR = 0xFF000FFF; |
| Ciesarik3 | 0:fb1547f2354e | 699 | /* Configure PFx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 700 | GPIOF->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 701 | /* No pull-up, pull-down for PFx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 702 | GPIOF->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 703 | |
| Ciesarik3 | 0:fb1547f2354e | 704 | /* Connect PGx pins to FMC Alternate function */ |
| Ciesarik3 | 0:fb1547f2354e | 705 | GPIOG->AFR[0] = 0x00CCCCCC; |
| Ciesarik3 | 0:fb1547f2354e | 706 | GPIOG->AFR[1] = 0x000000C0; |
| Ciesarik3 | 0:fb1547f2354e | 707 | /* Configure PGx pins in Alternate function mode */ |
| Ciesarik3 | 0:fb1547f2354e | 708 | GPIOG->MODER = 0x00085AAA; |
| Ciesarik3 | 0:fb1547f2354e | 709 | /* Configure PGx pins speed to 100 MHz */ |
| Ciesarik3 | 0:fb1547f2354e | 710 | GPIOG->OSPEEDR = 0x000CAFFF; |
| Ciesarik3 | 0:fb1547f2354e | 711 | /* Configure PGx pins Output type to push-pull */ |
| Ciesarik3 | 0:fb1547f2354e | 712 | GPIOG->OTYPER = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 713 | /* No pull-up, pull-down for PGx pins */ |
| Ciesarik3 | 0:fb1547f2354e | 714 | GPIOG->PUPDR = 0x00000000; |
| Ciesarik3 | 0:fb1547f2354e | 715 | |
| Ciesarik3 | 0:fb1547f2354e | 716 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| Ciesarik3 | 0:fb1547f2354e | 717 | /* Enable the FMC/FSMC interface clock */ |
| Ciesarik3 | 0:fb1547f2354e | 718 | RCC->AHB3ENR |= 0x00000001; |
| Ciesarik3 | 0:fb1547f2354e | 719 | |
| Ciesarik3 | 0:fb1547f2354e | 720 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| Ciesarik3 | 0:fb1547f2354e | 721 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 722 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Ciesarik3 | 0:fb1547f2354e | 723 | /* Configure and enable Bank1_SRAM2 */ |
| Ciesarik3 | 0:fb1547f2354e | 724 | FMC_Bank1->BTCR[2] = 0x00001011; |
| Ciesarik3 | 0:fb1547f2354e | 725 | FMC_Bank1->BTCR[3] = 0x00000201; |
| Ciesarik3 | 0:fb1547f2354e | 726 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Ciesarik3 | 0:fb1547f2354e | 727 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| Ciesarik3 | 0:fb1547f2354e | 728 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| Ciesarik3 | 0:fb1547f2354e | 729 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 730 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); |
| Ciesarik3 | 0:fb1547f2354e | 731 | /* Configure and enable Bank1_SRAM2 */ |
| Ciesarik3 | 0:fb1547f2354e | 732 | FMC_Bank1->BTCR[2] = 0x00001091; |
| Ciesarik3 | 0:fb1547f2354e | 733 | FMC_Bank1->BTCR[3] = 0x00110212; |
| Ciesarik3 | 0:fb1547f2354e | 734 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| Ciesarik3 | 0:fb1547f2354e | 735 | #endif /* STM32F469xx || STM32F479xx */ |
| Ciesarik3 | 0:fb1547f2354e | 736 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ |
| Ciesarik3 | 0:fb1547f2354e | 737 | || defined(STM32F412Zx) || defined(STM32F412Vx) |
| Ciesarik3 | 0:fb1547f2354e | 738 | /* Delay after an RCC peripheral clock enabling */ |
| Ciesarik3 | 0:fb1547f2354e | 739 | tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); |
| Ciesarik3 | 0:fb1547f2354e | 740 | /* Configure and enable Bank1_SRAM2 */ |
| Ciesarik3 | 0:fb1547f2354e | 741 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| Ciesarik3 | 0:fb1547f2354e | 742 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| Ciesarik3 | 0:fb1547f2354e | 743 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| Ciesarik3 | 0:fb1547f2354e | 744 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ |
| Ciesarik3 | 0:fb1547f2354e | 745 | |
| Ciesarik3 | 0:fb1547f2354e | 746 | #endif /* DATA_IN_ExtSRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 747 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
| Ciesarik3 | 0:fb1547f2354e | 748 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ |
| Ciesarik3 | 0:fb1547f2354e | 749 | (void)(tmp); |
| Ciesarik3 | 0:fb1547f2354e | 750 | } |
| Ciesarik3 | 0:fb1547f2354e | 751 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| Ciesarik3 | 0:fb1547f2354e | 752 | /** |
| Ciesarik3 | 0:fb1547f2354e | 753 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 754 | */ |
| Ciesarik3 | 0:fb1547f2354e | 755 | |
| Ciesarik3 | 0:fb1547f2354e | 756 | /** |
| Ciesarik3 | 0:fb1547f2354e | 757 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 758 | */ |
| Ciesarik3 | 0:fb1547f2354e | 759 | |
| Ciesarik3 | 0:fb1547f2354e | 760 | /** |
| Ciesarik3 | 0:fb1547f2354e | 761 | * @} |
| Ciesarik3 | 0:fb1547f2354e | 762 | */ |
| Ciesarik3 | 0:fb1547f2354e | 763 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |