Roman Ciesarík / bluenrg_interface

bluenrg_interface

stm32f4xx_hal_msp.c@0:fb1547f2354e, 2018-11-12 (annotated)

Committer:
Ciesarik3
Date:
Mon Nov 12 18:36:18 2018 +0000
Revision:
0:fb1547f2354e
crc;

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Ciesarik3 0:fb1547f2354e 1 /**
Ciesarik3 0:fb1547f2354e 2 ******************************************************************************
Ciesarik3 0:fb1547f2354e 3 * @file stm32f4xx_hal_msp.c
Ciesarik3 0:fb1547f2354e 4 * @author MCD Application Team
Ciesarik3 0:fb1547f2354e 5 * @version V1.5.0
Ciesarik3 0:fb1547f2354e 6 * @date 06-May-2016
Ciesarik3 0:fb1547f2354e 7 * @brief This file contains the HAL System and Peripheral (PPP) MSP initialization
Ciesarik3 0:fb1547f2354e 8 * and de-initialization functions.
Ciesarik3 0:fb1547f2354e 9 *******************************************************************************
Ciesarik3 0:fb1547f2354e 10 * @attention
Ciesarik3 0:fb1547f2354e 11 *
Ciesarik3 0:fb1547f2354e 12 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Ciesarik3 0:fb1547f2354e 13 *
Ciesarik3 0:fb1547f2354e 14 * Redistribution and use in source and binary forms, with or without modification,
Ciesarik3 0:fb1547f2354e 15 * are permitted provided that the following conditions are met:
Ciesarik3 0:fb1547f2354e 16 * 1. Redistributions of source code must retain the above copyright notice,
Ciesarik3 0:fb1547f2354e 17 * this list of conditions and the following disclaimer.
Ciesarik3 0:fb1547f2354e 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Ciesarik3 0:fb1547f2354e 19 * this list of conditions and the following disclaimer in the documentation
Ciesarik3 0:fb1547f2354e 20 * and/or other materials provided with the distribution.
Ciesarik3 0:fb1547f2354e 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Ciesarik3 0:fb1547f2354e 22 * may be used to endorse or promote products derived from this software
Ciesarik3 0:fb1547f2354e 23 * without specific prior written permission.
Ciesarik3 0:fb1547f2354e 24 *
Ciesarik3 0:fb1547f2354e 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Ciesarik3 0:fb1547f2354e 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Ciesarik3 0:fb1547f2354e 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Ciesarik3 0:fb1547f2354e 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Ciesarik3 0:fb1547f2354e 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Ciesarik3 0:fb1547f2354e 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Ciesarik3 0:fb1547f2354e 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Ciesarik3 0:fb1547f2354e 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Ciesarik3 0:fb1547f2354e 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Ciesarik3 0:fb1547f2354e 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Ciesarik3 0:fb1547f2354e 35 *
Ciesarik3 0:fb1547f2354e 36 ******************************************************************************
Ciesarik3 0:fb1547f2354e 37 */
Ciesarik3 0:fb1547f2354e 38
Ciesarik3 0:fb1547f2354e 39 /* Includes ------------------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 40 #include "stm32f4xx_nucleo_bluenrg.h"
Ciesarik3 0:fb1547f2354e 41
Ciesarik3 0:fb1547f2354e 42 /** @addtogroup X-CUBE-BLE1_Applications
Ciesarik3 0:fb1547f2354e 43 * @{
Ciesarik3 0:fb1547f2354e 44 */
Ciesarik3 0:fb1547f2354e 45
Ciesarik3 0:fb1547f2354e 46 /** @addtogroup SensorDemo
Ciesarik3 0:fb1547f2354e 47 * @{
Ciesarik3 0:fb1547f2354e 48 */
Ciesarik3 0:fb1547f2354e 49
Ciesarik3 0:fb1547f2354e 50 /** @defgroup STM32F4XX_HAL_MSP
Ciesarik3 0:fb1547f2354e 51 * @{
Ciesarik3 0:fb1547f2354e 52 */
Ciesarik3 0:fb1547f2354e 53
Ciesarik3 0:fb1547f2354e 54 /* Private typedef -----------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 55 /* Private define ------------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 56 /* Private macro -------------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 57 /* Private variables ---------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 58 /* Private function prototypes -----------------------------------------------*/
Ciesarik3 0:fb1547f2354e 59 /* Private functions ---------------------------------------------------------*/
Ciesarik3 0:fb1547f2354e 60
Ciesarik3 0:fb1547f2354e 61 /** @defgroup STM32F4XX_HAL_MSP_Private_Functions
Ciesarik3 0:fb1547f2354e 62 * @{
Ciesarik3 0:fb1547f2354e 63 */
Ciesarik3 0:fb1547f2354e 64
Ciesarik3 0:fb1547f2354e 65 /**
Ciesarik3 0:fb1547f2354e 66 * @brief This function is used for low level initialization of the SPI
Ciesarik3 0:fb1547f2354e 67 * communication with the BlueNRG Expansion Board.
Ciesarik3 0:fb1547f2354e 68 * @param hspi: SPI handle.
Ciesarik3 0:fb1547f2354e 69 * @retval None
Ciesarik3 0:fb1547f2354e 70 */
Ciesarik3 0:fb1547f2354e 71 void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
Ciesarik3 0:fb1547f2354e 72 {
Ciesarik3 0:fb1547f2354e 73 GPIO_InitTypeDef GPIO_InitStruct;
Ciesarik3 0:fb1547f2354e 74 if(hspi->Instance==BNRG_SPI_INSTANCE)
Ciesarik3 0:fb1547f2354e 75 {
Ciesarik3 0:fb1547f2354e 76 /* Enable peripherals clock */
Ciesarik3 0:fb1547f2354e 77
Ciesarik3 0:fb1547f2354e 78 /* Enable GPIO Ports Clock */
Ciesarik3 0:fb1547f2354e 79 BNRG_SPI_RESET_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 80 BNRG_SPI_SCLK_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 81 BNRG_SPI_MISO_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 82 BNRG_SPI_MOSI_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 83 BNRG_SPI_CS_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 84 BNRG_SPI_IRQ_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 85
Ciesarik3 0:fb1547f2354e 86 /* Enable SPI clock */
Ciesarik3 0:fb1547f2354e 87 BNRG_SPI_CLK_ENABLE();
Ciesarik3 0:fb1547f2354e 88
Ciesarik3 0:fb1547f2354e 89 /* Reset */
Ciesarik3 0:fb1547f2354e 90 GPIO_InitStruct.Pin = BNRG_SPI_RESET_PIN;
Ciesarik3 0:fb1547f2354e 91 GPIO_InitStruct.Mode = BNRG_SPI_RESET_MODE;
Ciesarik3 0:fb1547f2354e 92 GPIO_InitStruct.Pull = BNRG_SPI_RESET_PULL;
Ciesarik3 0:fb1547f2354e 93 GPIO_InitStruct.Speed = BNRG_SPI_RESET_SPEED;
Ciesarik3 0:fb1547f2354e 94 GPIO_InitStruct.Alternate = BNRG_SPI_RESET_ALTERNATE;
Ciesarik3 0:fb1547f2354e 95 HAL_GPIO_Init(BNRG_SPI_RESET_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 96 HAL_GPIO_WritePin(BNRG_SPI_RESET_PORT, BNRG_SPI_RESET_PIN, GPIO_PIN_RESET); /*Added to avoid spurious interrupt from the BlueNRG */
Ciesarik3 0:fb1547f2354e 97
Ciesarik3 0:fb1547f2354e 98 /* SCLK */
Ciesarik3 0:fb1547f2354e 99 GPIO_InitStruct.Pin = BNRG_SPI_SCLK_PIN;
Ciesarik3 0:fb1547f2354e 100 GPIO_InitStruct.Mode = BNRG_SPI_SCLK_MODE;
Ciesarik3 0:fb1547f2354e 101 GPIO_InitStruct.Pull = BNRG_SPI_SCLK_PULL;
Ciesarik3 0:fb1547f2354e 102 GPIO_InitStruct.Speed = BNRG_SPI_SCLK_SPEED;
Ciesarik3 0:fb1547f2354e 103 GPIO_InitStruct.Alternate = BNRG_SPI_SCLK_ALTERNATE;
Ciesarik3 0:fb1547f2354e 104 HAL_GPIO_Init(BNRG_SPI_SCLK_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 105
Ciesarik3 0:fb1547f2354e 106 /* MISO */
Ciesarik3 0:fb1547f2354e 107 GPIO_InitStruct.Pin = BNRG_SPI_MISO_PIN;
Ciesarik3 0:fb1547f2354e 108 GPIO_InitStruct.Mode = BNRG_SPI_MISO_MODE;
Ciesarik3 0:fb1547f2354e 109 GPIO_InitStruct.Pull = BNRG_SPI_MISO_PULL;
Ciesarik3 0:fb1547f2354e 110 GPIO_InitStruct.Speed = BNRG_SPI_MISO_SPEED;
Ciesarik3 0:fb1547f2354e 111 GPIO_InitStruct.Alternate = BNRG_SPI_MISO_ALTERNATE;
Ciesarik3 0:fb1547f2354e 112 HAL_GPIO_Init(BNRG_SPI_MISO_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 113
Ciesarik3 0:fb1547f2354e 114 /* MOSI */
Ciesarik3 0:fb1547f2354e 115 GPIO_InitStruct.Pin = BNRG_SPI_MOSI_PIN;
Ciesarik3 0:fb1547f2354e 116 GPIO_InitStruct.Mode = BNRG_SPI_MOSI_MODE;
Ciesarik3 0:fb1547f2354e 117 GPIO_InitStruct.Pull = BNRG_SPI_MOSI_PULL;
Ciesarik3 0:fb1547f2354e 118 GPIO_InitStruct.Speed = BNRG_SPI_MOSI_SPEED;
Ciesarik3 0:fb1547f2354e 119 GPIO_InitStruct.Alternate = BNRG_SPI_MOSI_ALTERNATE;
Ciesarik3 0:fb1547f2354e 120 HAL_GPIO_Init(BNRG_SPI_MOSI_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 121
Ciesarik3 0:fb1547f2354e 122 /* NSS/CSN/CS */
Ciesarik3 0:fb1547f2354e 123 GPIO_InitStruct.Pin = BNRG_SPI_CS_PIN;
Ciesarik3 0:fb1547f2354e 124 GPIO_InitStruct.Mode = BNRG_SPI_CS_MODE;
Ciesarik3 0:fb1547f2354e 125 GPIO_InitStruct.Pull = BNRG_SPI_CS_PULL;
Ciesarik3 0:fb1547f2354e 126 GPIO_InitStruct.Speed = BNRG_SPI_CS_SPEED;
Ciesarik3 0:fb1547f2354e 127 GPIO_InitStruct.Alternate = BNRG_SPI_CS_ALTERNATE;
Ciesarik3 0:fb1547f2354e 128 HAL_GPIO_Init(BNRG_SPI_CS_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 129 HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_SET);
Ciesarik3 0:fb1547f2354e 130
Ciesarik3 0:fb1547f2354e 131 /* IRQ -- INPUT */
Ciesarik3 0:fb1547f2354e 132 GPIO_InitStruct.Pin = BNRG_SPI_IRQ_PIN;
Ciesarik3 0:fb1547f2354e 133 GPIO_InitStruct.Mode = BNRG_SPI_IRQ_MODE;
Ciesarik3 0:fb1547f2354e 134 GPIO_InitStruct.Pull = BNRG_SPI_IRQ_PULL;
Ciesarik3 0:fb1547f2354e 135 GPIO_InitStruct.Speed = BNRG_SPI_IRQ_SPEED;
Ciesarik3 0:fb1547f2354e 136 GPIO_InitStruct.Alternate = BNRG_SPI_IRQ_ALTERNATE;
Ciesarik3 0:fb1547f2354e 137 HAL_GPIO_Init(BNRG_SPI_IRQ_PORT, &GPIO_InitStruct);
Ciesarik3 0:fb1547f2354e 138
Ciesarik3 0:fb1547f2354e 139 /* Configure the NVIC for SPI */
Ciesarik3 0:fb1547f2354e 140 HAL_NVIC_SetPriority(BNRG_SPI_EXTI_IRQn, 3, 0);
Ciesarik3 0:fb1547f2354e 141 HAL_NVIC_EnableIRQ(BNRG_SPI_EXTI_IRQn);
Ciesarik3 0:fb1547f2354e 142 }
Ciesarik3 0:fb1547f2354e 143 }
Ciesarik3 0:fb1547f2354e 144
Ciesarik3 0:fb1547f2354e 145 /**
Ciesarik3 0:fb1547f2354e 146 * @}
Ciesarik3 0:fb1547f2354e 147 */
Ciesarik3 0:fb1547f2354e 148
Ciesarik3 0:fb1547f2354e 149 /**
Ciesarik3 0:fb1547f2354e 150 * @}
Ciesarik3 0:fb1547f2354e 151 */
Ciesarik3 0:fb1547f2354e 152
Ciesarik3 0:fb1547f2354e 153 /**
Ciesarik3 0:fb1547f2354e 154 * @}
Ciesarik3 0:fb1547f2354e 155 */
Ciesarik3 0:fb1547f2354e 156
Ciesarik3 0:fb1547f2354e 157 /**
Ciesarik3 0:fb1547f2354e 158 * @}
Ciesarik3 0:fb1547f2354e 159 */
Ciesarik3 0:fb1547f2354e 160
Ciesarik3 0:fb1547f2354e 161 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/