Allan Brignoli / Mbed 2 deprecated Rome2_P6

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Dependencies:   mbed

EncoderCounter.cpp@0:1a0321f1ffbc, 2018-05-18 (annotated)

Committer:
Brignall
Date:
Fri May 18 12:18:21 2018 +0000
Revision:
0:1a0321f1ffbc
lala;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Brignall 0:1a0321f1ffbc 1 /*
Brignall 0:1a0321f1ffbc 2 * EncoderCounter.cpp
Brignall 0:1a0321f1ffbc 3 * Copyright (c) 2018, ZHAW
Brignall 0:1a0321f1ffbc 4 * All rights reserved.
Brignall 0:1a0321f1ffbc 5 */
Brignall 0:1a0321f1ffbc 6
Brignall 0:1a0321f1ffbc 7 #include "EncoderCounter.h"
Brignall 0:1a0321f1ffbc 8
Brignall 0:1a0321f1ffbc 9 using namespace std;
Brignall 0:1a0321f1ffbc 10
Brignall 0:1a0321f1ffbc 11 /**
Brignall 0:1a0321f1ffbc 12 * Creates and initializes the driver to read the quadrature
Brignall 0:1a0321f1ffbc 13 * encoder counter of the STM32 microcontroller.
Brignall 0:1a0321f1ffbc 14 * @param a the input pin for the channel A.
Brignall 0:1a0321f1ffbc 15 * @param b the input pin for the channel B.
Brignall 0:1a0321f1ffbc 16 */
Brignall 0:1a0321f1ffbc 17 EncoderCounter::EncoderCounter(PinName a, PinName b) {
Brignall 0:1a0321f1ffbc 18
Brignall 0:1a0321f1ffbc 19 // check pins
Brignall 0:1a0321f1ffbc 20
Brignall 0:1a0321f1ffbc 21 if ((a == PA_0) && (b == PA_1)) {
Brignall 0:1a0321f1ffbc 22
Brignall 0:1a0321f1ffbc 23 // pinmap OK for TIM2 CH1 and CH2
Brignall 0:1a0321f1ffbc 24
Brignall 0:1a0321f1ffbc 25 TIM = TIM2;
Brignall 0:1a0321f1ffbc 26
Brignall 0:1a0321f1ffbc 27 // configure general purpose I/O registers
Brignall 0:1a0321f1ffbc 28
Brignall 0:1a0321f1ffbc 29 GPIOA->MODER &= ~GPIO_MODER_MODER0; // reset port A0
Brignall 0:1a0321f1ffbc 30 GPIOA->MODER |= GPIO_MODER_MODER0_1; // set alternate mode of port A0
Brignall 0:1a0321f1ffbc 31 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR0; // reset pull-up/pull-down on port A0
Brignall 0:1a0321f1ffbc 32 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR0_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 33 GPIOA->AFR[0] &= ~(0xF << 4*0); // reset alternate function of port A0
Brignall 0:1a0321f1ffbc 34 GPIOA->AFR[0] |= 1 << 4*0; // set alternate funtion 1 of port A0
Brignall 0:1a0321f1ffbc 35
Brignall 0:1a0321f1ffbc 36 GPIOA->MODER &= ~GPIO_MODER_MODER1; // reset port A1
Brignall 0:1a0321f1ffbc 37 GPIOA->MODER |= GPIO_MODER_MODER1_1; // set alternate mode of port A1
Brignall 0:1a0321f1ffbc 38 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR1; // reset pull-up/pull-down on port A1
Brignall 0:1a0321f1ffbc 39 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR1_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 40 GPIOA->AFR[0] &= ~(0xF << 4*1); // reset alternate function of port A1
Brignall 0:1a0321f1ffbc 41 GPIOA->AFR[0] |= 1 << 4*1; // set alternate funtion 1 of port A1
Brignall 0:1a0321f1ffbc 42
Brignall 0:1a0321f1ffbc 43 // configure reset and clock control registers
Brignall 0:1a0321f1ffbc 44
Brignall 0:1a0321f1ffbc 45 RCC->APB1RSTR |= RCC_APB1RSTR_TIM2RST; //reset TIM2 controller
Brignall 0:1a0321f1ffbc 46 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM2RST;
Brignall 0:1a0321f1ffbc 47
Brignall 0:1a0321f1ffbc 48 RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; // TIM2 clock enable
Brignall 0:1a0321f1ffbc 49
Brignall 0:1a0321f1ffbc 50 } else if ((a == PA_6) && (b == PC_7)) {
Brignall 0:1a0321f1ffbc 51
Brignall 0:1a0321f1ffbc 52 // pinmap OK for TIM3 CH1 and CH2
Brignall 0:1a0321f1ffbc 53
Brignall 0:1a0321f1ffbc 54 TIM = TIM3;
Brignall 0:1a0321f1ffbc 55
Brignall 0:1a0321f1ffbc 56 // configure reset and clock control registers
Brignall 0:1a0321f1ffbc 57
Brignall 0:1a0321f1ffbc 58 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; // manually enable port C (port A enabled by mbed library)
Brignall 0:1a0321f1ffbc 59
Brignall 0:1a0321f1ffbc 60 // configure general purpose I/O registers
Brignall 0:1a0321f1ffbc 61
Brignall 0:1a0321f1ffbc 62 GPIOA->MODER &= ~GPIO_MODER_MODER6; // reset port A6
Brignall 0:1a0321f1ffbc 63 GPIOA->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port A6
Brignall 0:1a0321f1ffbc 64 GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port A6
Brignall 0:1a0321f1ffbc 65 GPIOA->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 66 GPIOA->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port A6
Brignall 0:1a0321f1ffbc 67 GPIOA->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port A6
Brignall 0:1a0321f1ffbc 68
Brignall 0:1a0321f1ffbc 69 GPIOC->MODER &= ~GPIO_MODER_MODER7; // reset port C7
Brignall 0:1a0321f1ffbc 70 GPIOC->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port C7
Brignall 0:1a0321f1ffbc 71 GPIOC->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port C7
Brignall 0:1a0321f1ffbc 72 GPIOC->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 73 GPIOC->AFR[0] &= ~0xF0000000; // reset alternate function of port C7
Brignall 0:1a0321f1ffbc 74 GPIOC->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port C7
Brignall 0:1a0321f1ffbc 75
Brignall 0:1a0321f1ffbc 76 // configure reset and clock control registers
Brignall 0:1a0321f1ffbc 77
Brignall 0:1a0321f1ffbc 78 RCC->APB1RSTR |= RCC_APB1RSTR_TIM3RST; //reset TIM3 controller
Brignall 0:1a0321f1ffbc 79 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM3RST;
Brignall 0:1a0321f1ffbc 80
Brignall 0:1a0321f1ffbc 81 RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; // TIM3 clock enable
Brignall 0:1a0321f1ffbc 82
Brignall 0:1a0321f1ffbc 83 } else if ((a == PB_6) && (b == PB_7)) {
Brignall 0:1a0321f1ffbc 84
Brignall 0:1a0321f1ffbc 85 // pinmap OK for TIM4 CH1 and CH2
Brignall 0:1a0321f1ffbc 86
Brignall 0:1a0321f1ffbc 87 TIM = TIM4;
Brignall 0:1a0321f1ffbc 88
Brignall 0:1a0321f1ffbc 89 // configure reset and clock control registers
Brignall 0:1a0321f1ffbc 90
Brignall 0:1a0321f1ffbc 91 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; // manually enable port B (port A enabled by mbed library)
Brignall 0:1a0321f1ffbc 92
Brignall 0:1a0321f1ffbc 93 // configure general purpose I/O registers
Brignall 0:1a0321f1ffbc 94
Brignall 0:1a0321f1ffbc 95 GPIOB->MODER &= ~GPIO_MODER_MODER6; // reset port B6
Brignall 0:1a0321f1ffbc 96 GPIOB->MODER |= GPIO_MODER_MODER6_1; // set alternate mode of port B6
Brignall 0:1a0321f1ffbc 97 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR6; // reset pull-up/pull-down on port B6
Brignall 0:1a0321f1ffbc 98 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR6_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 99 GPIOB->AFR[0] &= ~(0xF << 4*6); // reset alternate function of port B6
Brignall 0:1a0321f1ffbc 100 GPIOB->AFR[0] |= 2 << 4*6; // set alternate funtion 2 of port B6
Brignall 0:1a0321f1ffbc 101
Brignall 0:1a0321f1ffbc 102 GPIOB->MODER &= ~GPIO_MODER_MODER7; // reset port B7
Brignall 0:1a0321f1ffbc 103 GPIOB->MODER |= GPIO_MODER_MODER7_1; // set alternate mode of port B7
Brignall 0:1a0321f1ffbc 104 GPIOB->PUPDR &= ~GPIO_PUPDR_PUPDR7; // reset pull-up/pull-down on port B7
Brignall 0:1a0321f1ffbc 105 GPIOB->PUPDR |= GPIO_PUPDR_PUPDR7_1; // set input as pull-down
Brignall 0:1a0321f1ffbc 106 GPIOB->AFR[0] &= ~0xF0000000; // reset alternate function of port B7
Brignall 0:1a0321f1ffbc 107 GPIOB->AFR[0] |= 2 << 4*7; // set alternate funtion 2 of port B7
Brignall 0:1a0321f1ffbc 108
Brignall 0:1a0321f1ffbc 109 // configure reset and clock control registers
Brignall 0:1a0321f1ffbc 110
Brignall 0:1a0321f1ffbc 111 RCC->APB1RSTR |= RCC_APB1RSTR_TIM4RST; //reset TIM4 controller
Brignall 0:1a0321f1ffbc 112 RCC->APB1RSTR &= ~RCC_APB1RSTR_TIM4RST;
Brignall 0:1a0321f1ffbc 113
Brignall 0:1a0321f1ffbc 114 RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // TIM4 clock enable
Brignall 0:1a0321f1ffbc 115
Brignall 0:1a0321f1ffbc 116 } else {
Brignall 0:1a0321f1ffbc 117
Brignall 0:1a0321f1ffbc 118 printf("pinmap not found for peripheral\n");
Brignall 0:1a0321f1ffbc 119 }
Brignall 0:1a0321f1ffbc 120
Brignall 0:1a0321f1ffbc 121 // configure general purpose timer 3 or 4
Brignall 0:1a0321f1ffbc 122
Brignall 0:1a0321f1ffbc 123 TIM->CR1 = 0x0000; // counter disable
Brignall 0:1a0321f1ffbc 124 TIM->CR2 = 0x0000; // reset master mode selection
Brignall 0:1a0321f1ffbc 125 TIM->SMCR = TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0; // counting on both TI1 & TI2 edges
Brignall 0:1a0321f1ffbc 126 TIM->CCMR1 = TIM_CCMR1_CC2S_0 | TIM_CCMR1_CC1S_0;
Brignall 0:1a0321f1ffbc 127 TIM->CCMR2 = 0x0000; // reset capture mode register 2
Brignall 0:1a0321f1ffbc 128 TIM->CCER = TIM_CCER_CC2E | TIM_CCER_CC1E;
Brignall 0:1a0321f1ffbc 129 TIM->CNT = 0x0000; // reset counter value
Brignall 0:1a0321f1ffbc 130 TIM->ARR = 0xFFFF; // auto reload register
Brignall 0:1a0321f1ffbc 131 TIM->CR1 = TIM_CR1_CEN; // counter enable
Brignall 0:1a0321f1ffbc 132 }
Brignall 0:1a0321f1ffbc 133
Brignall 0:1a0321f1ffbc 134 EncoderCounter::~EncoderCounter() {}
Brignall 0:1a0321f1ffbc 135
Brignall 0:1a0321f1ffbc 136 /**
Brignall 0:1a0321f1ffbc 137 * Resets the counter value to zero.
Brignall 0:1a0321f1ffbc 138 */
Brignall 0:1a0321f1ffbc 139 void EncoderCounter::reset() {
Brignall 0:1a0321f1ffbc 140
Brignall 0:1a0321f1ffbc 141 TIM->CNT = 0x0000;
Brignall 0:1a0321f1ffbc 142 }
Brignall 0:1a0321f1ffbc 143
Brignall 0:1a0321f1ffbc 144 /**
Brignall 0:1a0321f1ffbc 145 * Resets the counter value to a given offset value.
Brignall 0:1a0321f1ffbc 146 * @param offset the offset value to reset the counter to.
Brignall 0:1a0321f1ffbc 147 */
Brignall 0:1a0321f1ffbc 148 void EncoderCounter::reset(short offset) {
Brignall 0:1a0321f1ffbc 149
Brignall 0:1a0321f1ffbc 150 TIM->CNT = -offset;
Brignall 0:1a0321f1ffbc 151 }
Brignall 0:1a0321f1ffbc 152
Brignall 0:1a0321f1ffbc 153 /**
Brignall 0:1a0321f1ffbc 154 * Reads the quadrature encoder counter value.
Brignall 0:1a0321f1ffbc 155 * @return the quadrature encoder counter as a signed 16-bit integer value.
Brignall 0:1a0321f1ffbc 156 */
Brignall 0:1a0321f1ffbc 157 short EncoderCounter::read() {
Brignall 0:1a0321f1ffbc 158
Brignall 0:1a0321f1ffbc 159 return (short)(-TIM->CNT);
Brignall 0:1a0321f1ffbc 160 }
Brignall 0:1a0321f1ffbc 161
Brignall 0:1a0321f1ffbc 162 /**
Brignall 0:1a0321f1ffbc 163 * The empty operator is a shorthand notation of the <code>read()</code> method.
Brignall 0:1a0321f1ffbc 164 */
Brignall 0:1a0321f1ffbc 165 EncoderCounter::operator short() {
Brignall 0:1a0321f1ffbc 166
Brignall 0:1a0321f1ffbc 167 return read();
Brignall 0:1a0321f1ffbc 168 }
Brignall 0:1a0321f1ffbc 169
Brignall 0:1a0321f1ffbc 170