Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/score_cm3.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /******************************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * @file: core_cm3.h
Michael J. Spencer 2:1df0b61d3b5a 3 * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Michael J. Spencer 2:1df0b61d3b5a 4 * @version: V1.30 PRE-RELEASE
Michael J. Spencer 2:1df0b61d3b5a 5 * @date: 30. July 2009
Michael J. Spencer 2:1df0b61d3b5a 6 *----------------------------------------------------------------------------
Michael J. Spencer 2:1df0b61d3b5a 7 *
Michael J. Spencer 2:1df0b61d3b5a 8 * Copyright (C) 2009 ARM Limited. All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 9 *
Michael J. Spencer 2:1df0b61d3b5a 10 * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
Michael J. Spencer 2:1df0b61d3b5a 11 * processor based microcontrollers. This file can be freely distributed
Michael J. Spencer 2:1df0b61d3b5a 12 * within development tools that are supporting such ARM based processors.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Michael J. Spencer 2:1df0b61d3b5a 15 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Michael J. Spencer 2:1df0b61d3b5a 16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Michael J. Spencer 2:1df0b61d3b5a 17 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Michael J. Spencer 2:1df0b61d3b5a 18 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Michael J. Spencer 2:1df0b61d3b5a 19 *
Michael J. Spencer 2:1df0b61d3b5a 20 ******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 21
Michael J. Spencer 2:1df0b61d3b5a 22 #ifndef __CM3_CORE_H__
Michael J. Spencer 2:1df0b61d3b5a 23 #define __CM3_CORE_H__
Michael J. Spencer 2:1df0b61d3b5a 24
Michael J. Spencer 2:1df0b61d3b5a 25 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 26 extern "C" {
Michael J. Spencer 2:1df0b61d3b5a 27 #endif
Michael J. Spencer 2:1df0b61d3b5a 28
Michael J. Spencer 2:1df0b61d3b5a 29 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
Michael J. Spencer 2:1df0b61d3b5a 30 #define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
Michael J. Spencer 2:1df0b61d3b5a 31 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #define __CORTEX_M (0x03) /*!< Cortex core */
Michael J. Spencer 2:1df0b61d3b5a 34
Michael J. Spencer 2:1df0b61d3b5a 35 /**
Michael J. Spencer 2:1df0b61d3b5a 36 * Lint configuration \n
Michael J. Spencer 2:1df0b61d3b5a 37 * ----------------------- \n
Michael J. Spencer 2:1df0b61d3b5a 38 *
Michael J. Spencer 2:1df0b61d3b5a 39 * The following Lint messages will be suppressed and not shown: \n
Michael J. Spencer 2:1df0b61d3b5a 40 * \n
Michael J. Spencer 2:1df0b61d3b5a 41 * --- Error 10: --- \n
Michael J. Spencer 2:1df0b61d3b5a 42 * register uint32_t __regBasePri __asm("basepri"); \n
Michael J. Spencer 2:1df0b61d3b5a 43 * Error 10: Expecting ';' \n
Michael J. Spencer 2:1df0b61d3b5a 44 * \n
Michael J. Spencer 2:1df0b61d3b5a 45 * --- Error 530: --- \n
Michael J. Spencer 2:1df0b61d3b5a 46 * return(__regBasePri); \n
Michael J. Spencer 2:1df0b61d3b5a 47 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
Michael J. Spencer 2:1df0b61d3b5a 48 * \n
Michael J. Spencer 2:1df0b61d3b5a 49 * --- Error 550: --- \n
Michael J. Spencer 2:1df0b61d3b5a 50 * __regBasePri = (basePri & 0x1ff); \n
Michael J. Spencer 2:1df0b61d3b5a 51 * } \n
Michael J. Spencer 2:1df0b61d3b5a 52 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
Michael J. Spencer 2:1df0b61d3b5a 53 * \n
Michael J. Spencer 2:1df0b61d3b5a 54 * --- Error 754: --- \n
Michael J. Spencer 2:1df0b61d3b5a 55 * uint32_t RESERVED0[24]; \n
Michael J. Spencer 2:1df0b61d3b5a 56 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
Michael J. Spencer 2:1df0b61d3b5a 57 * \n
Michael J. Spencer 2:1df0b61d3b5a 58 * --- Error 750: --- \n
Michael J. Spencer 2:1df0b61d3b5a 59 * #define __CM3_CORE_H__ \n
Michael J. Spencer 2:1df0b61d3b5a 60 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
Michael J. Spencer 2:1df0b61d3b5a 61 * \n
Michael J. Spencer 2:1df0b61d3b5a 62 * --- Error 528: --- \n
Michael J. Spencer 2:1df0b61d3b5a 63 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
Michael J. Spencer 2:1df0b61d3b5a 64 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
Michael J. Spencer 2:1df0b61d3b5a 65 * \n
Michael J. Spencer 2:1df0b61d3b5a 66 * --- Error 751: --- \n
Michael J. Spencer 2:1df0b61d3b5a 67 * } InterruptType_Type; \n
Michael J. Spencer 2:1df0b61d3b5a 68 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
Michael J. Spencer 2:1df0b61d3b5a 69 * \n
Michael J. Spencer 2:1df0b61d3b5a 70 * \n
Michael J. Spencer 2:1df0b61d3b5a 71 * Note: To re-enable a Message, insert a space before 'lint' * \n
Michael J. Spencer 2:1df0b61d3b5a 72 *
Michael J. Spencer 2:1df0b61d3b5a 73 */
Michael J. Spencer 2:1df0b61d3b5a 74
Michael J. Spencer 2:1df0b61d3b5a 75 /*lint -save */
Michael J. Spencer 2:1df0b61d3b5a 76 /*lint -e10 */
Michael J. Spencer 2:1df0b61d3b5a 77 /*lint -e530 */
Michael J. Spencer 2:1df0b61d3b5a 78 /*lint -e550 */
Michael J. Spencer 2:1df0b61d3b5a 79 /*lint -e754 */
Michael J. Spencer 2:1df0b61d3b5a 80 /*lint -e750 */
Michael J. Spencer 2:1df0b61d3b5a 81 /*lint -e528 */
Michael J. Spencer 2:1df0b61d3b5a 82 /*lint -e751 */
Michael J. Spencer 2:1df0b61d3b5a 83
Michael J. Spencer 2:1df0b61d3b5a 84
Michael J. Spencer 2:1df0b61d3b5a 85 #include <stdint.h> /* Include standard types */
Michael J. Spencer 2:1df0b61d3b5a 86
Michael J. Spencer 2:1df0b61d3b5a 87 #if defined (__ICCARM__)
Michael J. Spencer 2:1df0b61d3b5a 88 #include <intrinsics.h> /* IAR Intrinsics */
Michael J. Spencer 2:1df0b61d3b5a 89 #endif
Michael J. Spencer 2:1df0b61d3b5a 90
Michael J. Spencer 2:1df0b61d3b5a 91
Michael J. Spencer 2:1df0b61d3b5a 92 #ifndef __NVIC_PRIO_BITS
Michael J. Spencer 2:1df0b61d3b5a 93 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
Michael J. Spencer 2:1df0b61d3b5a 94 #endif
Michael J. Spencer 2:1df0b61d3b5a 95
Michael J. Spencer 2:1df0b61d3b5a 96
Michael J. Spencer 2:1df0b61d3b5a 97
Michael J. Spencer 2:1df0b61d3b5a 98
Michael J. Spencer 2:1df0b61d3b5a 99 /**
Michael J. Spencer 2:1df0b61d3b5a 100 * IO definitions
Michael J. Spencer 2:1df0b61d3b5a 101 *
Michael J. Spencer 2:1df0b61d3b5a 102 * define access restrictions to peripheral registers
Michael J. Spencer 2:1df0b61d3b5a 103 */
Michael J. Spencer 2:1df0b61d3b5a 104
Michael J. Spencer 2:1df0b61d3b5a 105 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 106 #define __I volatile /*!< defines 'read only' permissions */
Michael J. Spencer 2:1df0b61d3b5a 107 #else
Michael J. Spencer 2:1df0b61d3b5a 108 #define __I volatile const /*!< defines 'read only' permissions */
Michael J. Spencer 2:1df0b61d3b5a 109 #endif
Michael J. Spencer 2:1df0b61d3b5a 110 #define __O volatile /*!< defines 'write only' permissions */
Michael J. Spencer 2:1df0b61d3b5a 111 #define __IO volatile /*!< defines 'read / write' permissions */
Michael J. Spencer 2:1df0b61d3b5a 112
Michael J. Spencer 2:1df0b61d3b5a 113
Michael J. Spencer 2:1df0b61d3b5a 114
Michael J. Spencer 2:1df0b61d3b5a 115 /*******************************************************************************
Michael J. Spencer 2:1df0b61d3b5a 116 * Register Abstraction
Michael J. Spencer 2:1df0b61d3b5a 117 ******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 118
Michael J. Spencer 2:1df0b61d3b5a 119
Michael J. Spencer 2:1df0b61d3b5a 120 /* System Reset */
Michael J. Spencer 2:1df0b61d3b5a 121 #define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
Michael J. Spencer 2:1df0b61d3b5a 122 #define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
Michael J. Spencer 2:1df0b61d3b5a 123 #define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
Michael J. Spencer 2:1df0b61d3b5a 124 #define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
Michael J. Spencer 2:1df0b61d3b5a 125
Michael J. Spencer 2:1df0b61d3b5a 126 /* Core Debug */
Michael J. Spencer 2:1df0b61d3b5a 127 #define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
Michael J. Spencer 2:1df0b61d3b5a 128 #define ITM_TCR_ITMENA 1 /*!< ITM enable */
Michael J. Spencer 2:1df0b61d3b5a 129
Michael J. Spencer 2:1df0b61d3b5a 130
Michael J. Spencer 2:1df0b61d3b5a 131
Michael J. Spencer 2:1df0b61d3b5a 132
Michael J. Spencer 2:1df0b61d3b5a 133 /* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
Michael J. Spencer 2:1df0b61d3b5a 134 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 135 {
Michael J. Spencer 2:1df0b61d3b5a 136 __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
Michael J. Spencer 2:1df0b61d3b5a 137 uint32_t RESERVED0[24];
Michael J. Spencer 2:1df0b61d3b5a 138 __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
Michael J. Spencer 2:1df0b61d3b5a 139 uint32_t RSERVED1[24];
Michael J. Spencer 2:1df0b61d3b5a 140 __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
Michael J. Spencer 2:1df0b61d3b5a 141 uint32_t RESERVED2[24];
Michael J. Spencer 2:1df0b61d3b5a 142 __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
Michael J. Spencer 2:1df0b61d3b5a 143 uint32_t RESERVED3[24];
Michael J. Spencer 2:1df0b61d3b5a 144 __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
Michael J. Spencer 2:1df0b61d3b5a 145 uint32_t RESERVED4[56];
Michael J. Spencer 2:1df0b61d3b5a 146 __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
Michael J. Spencer 2:1df0b61d3b5a 147 uint32_t RESERVED5[644];
Michael J. Spencer 2:1df0b61d3b5a 148 __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
Michael J. Spencer 2:1df0b61d3b5a 149 } NVIC_Type;
Michael J. Spencer 2:1df0b61d3b5a 150
Michael J. Spencer 2:1df0b61d3b5a 151
Michael J. Spencer 2:1df0b61d3b5a 152 /* memory mapping struct for System Control Block */
Michael J. Spencer 2:1df0b61d3b5a 153 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 154 {
Michael J. Spencer 2:1df0b61d3b5a 155 __I uint32_t CPUID; /*!< CPU ID Base Register */
Michael J. Spencer 2:1df0b61d3b5a 156 __IO uint32_t ICSR; /*!< Interrupt Control State Register */
Michael J. Spencer 2:1df0b61d3b5a 157 __IO uint32_t VTOR; /*!< Vector Table Offset Register */
Michael J. Spencer 2:1df0b61d3b5a 158 __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
Michael J. Spencer 2:1df0b61d3b5a 159 __IO uint32_t SCR; /*!< System Control Register */
Michael J. Spencer 2:1df0b61d3b5a 160 __IO uint32_t CCR; /*!< Configuration Control Register */
Michael J. Spencer 2:1df0b61d3b5a 161 __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
Michael J. Spencer 2:1df0b61d3b5a 162 __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
Michael J. Spencer 2:1df0b61d3b5a 163 __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
Michael J. Spencer 2:1df0b61d3b5a 164 __IO uint32_t HFSR; /*!< Hard Fault Status Register */
Michael J. Spencer 2:1df0b61d3b5a 165 __IO uint32_t DFSR; /*!< Debug Fault Status Register */
Michael J. Spencer 2:1df0b61d3b5a 166 __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
Michael J. Spencer 2:1df0b61d3b5a 167 __IO uint32_t BFAR; /*!< Bus Fault Address Register */
Michael J. Spencer 2:1df0b61d3b5a 168 __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
Michael J. Spencer 2:1df0b61d3b5a 169 __I uint32_t PFR[2]; /*!< Processor Feature Register */
Michael J. Spencer 2:1df0b61d3b5a 170 __I uint32_t DFR; /*!< Debug Feature Register */
Michael J. Spencer 2:1df0b61d3b5a 171 __I uint32_t ADR; /*!< Auxiliary Feature Register */
Michael J. Spencer 2:1df0b61d3b5a 172 __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
Michael J. Spencer 2:1df0b61d3b5a 173 __I uint32_t ISAR[5]; /*!< ISA Feature Register */
Michael J. Spencer 2:1df0b61d3b5a 174 } SCB_Type;
Michael J. Spencer 2:1df0b61d3b5a 175
Michael J. Spencer 2:1df0b61d3b5a 176
Michael J. Spencer 2:1df0b61d3b5a 177 /* memory mapping struct for SysTick */
Michael J. Spencer 2:1df0b61d3b5a 178 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 179 {
Michael J. Spencer 2:1df0b61d3b5a 180 __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
Michael J. Spencer 2:1df0b61d3b5a 181 __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
Michael J. Spencer 2:1df0b61d3b5a 182 __IO uint32_t VAL; /*!< SysTick Current Value Register */
Michael J. Spencer 2:1df0b61d3b5a 183 __I uint32_t CALIB; /*!< SysTick Calibration Register */
Michael J. Spencer 2:1df0b61d3b5a 184 } SysTick_Type;
Michael J. Spencer 2:1df0b61d3b5a 185
Michael J. Spencer 2:1df0b61d3b5a 186
Michael J. Spencer 2:1df0b61d3b5a 187 /* memory mapping structur for ITM */
Michael J. Spencer 2:1df0b61d3b5a 188 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 189 {
Michael J. Spencer 2:1df0b61d3b5a 190 __O union
Michael J. Spencer 2:1df0b61d3b5a 191 {
Michael J. Spencer 2:1df0b61d3b5a 192 __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
Michael J. Spencer 2:1df0b61d3b5a 193 __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
Michael J. Spencer 2:1df0b61d3b5a 194 __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
Michael J. Spencer 2:1df0b61d3b5a 195 } PORT [32]; /*!< ITM Stimulus Port Registers */
Michael J. Spencer 2:1df0b61d3b5a 196 uint32_t RESERVED0[864];
Michael J. Spencer 2:1df0b61d3b5a 197 __IO uint32_t TER; /*!< ITM Trace Enable Register */
Michael J. Spencer 2:1df0b61d3b5a 198 uint32_t RESERVED1[15];
Michael J. Spencer 2:1df0b61d3b5a 199 __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
Michael J. Spencer 2:1df0b61d3b5a 200 uint32_t RESERVED2[15];
Michael J. Spencer 2:1df0b61d3b5a 201 __IO uint32_t TCR; /*!< ITM Trace Control Register */
Michael J. Spencer 2:1df0b61d3b5a 202 uint32_t RESERVED3[29];
Michael J. Spencer 2:1df0b61d3b5a 203 __IO uint32_t IWR; /*!< ITM Integration Write Register */
Michael J. Spencer 2:1df0b61d3b5a 204 __IO uint32_t IRR; /*!< ITM Integration Read Register */
Michael J. Spencer 2:1df0b61d3b5a 205 __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
Michael J. Spencer 2:1df0b61d3b5a 206 uint32_t RESERVED4[43];
Michael J. Spencer 2:1df0b61d3b5a 207 __IO uint32_t LAR; /*!< ITM Lock Access Register */
Michael J. Spencer 2:1df0b61d3b5a 208 __IO uint32_t LSR; /*!< ITM Lock Status Register */
Michael J. Spencer 2:1df0b61d3b5a 209 uint32_t RESERVED5[6];
Michael J. Spencer 2:1df0b61d3b5a 210 __I uint32_t PID4; /*!< ITM Product ID Registers */
Michael J. Spencer 2:1df0b61d3b5a 211 __I uint32_t PID5;
Michael J. Spencer 2:1df0b61d3b5a 212 __I uint32_t PID6;
Michael J. Spencer 2:1df0b61d3b5a 213 __I uint32_t PID7;
Michael J. Spencer 2:1df0b61d3b5a 214 __I uint32_t PID0;
Michael J. Spencer 2:1df0b61d3b5a 215 __I uint32_t PID1;
Michael J. Spencer 2:1df0b61d3b5a 216 __I uint32_t PID2;
Michael J. Spencer 2:1df0b61d3b5a 217 __I uint32_t PID3;
Michael J. Spencer 2:1df0b61d3b5a 218 __I uint32_t CID0;
Michael J. Spencer 2:1df0b61d3b5a 219 __I uint32_t CID1;
Michael J. Spencer 2:1df0b61d3b5a 220 __I uint32_t CID2;
Michael J. Spencer 2:1df0b61d3b5a 221 __I uint32_t CID3;
Michael J. Spencer 2:1df0b61d3b5a 222 } ITM_Type;
Michael J. Spencer 2:1df0b61d3b5a 223
Michael J. Spencer 2:1df0b61d3b5a 224
Michael J. Spencer 2:1df0b61d3b5a 225 /* memory mapped struct for Interrupt Type */
Michael J. Spencer 2:1df0b61d3b5a 226 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 227 {
Michael J. Spencer 2:1df0b61d3b5a 228 uint32_t RESERVED0;
Michael J. Spencer 2:1df0b61d3b5a 229 __I uint32_t ICTR; /*!< Interrupt Control Type Register */
Michael J. Spencer 2:1df0b61d3b5a 230 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Michael J. Spencer 2:1df0b61d3b5a 231 __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
Michael J. Spencer 2:1df0b61d3b5a 232 #else
Michael J. Spencer 2:1df0b61d3b5a 233 uint32_t RESERVED1;
Michael J. Spencer 2:1df0b61d3b5a 234 #endif
Michael J. Spencer 2:1df0b61d3b5a 235 } InterruptType_Type;
Michael J. Spencer 2:1df0b61d3b5a 236
Michael J. Spencer 2:1df0b61d3b5a 237
Michael J. Spencer 2:1df0b61d3b5a 238 /* Memory Protection Unit */
Michael J. Spencer 2:1df0b61d3b5a 239 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
Michael J. Spencer 2:1df0b61d3b5a 240 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 241 {
Michael J. Spencer 2:1df0b61d3b5a 242 __I uint32_t TYPE; /*!< MPU Type Register */
Michael J. Spencer 2:1df0b61d3b5a 243 __IO uint32_t CTRL; /*!< MPU Control Register */
Michael J. Spencer 2:1df0b61d3b5a 244 __IO uint32_t RNR; /*!< MPU Region RNRber Register */
Michael J. Spencer 2:1df0b61d3b5a 245 __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
Michael J. Spencer 2:1df0b61d3b5a 246 __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
Michael J. Spencer 2:1df0b61d3b5a 247 __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
Michael J. Spencer 2:1df0b61d3b5a 248 __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
Michael J. Spencer 2:1df0b61d3b5a 249 __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
Michael J. Spencer 2:1df0b61d3b5a 250 __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
Michael J. Spencer 2:1df0b61d3b5a 251 __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
Michael J. Spencer 2:1df0b61d3b5a 252 __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
Michael J. Spencer 2:1df0b61d3b5a 253 } MPU_Type;
Michael J. Spencer 2:1df0b61d3b5a 254 #endif
Michael J. Spencer 2:1df0b61d3b5a 255
Michael J. Spencer 2:1df0b61d3b5a 256
Michael J. Spencer 2:1df0b61d3b5a 257 /* Core Debug Register */
Michael J. Spencer 2:1df0b61d3b5a 258 typedef struct
Michael J. Spencer 2:1df0b61d3b5a 259 {
Michael J. Spencer 2:1df0b61d3b5a 260 __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
Michael J. Spencer 2:1df0b61d3b5a 261 __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
Michael J. Spencer 2:1df0b61d3b5a 262 __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
Michael J. Spencer 2:1df0b61d3b5a 263 __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
Michael J. Spencer 2:1df0b61d3b5a 264 } CoreDebug_Type;
Michael J. Spencer 2:1df0b61d3b5a 265
Michael J. Spencer 2:1df0b61d3b5a 266
Michael J. Spencer 2:1df0b61d3b5a 267 /* Memory mapping of Cortex-M3 Hardware */
Michael J. Spencer 2:1df0b61d3b5a 268 #define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
Michael J. Spencer 2:1df0b61d3b5a 269 #define ITM_BASE (0xE0000000) /*!< ITM Base Address */
Michael J. Spencer 2:1df0b61d3b5a 270 #define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
Michael J. Spencer 2:1df0b61d3b5a 271 #define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
Michael J. Spencer 2:1df0b61d3b5a 272 #define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
Michael J. Spencer 2:1df0b61d3b5a 273 #define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
Michael J. Spencer 2:1df0b61d3b5a 274
Michael J. Spencer 2:1df0b61d3b5a 275 #define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
Michael J. Spencer 2:1df0b61d3b5a 276 #define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
Michael J. Spencer 2:1df0b61d3b5a 277 #define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
Michael J. Spencer 2:1df0b61d3b5a 278 #define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
Michael J. Spencer 2:1df0b61d3b5a 279 #define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
Michael J. Spencer 2:1df0b61d3b5a 280 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
Michael J. Spencer 2:1df0b61d3b5a 281
Michael J. Spencer 2:1df0b61d3b5a 282 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
Michael J. Spencer 2:1df0b61d3b5a 283 #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
Michael J. Spencer 2:1df0b61d3b5a 284 #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
Michael J. Spencer 2:1df0b61d3b5a 285 #endif
Michael J. Spencer 2:1df0b61d3b5a 286
Michael J. Spencer 2:1df0b61d3b5a 287
Michael J. Spencer 2:1df0b61d3b5a 288 /*******************************************************************************
Michael J. Spencer 2:1df0b61d3b5a 289 * Hardware Abstraction Layer
Michael J. Spencer 2:1df0b61d3b5a 290 ******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 291
Michael J. Spencer 2:1df0b61d3b5a 292
Michael J. Spencer 2:1df0b61d3b5a 293 #if defined ( __CC_ARM )
Michael J. Spencer 2:1df0b61d3b5a 294 #define __ASM __asm /*!< asm keyword for ARM Compiler */
Michael J. Spencer 2:1df0b61d3b5a 295 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
Michael J. Spencer 2:1df0b61d3b5a 296
Michael J. Spencer 2:1df0b61d3b5a 297 #elif defined ( __ICCARM__ )
Michael J. Spencer 2:1df0b61d3b5a 298 #define __ASM __asm /*!< asm keyword for IAR Compiler */
Michael J. Spencer 2:1df0b61d3b5a 299 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
Michael J. Spencer 2:1df0b61d3b5a 300
Michael J. Spencer 2:1df0b61d3b5a 301 #elif defined ( __GNUC__ )
Michael J. Spencer 2:1df0b61d3b5a 302 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Michael J. Spencer 2:1df0b61d3b5a 303 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Michael J. Spencer 2:1df0b61d3b5a 304
Michael J. Spencer 2:1df0b61d3b5a 305 #elif defined ( __TASKING__ )
Michael J. Spencer 2:1df0b61d3b5a 306 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
Michael J. Spencer 2:1df0b61d3b5a 307 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
Michael J. Spencer 2:1df0b61d3b5a 308
Michael J. Spencer 2:1df0b61d3b5a 309 #endif
Michael J. Spencer 2:1df0b61d3b5a 310
Michael J. Spencer 2:1df0b61d3b5a 311
Michael J. Spencer 2:1df0b61d3b5a 312 /* ################### Compiler specific Intrinsics ########################### */
Michael J. Spencer 2:1df0b61d3b5a 313
Michael J. Spencer 2:1df0b61d3b5a 314 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Michael J. Spencer 2:1df0b61d3b5a 315 /* ARM armcc specific functions */
Michael J. Spencer 2:1df0b61d3b5a 316
Michael J. Spencer 2:1df0b61d3b5a 317 #define __enable_fault_irq __enable_fiq
Michael J. Spencer 2:1df0b61d3b5a 318 #define __disable_fault_irq __disable_fiq
Michael J. Spencer 2:1df0b61d3b5a 319
Michael J. Spencer 2:1df0b61d3b5a 320 #define __NOP __nop
Michael J. Spencer 2:1df0b61d3b5a 321 #define __WFI __wfi
Michael J. Spencer 2:1df0b61d3b5a 322 #define __WFE __wfe
Michael J. Spencer 2:1df0b61d3b5a 323 #define __SEV __sev
Michael J. Spencer 2:1df0b61d3b5a 324 #define __ISB() __isb(0)
Michael J. Spencer 2:1df0b61d3b5a 325 #define __DSB() __dsb(0)
Michael J. Spencer 2:1df0b61d3b5a 326 #define __DMB() __dmb(0)
Michael J. Spencer 2:1df0b61d3b5a 327 #define __REV __rev
Michael J. Spencer 2:1df0b61d3b5a 328 #define __RBIT __rbit
Michael J. Spencer 2:1df0b61d3b5a 329 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
Michael J. Spencer 2:1df0b61d3b5a 330 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
Michael J. Spencer 2:1df0b61d3b5a 331 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
Michael J. Spencer 2:1df0b61d3b5a 332 #define __STREXB(value, ptr) __strex(value, ptr)
Michael J. Spencer 2:1df0b61d3b5a 333 #define __STREXH(value, ptr) __strex(value, ptr)
Michael J. Spencer 2:1df0b61d3b5a 334 #define __STREXW(value, ptr) __strex(value, ptr)
Michael J. Spencer 2:1df0b61d3b5a 335
Michael J. Spencer 2:1df0b61d3b5a 336
Michael J. Spencer 2:1df0b61d3b5a 337 /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
Michael J. Spencer 2:1df0b61d3b5a 338 /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
Michael J. Spencer 2:1df0b61d3b5a 339 /* intrinsic void __enable_irq(); */
Michael J. Spencer 2:1df0b61d3b5a 340 /* intrinsic void __disable_irq(); */
Michael J. Spencer 2:1df0b61d3b5a 341
Michael J. Spencer 2:1df0b61d3b5a 342
Michael J. Spencer 2:1df0b61d3b5a 343 #if (__ARMCC_VERSION < 400000)
Michael J. Spencer 2:1df0b61d3b5a 344
Michael J. Spencer 2:1df0b61d3b5a 345 #else /* (__ARMCC_VERSION >= 400000) */
Michael J. Spencer 2:1df0b61d3b5a 346
Michael J. Spencer 2:1df0b61d3b5a 347
Michael J. Spencer 2:1df0b61d3b5a 348 /**
Michael J. Spencer 2:1df0b61d3b5a 349 * @brief Remove the exclusive lock created by ldrex
Michael J. Spencer 2:1df0b61d3b5a 350 *
Michael J. Spencer 2:1df0b61d3b5a 351 * @param none
Michael J. Spencer 2:1df0b61d3b5a 352 * @return none
Michael J. Spencer 2:1df0b61d3b5a 353 *
Michael J. Spencer 2:1df0b61d3b5a 354 * Removes the exclusive lock which is created by ldrex.
Michael J. Spencer 2:1df0b61d3b5a 355 */
Michael J. Spencer 2:1df0b61d3b5a 356 #define __CLREX __clrex
Michael J. Spencer 2:1df0b61d3b5a 357
Michael J. Spencer 2:1df0b61d3b5a 358 /**
Michael J. Spencer 2:1df0b61d3b5a 359 * @brief Return the Base Priority value
Michael J. Spencer 2:1df0b61d3b5a 360 *
Michael J. Spencer 2:1df0b61d3b5a 361 * @param none
Michael J. Spencer 2:1df0b61d3b5a 362 * @return uint32_t BasePriority
Michael J. Spencer 2:1df0b61d3b5a 363 *
Michael J. Spencer 2:1df0b61d3b5a 364 * Return the content of the base priority register
Michael J. Spencer 2:1df0b61d3b5a 365 */
Michael J. Spencer 2:1df0b61d3b5a 366 static __INLINE uint32_t __get_BASEPRI(void)
Michael J. Spencer 2:1df0b61d3b5a 367 {
Michael J. Spencer 2:1df0b61d3b5a 368 register uint32_t __regBasePri __ASM("basepri");
Michael J. Spencer 2:1df0b61d3b5a 369 return(__regBasePri);
Michael J. Spencer 2:1df0b61d3b5a 370 }
Michael J. Spencer 2:1df0b61d3b5a 371
Michael J. Spencer 2:1df0b61d3b5a 372 /**
Michael J. Spencer 2:1df0b61d3b5a 373 * @brief Set the Base Priority value
Michael J. Spencer 2:1df0b61d3b5a 374 *
Michael J. Spencer 2:1df0b61d3b5a 375 * @param uint32_t BasePriority
Michael J. Spencer 2:1df0b61d3b5a 376 * @return none
Michael J. Spencer 2:1df0b61d3b5a 377 *
Michael J. Spencer 2:1df0b61d3b5a 378 * Set the base priority register
Michael J. Spencer 2:1df0b61d3b5a 379 */
Michael J. Spencer 2:1df0b61d3b5a 380 static __INLINE void __set_BASEPRI(uint32_t basePri)
Michael J. Spencer 2:1df0b61d3b5a 381 {
Michael J. Spencer 2:1df0b61d3b5a 382 register uint32_t __regBasePri __ASM("basepri");
Michael J. Spencer 2:1df0b61d3b5a 383 __regBasePri = (basePri & 0xff);
Michael J. Spencer 2:1df0b61d3b5a 384 }
Michael J. Spencer 2:1df0b61d3b5a 385
Michael J. Spencer 2:1df0b61d3b5a 386 /**
Michael J. Spencer 2:1df0b61d3b5a 387 * @brief Return the Priority Mask value
Michael J. Spencer 2:1df0b61d3b5a 388 *
Michael J. Spencer 2:1df0b61d3b5a 389 * @param none
Michael J. Spencer 2:1df0b61d3b5a 390 * @return uint32_t PriMask
Michael J. Spencer 2:1df0b61d3b5a 391 *
Michael J. Spencer 2:1df0b61d3b5a 392 * Return the state of the priority mask bit from the priority mask
Michael J. Spencer 2:1df0b61d3b5a 393 * register
Michael J. Spencer 2:1df0b61d3b5a 394 */
Michael J. Spencer 2:1df0b61d3b5a 395 static __INLINE uint32_t __get_PRIMASK(void)
Michael J. Spencer 2:1df0b61d3b5a 396 {
Michael J. Spencer 2:1df0b61d3b5a 397 register uint32_t __regPriMask __ASM("primask");
Michael J. Spencer 2:1df0b61d3b5a 398 return(__regPriMask);
Michael J. Spencer 2:1df0b61d3b5a 399 }
Michael J. Spencer 2:1df0b61d3b5a 400
Michael J. Spencer 2:1df0b61d3b5a 401 /**
Michael J. Spencer 2:1df0b61d3b5a 402 * @brief Set the Priority Mask value
Michael J. Spencer 2:1df0b61d3b5a 403 *
Michael J. Spencer 2:1df0b61d3b5a 404 * @param uint32_t PriMask
Michael J. Spencer 2:1df0b61d3b5a 405 * @return none
Michael J. Spencer 2:1df0b61d3b5a 406 *
Michael J. Spencer 2:1df0b61d3b5a 407 * Set the priority mask bit in the priority mask register
Michael J. Spencer 2:1df0b61d3b5a 408 */
Michael J. Spencer 2:1df0b61d3b5a 409 static __INLINE void __set_PRIMASK(uint32_t priMask)
Michael J. Spencer 2:1df0b61d3b5a 410 {
Michael J. Spencer 2:1df0b61d3b5a 411 register uint32_t __regPriMask __ASM("primask");
Michael J. Spencer 2:1df0b61d3b5a 412 __regPriMask = (priMask);
Michael J. Spencer 2:1df0b61d3b5a 413 }
Michael J. Spencer 2:1df0b61d3b5a 414
Michael J. Spencer 2:1df0b61d3b5a 415 /**
Michael J. Spencer 2:1df0b61d3b5a 416 * @brief Return the Fault Mask value
Michael J. Spencer 2:1df0b61d3b5a 417 *
Michael J. Spencer 2:1df0b61d3b5a 418 * @param none
Michael J. Spencer 2:1df0b61d3b5a 419 * @return uint32_t FaultMask
Michael J. Spencer 2:1df0b61d3b5a 420 *
Michael J. Spencer 2:1df0b61d3b5a 421 * Return the content of the fault mask register
Michael J. Spencer 2:1df0b61d3b5a 422 */
Michael J. Spencer 2:1df0b61d3b5a 423 static __INLINE uint32_t __get_FAULTMASK(void)
Michael J. Spencer 2:1df0b61d3b5a 424 {
Michael J. Spencer 2:1df0b61d3b5a 425 register uint32_t __regFaultMask __ASM("faultmask");
Michael J. Spencer 2:1df0b61d3b5a 426 return(__regFaultMask);
Michael J. Spencer 2:1df0b61d3b5a 427 }
Michael J. Spencer 2:1df0b61d3b5a 428
Michael J. Spencer 2:1df0b61d3b5a 429 /**
Michael J. Spencer 2:1df0b61d3b5a 430 * @brief Set the Fault Mask value
Michael J. Spencer 2:1df0b61d3b5a 431 *
Michael J. Spencer 2:1df0b61d3b5a 432 * @param uint32_t faultMask value
Michael J. Spencer 2:1df0b61d3b5a 433 * @return none
Michael J. Spencer 2:1df0b61d3b5a 434 *
Michael J. Spencer 2:1df0b61d3b5a 435 * Set the fault mask register
Michael J. Spencer 2:1df0b61d3b5a 436 */
Michael J. Spencer 2:1df0b61d3b5a 437 static __INLINE void __set_FAULTMASK(uint32_t faultMask)
Michael J. Spencer 2:1df0b61d3b5a 438 {
Michael J. Spencer 2:1df0b61d3b5a 439 register uint32_t __regFaultMask __ASM("faultmask");
Michael J. Spencer 2:1df0b61d3b5a 440 __regFaultMask = (faultMask & 1);
Michael J. Spencer 2:1df0b61d3b5a 441 }
Michael J. Spencer 2:1df0b61d3b5a 442
Michael J. Spencer 2:1df0b61d3b5a 443 /**
Michael J. Spencer 2:1df0b61d3b5a 444 * @brief Return the Control Register value
Michael J. Spencer 2:1df0b61d3b5a 445 *
Michael J. Spencer 2:1df0b61d3b5a 446 * @param none
Michael J. Spencer 2:1df0b61d3b5a 447 * @return uint32_t Control value
Michael J. Spencer 2:1df0b61d3b5a 448 *
Michael J. Spencer 2:1df0b61d3b5a 449 * Return the content of the control register
Michael J. Spencer 2:1df0b61d3b5a 450 */
Michael J. Spencer 2:1df0b61d3b5a 451 static __INLINE uint32_t __get_CONTROL(void)
Michael J. Spencer 2:1df0b61d3b5a 452 {
Michael J. Spencer 2:1df0b61d3b5a 453 register uint32_t __regControl __ASM("control");
Michael J. Spencer 2:1df0b61d3b5a 454 return(__regControl);
Michael J. Spencer 2:1df0b61d3b5a 455 }
Michael J. Spencer 2:1df0b61d3b5a 456
Michael J. Spencer 2:1df0b61d3b5a 457 /**
Michael J. Spencer 2:1df0b61d3b5a 458 * @brief Set the Control Register value
Michael J. Spencer 2:1df0b61d3b5a 459 *
Michael J. Spencer 2:1df0b61d3b5a 460 * @param uint32_t Control value
Michael J. Spencer 2:1df0b61d3b5a 461 * @return none
Michael J. Spencer 2:1df0b61d3b5a 462 *
Michael J. Spencer 2:1df0b61d3b5a 463 * Set the control register
Michael J. Spencer 2:1df0b61d3b5a 464 */
Michael J. Spencer 2:1df0b61d3b5a 465 static __INLINE void __set_CONTROL(uint32_t control)
Michael J. Spencer 2:1df0b61d3b5a 466 {
Michael J. Spencer 2:1df0b61d3b5a 467 register uint32_t __regControl __ASM("control");
Michael J. Spencer 2:1df0b61d3b5a 468 __regControl = control;
Michael J. Spencer 2:1df0b61d3b5a 469 }
Michael J. Spencer 2:1df0b61d3b5a 470
Michael J. Spencer 2:1df0b61d3b5a 471 #endif /* __ARMCC_VERSION */
Michael J. Spencer 2:1df0b61d3b5a 472
Michael J. Spencer 2:1df0b61d3b5a 473
Michael J. Spencer 2:1df0b61d3b5a 474
Michael J. Spencer 2:1df0b61d3b5a 475 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
Michael J. Spencer 2:1df0b61d3b5a 476 /* IAR iccarm specific functions */
Michael J. Spencer 2:1df0b61d3b5a 477
Michael J. Spencer 2:1df0b61d3b5a 478 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
Michael J. Spencer 2:1df0b61d3b5a 479 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
Michael J. Spencer 2:1df0b61d3b5a 480
Michael J. Spencer 2:1df0b61d3b5a 481 static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
Michael J. Spencer 2:1df0b61d3b5a 482 static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
Michael J. Spencer 2:1df0b61d3b5a 483
Michael J. Spencer 2:1df0b61d3b5a 484 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
Michael J. Spencer 2:1df0b61d3b5a 485 static __INLINE void __WFI() { __ASM ("wfi"); }
Michael J. Spencer 2:1df0b61d3b5a 486 static __INLINE void __WFE() { __ASM ("wfe"); }
Michael J. Spencer 2:1df0b61d3b5a 487 static __INLINE void __SEV() { __ASM ("sev"); }
Michael J. Spencer 2:1df0b61d3b5a 488 static __INLINE void __CLREX() { __ASM ("clrex"); }
Michael J. Spencer 2:1df0b61d3b5a 489
Michael J. Spencer 2:1df0b61d3b5a 490 /* intrinsic void __ISB(void) */
Michael J. Spencer 2:1df0b61d3b5a 491 /* intrinsic void __DSB(void) */
Michael J. Spencer 2:1df0b61d3b5a 492 /* intrinsic void __DMB(void) */
Michael J. Spencer 2:1df0b61d3b5a 493 /* intrinsic void __set_PRIMASK(); */
Michael J. Spencer 2:1df0b61d3b5a 494 /* intrinsic void __get_PRIMASK(); */
Michael J. Spencer 2:1df0b61d3b5a 495 /* intrinsic void __set_FAULTMASK(); */
Michael J. Spencer 2:1df0b61d3b5a 496 /* intrinsic void __get_FAULTMASK(); */
Michael J. Spencer 2:1df0b61d3b5a 497 /* intrinsic uint32_t __REV(uint32_t value); */
Michael J. Spencer 2:1df0b61d3b5a 498 /* intrinsic uint32_t __REVSH(uint32_t value); */
Michael J. Spencer 2:1df0b61d3b5a 499 /* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
Michael J. Spencer 2:1df0b61d3b5a 500 /* intrinsic unsigned long __LDREX(unsigned long *); */
Michael J. Spencer 2:1df0b61d3b5a 501
Michael J. Spencer 2:1df0b61d3b5a 502
Michael J. Spencer 2:1df0b61d3b5a 503 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
Michael J. Spencer 2:1df0b61d3b5a 504 /* GNU gcc specific functions */
Michael J. Spencer 2:1df0b61d3b5a 505
Michael J. Spencer 2:1df0b61d3b5a 506 static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
Michael J. Spencer 2:1df0b61d3b5a 507 static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
Michael J. Spencer 2:1df0b61d3b5a 508
Michael J. Spencer 2:1df0b61d3b5a 509 static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
Michael J. Spencer 2:1df0b61d3b5a 510 static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
Michael J. Spencer 2:1df0b61d3b5a 511
Michael J. Spencer 2:1df0b61d3b5a 512 static __INLINE void __NOP() { __ASM volatile ("nop"); }
Michael J. Spencer 2:1df0b61d3b5a 513 static __INLINE void __WFI() { __ASM volatile ("wfi"); }
Michael J. Spencer 2:1df0b61d3b5a 514 static __INLINE void __WFE() { __ASM volatile ("wfe"); }
Michael J. Spencer 2:1df0b61d3b5a 515 static __INLINE void __SEV() { __ASM volatile ("sev"); }
Michael J. Spencer 2:1df0b61d3b5a 516 static __INLINE void __ISB() { __ASM volatile ("isb"); }
Michael J. Spencer 2:1df0b61d3b5a 517 static __INLINE void __DSB() { __ASM volatile ("dsb"); }
Michael J. Spencer 2:1df0b61d3b5a 518 static __INLINE void __DMB() { __ASM volatile ("dmb"); }
Michael J. Spencer 2:1df0b61d3b5a 519 static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
Michael J. Spencer 2:1df0b61d3b5a 520
Michael J. Spencer 2:1df0b61d3b5a 521
Michael J. Spencer 2:1df0b61d3b5a 522 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
Michael J. Spencer 2:1df0b61d3b5a 523 /* TASKING carm specific functions */
Michael J. Spencer 2:1df0b61d3b5a 524
Michael J. Spencer 2:1df0b61d3b5a 525 /*
Michael J. Spencer 2:1df0b61d3b5a 526 * The CMSIS functions have been implemented as intrinsics in the compiler.
Michael J. Spencer 2:1df0b61d3b5a 527 * Please use "carm -?i" to get an up to date list of all instrinsics,
Michael J. Spencer 2:1df0b61d3b5a 528 * Including the CMSIS ones.
Michael J. Spencer 2:1df0b61d3b5a 529 */
Michael J. Spencer 2:1df0b61d3b5a 530
Michael J. Spencer 2:1df0b61d3b5a 531 #endif
Michael J. Spencer 2:1df0b61d3b5a 532
Michael J. Spencer 2:1df0b61d3b5a 533
Michael J. Spencer 2:1df0b61d3b5a 534
Michael J. Spencer 2:1df0b61d3b5a 535 /* ########################## NVIC functions #################################### */
Michael J. Spencer 2:1df0b61d3b5a 536
Michael J. Spencer 2:1df0b61d3b5a 537
Michael J. Spencer 2:1df0b61d3b5a 538 /**
Michael J. Spencer 2:1df0b61d3b5a 539 * @brief Set the Priority Grouping in NVIC Interrupt Controller
Michael J. Spencer 2:1df0b61d3b5a 540 *
Michael J. Spencer 2:1df0b61d3b5a 541 * @param uint32_t priority_grouping is priority grouping field
Michael J. Spencer 2:1df0b61d3b5a 542 * @return none
Michael J. Spencer 2:1df0b61d3b5a 543 *
Michael J. Spencer 2:1df0b61d3b5a 544 * Set the priority grouping field using the required unlock sequence.
Michael J. Spencer 2:1df0b61d3b5a 545 * The parameter priority_grouping is assigned to the field
Michael J. Spencer 2:1df0b61d3b5a 546 * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
Michael J. Spencer 2:1df0b61d3b5a 547 * In case of a conflict between priority grouping and available
Michael J. Spencer 2:1df0b61d3b5a 548 * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
Michael J. Spencer 2:1df0b61d3b5a 549 */
Michael J. Spencer 2:1df0b61d3b5a 550 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Michael J. Spencer 2:1df0b61d3b5a 551 {
Michael J. Spencer 2:1df0b61d3b5a 552 uint32_t reg_value;
Michael J. Spencer 2:1df0b61d3b5a 553 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Michael J. Spencer 2:1df0b61d3b5a 554
Michael J. Spencer 2:1df0b61d3b5a 555 reg_value = SCB->AIRCR; /* read old register configuration */
Michael J. Spencer 2:1df0b61d3b5a 556 reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
Michael J. Spencer 2:1df0b61d3b5a 557 reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (PriorityGroupTmp << 8))); /* Insert write key and priorty group */
Michael J. Spencer 2:1df0b61d3b5a 558 SCB->AIRCR = reg_value;
Michael J. Spencer 2:1df0b61d3b5a 559 }
Michael J. Spencer 2:1df0b61d3b5a 560
Michael J. Spencer 2:1df0b61d3b5a 561 /**
Michael J. Spencer 2:1df0b61d3b5a 562 * @brief Get the Priority Grouping from NVIC Interrupt Controller
Michael J. Spencer 2:1df0b61d3b5a 563 *
Michael J. Spencer 2:1df0b61d3b5a 564 * @param none
Michael J. Spencer 2:1df0b61d3b5a 565 * @return uint32_t priority grouping field
Michael J. Spencer 2:1df0b61d3b5a 566 *
Michael J. Spencer 2:1df0b61d3b5a 567 * Get the priority grouping from NVIC Interrupt Controller.
Michael J. Spencer 2:1df0b61d3b5a 568 * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
Michael J. Spencer 2:1df0b61d3b5a 569 */
Michael J. Spencer 2:1df0b61d3b5a 570 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
Michael J. Spencer 2:1df0b61d3b5a 571 {
Michael J. Spencer 2:1df0b61d3b5a 572 return ((SCB->AIRCR >> 8) & 0x07); /* read priority grouping field */
Michael J. Spencer 2:1df0b61d3b5a 573 }
Michael J. Spencer 2:1df0b61d3b5a 574
Michael J. Spencer 2:1df0b61d3b5a 575 /**
Michael J. Spencer 2:1df0b61d3b5a 576 * @brief Enable Interrupt in NVIC Interrupt Controller
Michael J. Spencer 2:1df0b61d3b5a 577 *
Michael J. Spencer 2:1df0b61d3b5a 578 * @param IRQn_Type IRQn specifies the interrupt number
Michael J. Spencer 2:1df0b61d3b5a 579 * @return none
Michael J. Spencer 2:1df0b61d3b5a 580 *
Michael J. Spencer 2:1df0b61d3b5a 581 * Enable a device specific interupt in the NVIC interrupt controller.
Michael J. Spencer 2:1df0b61d3b5a 582 * The interrupt number cannot be a negative value.
Michael J. Spencer 2:1df0b61d3b5a 583 */
Michael J. Spencer 2:1df0b61d3b5a 584 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 585 {
Michael J. Spencer 2:1df0b61d3b5a 586 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Michael J. Spencer 2:1df0b61d3b5a 587 }
Michael J. Spencer 2:1df0b61d3b5a 588
Michael J. Spencer 2:1df0b61d3b5a 589 /**
Michael J. Spencer 2:1df0b61d3b5a 590 * @brief Disable the interrupt line for external interrupt specified
Michael J. Spencer 2:1df0b61d3b5a 591 *
Michael J. Spencer 2:1df0b61d3b5a 592 * @param IRQn_Type IRQn is the positive number of the external interrupt
Michael J. Spencer 2:1df0b61d3b5a 593 * @return none
Michael J. Spencer 2:1df0b61d3b5a 594 *
Michael J. Spencer 2:1df0b61d3b5a 595 * Disable a device specific interupt in the NVIC interrupt controller.
Michael J. Spencer 2:1df0b61d3b5a 596 * The interrupt number cannot be a negative value.
Michael J. Spencer 2:1df0b61d3b5a 597 */
Michael J. Spencer 2:1df0b61d3b5a 598 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 599 {
Michael J. Spencer 2:1df0b61d3b5a 600 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Michael J. Spencer 2:1df0b61d3b5a 601 }
Michael J. Spencer 2:1df0b61d3b5a 602
Michael J. Spencer 2:1df0b61d3b5a 603 /**
Michael J. Spencer 2:1df0b61d3b5a 604 * @brief Read the interrupt pending bit for a device specific interrupt source
Michael J. Spencer 2:1df0b61d3b5a 605 *
Michael J. Spencer 2:1df0b61d3b5a 606 * @param IRQn_Type IRQn is the number of the device specifc interrupt
Michael J. Spencer 2:1df0b61d3b5a 607 * @return uint32_t 1 if pending interrupt else 0
Michael J. Spencer 2:1df0b61d3b5a 608 *
Michael J. Spencer 2:1df0b61d3b5a 609 * Read the pending register in NVIC and return 1 if its status is pending,
Michael J. Spencer 2:1df0b61d3b5a 610 * otherwise it returns 0
Michael J. Spencer 2:1df0b61d3b5a 611 */
Michael J. Spencer 2:1df0b61d3b5a 612 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 613 {
Michael J. Spencer 2:1df0b61d3b5a 614 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Michael J. Spencer 2:1df0b61d3b5a 615 }
Michael J. Spencer 2:1df0b61d3b5a 616
Michael J. Spencer 2:1df0b61d3b5a 617 /**
Michael J. Spencer 2:1df0b61d3b5a 618 * @brief Set the pending bit for an external interrupt
Michael J. Spencer 2:1df0b61d3b5a 619 *
Michael J. Spencer 2:1df0b61d3b5a 620 * @param IRQn_Type IRQn is the Number of the interrupt
Michael J. Spencer 2:1df0b61d3b5a 621 * @return none
Michael J. Spencer 2:1df0b61d3b5a 622 *
Michael J. Spencer 2:1df0b61d3b5a 623 * Set the pending bit for the specified interrupt.
Michael J. Spencer 2:1df0b61d3b5a 624 * The interrupt number cannot be a negative value.
Michael J. Spencer 2:1df0b61d3b5a 625 */
Michael J. Spencer 2:1df0b61d3b5a 626 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 627 {
Michael J. Spencer 2:1df0b61d3b5a 628 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Michael J. Spencer 2:1df0b61d3b5a 629 }
Michael J. Spencer 2:1df0b61d3b5a 630
Michael J. Spencer 2:1df0b61d3b5a 631 /**
Michael J. Spencer 2:1df0b61d3b5a 632 * @brief Clear the pending bit for an external interrupt
Michael J. Spencer 2:1df0b61d3b5a 633 *
Michael J. Spencer 2:1df0b61d3b5a 634 * @param IRQn_Type IRQn is the Number of the interrupt
Michael J. Spencer 2:1df0b61d3b5a 635 * @return none
Michael J. Spencer 2:1df0b61d3b5a 636 *
Michael J. Spencer 2:1df0b61d3b5a 637 * Clear the pending bit for the specified interrupt.
Michael J. Spencer 2:1df0b61d3b5a 638 * The interrupt number cannot be a negative value.
Michael J. Spencer 2:1df0b61d3b5a 639 */
Michael J. Spencer 2:1df0b61d3b5a 640 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 641 {
Michael J. Spencer 2:1df0b61d3b5a 642 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Michael J. Spencer 2:1df0b61d3b5a 643 }
Michael J. Spencer 2:1df0b61d3b5a 644
Michael J. Spencer 2:1df0b61d3b5a 645 /**
Michael J. Spencer 2:1df0b61d3b5a 646 * @brief Read the active bit for an external interrupt
Michael J. Spencer 2:1df0b61d3b5a 647 *
Michael J. Spencer 2:1df0b61d3b5a 648 * @param IRQn_Type IRQn is the Number of the interrupt
Michael J. Spencer 2:1df0b61d3b5a 649 * @return uint32_t 1 if active else 0
Michael J. Spencer 2:1df0b61d3b5a 650 *
Michael J. Spencer 2:1df0b61d3b5a 651 * Read the active register in NVIC and returns 1 if its status is active,
Michael J. Spencer 2:1df0b61d3b5a 652 * otherwise it returns 0.
Michael J. Spencer 2:1df0b61d3b5a 653 */
Michael J. Spencer 2:1df0b61d3b5a 654 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 655 {
Michael J. Spencer 2:1df0b61d3b5a 656 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Michael J. Spencer 2:1df0b61d3b5a 657 }
Michael J. Spencer 2:1df0b61d3b5a 658
Michael J. Spencer 2:1df0b61d3b5a 659 /**
Michael J. Spencer 2:1df0b61d3b5a 660 * @brief Set the priority for an interrupt
Michael J. Spencer 2:1df0b61d3b5a 661 *
Michael J. Spencer 2:1df0b61d3b5a 662 * @param IRQn_Type IRQn is the Number of the interrupt
Michael J. Spencer 2:1df0b61d3b5a 663 * @param priority is the priority for the interrupt
Michael J. Spencer 2:1df0b61d3b5a 664 * @return none
Michael J. Spencer 2:1df0b61d3b5a 665 *
Michael J. Spencer 2:1df0b61d3b5a 666 * Set the priority for the specified interrupt. The interrupt
Michael J. Spencer 2:1df0b61d3b5a 667 * number can be positive to specify an external (device specific)
Michael J. Spencer 2:1df0b61d3b5a 668 * interrupt, or negative to specify an internal (core) interrupt. \n
Michael J. Spencer 2:1df0b61d3b5a 669 *
Michael J. Spencer 2:1df0b61d3b5a 670 * Note: The priority cannot be set for every core interrupt.
Michael J. Spencer 2:1df0b61d3b5a 671 */
Michael J. Spencer 2:1df0b61d3b5a 672 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Michael J. Spencer 2:1df0b61d3b5a 673 {
Michael J. Spencer 2:1df0b61d3b5a 674 if(IRQn < 0) {
Michael J. Spencer 2:1df0b61d3b5a 675 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
Michael J. Spencer 2:1df0b61d3b5a 676 else {
Michael J. Spencer 2:1df0b61d3b5a 677 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Michael J. Spencer 2:1df0b61d3b5a 678 }
Michael J. Spencer 2:1df0b61d3b5a 679
Michael J. Spencer 2:1df0b61d3b5a 680 /**
Michael J. Spencer 2:1df0b61d3b5a 681 * @brief Read the priority for an interrupt
Michael J. Spencer 2:1df0b61d3b5a 682 *
Michael J. Spencer 2:1df0b61d3b5a 683 * @param IRQn_Type IRQn is the Number of the interrupt
Michael J. Spencer 2:1df0b61d3b5a 684 * @return uint32_t priority is the priority for the interrupt
Michael J. Spencer 2:1df0b61d3b5a 685 *
Michael J. Spencer 2:1df0b61d3b5a 686 * Read the priority for the specified interrupt. The interrupt
Michael J. Spencer 2:1df0b61d3b5a 687 * number can be positive to specify an external (device specific)
Michael J. Spencer 2:1df0b61d3b5a 688 * interrupt, or negative to specify an internal (core) interrupt.
Michael J. Spencer 2:1df0b61d3b5a 689 *
Michael J. Spencer 2:1df0b61d3b5a 690 * The returned priority value is automatically aligned to the implemented
Michael J. Spencer 2:1df0b61d3b5a 691 * priority bits of the microcontroller.
Michael J. Spencer 2:1df0b61d3b5a 692 *
Michael J. Spencer 2:1df0b61d3b5a 693 * Note: The priority cannot be set for every core interrupt.
Michael J. Spencer 2:1df0b61d3b5a 694 */
Michael J. Spencer 2:1df0b61d3b5a 695 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Michael J. Spencer 2:1df0b61d3b5a 696 {
Michael J. Spencer 2:1df0b61d3b5a 697
Michael J. Spencer 2:1df0b61d3b5a 698 if(IRQn < 0) {
Michael J. Spencer 2:1df0b61d3b5a 699 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
Michael J. Spencer 2:1df0b61d3b5a 700 else {
Michael J. Spencer 2:1df0b61d3b5a 701 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Michael J. Spencer 2:1df0b61d3b5a 702 }
Michael J. Spencer 2:1df0b61d3b5a 703
Michael J. Spencer 2:1df0b61d3b5a 704
Michael J. Spencer 2:1df0b61d3b5a 705 /**
Michael J. Spencer 2:1df0b61d3b5a 706 * @brief Encode the priority for an interrupt
Michael J. Spencer 2:1df0b61d3b5a 707 *
Michael J. Spencer 2:1df0b61d3b5a 708 * @param uint32_t PriorityGroup is the used priority group
Michael J. Spencer 2:1df0b61d3b5a 709 * @param uint32_t PreemptPriority is the preemptive priority value (starting from 0)
Michael J. Spencer 2:1df0b61d3b5a 710 * @param uint32_t SubPriority is the sub priority value (starting from 0)
Michael J. Spencer 2:1df0b61d3b5a 711 * @return uint32_t the priority for the interrupt
Michael J. Spencer 2:1df0b61d3b5a 712 *
Michael J. Spencer 2:1df0b61d3b5a 713 * Encode the priority for an interrupt with the given priority group,
Michael J. Spencer 2:1df0b61d3b5a 714 * preemptive priority value and sub priority value.
Michael J. Spencer 2:1df0b61d3b5a 715 * In case of a conflict between priority grouping and available
Michael J. Spencer 2:1df0b61d3b5a 716 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Michael J. Spencer 2:1df0b61d3b5a 717 *
Michael J. Spencer 2:1df0b61d3b5a 718 * The returned priority value can be used for NVIC_SetPriority(...) function
Michael J. Spencer 2:1df0b61d3b5a 719 */
Michael J. Spencer 2:1df0b61d3b5a 720 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Michael J. Spencer 2:1df0b61d3b5a 721 {
Michael J. Spencer 2:1df0b61d3b5a 722 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Michael J. Spencer 2:1df0b61d3b5a 723 uint32_t PreemptPriorityBits;
Michael J. Spencer 2:1df0b61d3b5a 724 uint32_t SubPriorityBits;
Michael J. Spencer 2:1df0b61d3b5a 725
Michael J. Spencer 2:1df0b61d3b5a 726 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Michael J. Spencer 2:1df0b61d3b5a 727 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Michael J. Spencer 2:1df0b61d3b5a 728
Michael J. Spencer 2:1df0b61d3b5a 729 return (
Michael J. Spencer 2:1df0b61d3b5a 730 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
Michael J. Spencer 2:1df0b61d3b5a 731 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Michael J. Spencer 2:1df0b61d3b5a 732 );
Michael J. Spencer 2:1df0b61d3b5a 733 }
Michael J. Spencer 2:1df0b61d3b5a 734
Michael J. Spencer 2:1df0b61d3b5a 735
Michael J. Spencer 2:1df0b61d3b5a 736 /**
Michael J. Spencer 2:1df0b61d3b5a 737 * @brief Decode the priority of an interrupt
Michael J. Spencer 2:1df0b61d3b5a 738 *
Michael J. Spencer 2:1df0b61d3b5a 739 * @param uint32_t Priority the priority for the interrupt
Michael J. Spencer 2:1df0b61d3b5a 740 * @param uint32_t PrioGroup is the used priority group
Michael J. Spencer 2:1df0b61d3b5a 741 * @param uint32_t* pPreemptPrio is the preemptive priority value (starting from 0)
Michael J. Spencer 2:1df0b61d3b5a 742 * @param uint32_t* pSubPrio is the sub priority value (starting from 0)
Michael J. Spencer 2:1df0b61d3b5a 743 * @return none
Michael J. Spencer 2:1df0b61d3b5a 744 *
Michael J. Spencer 2:1df0b61d3b5a 745 * Decode an interrupt priority value with the given priority group to
Michael J. Spencer 2:1df0b61d3b5a 746 * preemptive priority value and sub priority value.
Michael J. Spencer 2:1df0b61d3b5a 747 * In case of a conflict between priority grouping and available
Michael J. Spencer 2:1df0b61d3b5a 748 * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Michael J. Spencer 2:1df0b61d3b5a 749 *
Michael J. Spencer 2:1df0b61d3b5a 750 * The priority value can be retrieved with NVIC_GetPriority(...) function
Michael J. Spencer 2:1df0b61d3b5a 751 */
Michael J. Spencer 2:1df0b61d3b5a 752 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Michael J. Spencer 2:1df0b61d3b5a 753 {
Michael J. Spencer 2:1df0b61d3b5a 754 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Michael J. Spencer 2:1df0b61d3b5a 755 uint32_t PreemptPriorityBits;
Michael J. Spencer 2:1df0b61d3b5a 756 uint32_t SubPriorityBits;
Michael J. Spencer 2:1df0b61d3b5a 757
Michael J. Spencer 2:1df0b61d3b5a 758 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Michael J. Spencer 2:1df0b61d3b5a 759 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Michael J. Spencer 2:1df0b61d3b5a 760
Michael J. Spencer 2:1df0b61d3b5a 761 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Michael J. Spencer 2:1df0b61d3b5a 762 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Michael J. Spencer 2:1df0b61d3b5a 763 }
Michael J. Spencer 2:1df0b61d3b5a 764
Michael J. Spencer 2:1df0b61d3b5a 765
Michael J. Spencer 2:1df0b61d3b5a 766
Michael J. Spencer 2:1df0b61d3b5a 767 /* ################################## SysTick function ############################################ */
Michael J. Spencer 2:1df0b61d3b5a 768
Michael J. Spencer 2:1df0b61d3b5a 769 #if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
Michael J. Spencer 2:1df0b61d3b5a 770
Michael J. Spencer 2:1df0b61d3b5a 771 /* SysTick constants */
Michael J. Spencer 2:1df0b61d3b5a 772 #define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
Michael J. Spencer 2:1df0b61d3b5a 773 #define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
Michael J. Spencer 2:1df0b61d3b5a 774 #define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
Michael J. Spencer 2:1df0b61d3b5a 775 #define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
Michael J. Spencer 2:1df0b61d3b5a 776
Michael J. Spencer 2:1df0b61d3b5a 777 /**
Michael J. Spencer 2:1df0b61d3b5a 778 * @brief Initialize and start the SysTick counter and its interrupt.
Michael J. Spencer 2:1df0b61d3b5a 779 *
Michael J. Spencer 2:1df0b61d3b5a 780 * @param uint32_t ticks is the number of ticks between two interrupts
Michael J. Spencer 2:1df0b61d3b5a 781 * @return none
Michael J. Spencer 2:1df0b61d3b5a 782 *
Michael J. Spencer 2:1df0b61d3b5a 783 * Initialise the system tick timer and its interrupt and start the
Michael J. Spencer 2:1df0b61d3b5a 784 * system tick timer / counter in free running mode to generate
Michael J. Spencer 2:1df0b61d3b5a 785 * periodical interrupts.
Michael J. Spencer 2:1df0b61d3b5a 786 */
Michael J. Spencer 2:1df0b61d3b5a 787 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
Michael J. Spencer 2:1df0b61d3b5a 788 {
Michael J. Spencer 2:1df0b61d3b5a 789 if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
Michael J. Spencer 2:1df0b61d3b5a 790
Michael J. Spencer 2:1df0b61d3b5a 791 SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
Michael J. Spencer 2:1df0b61d3b5a 792 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
Michael J. Spencer 2:1df0b61d3b5a 793 SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
Michael J. Spencer 2:1df0b61d3b5a 794 SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
Michael J. Spencer 2:1df0b61d3b5a 795 return (0); /* Function successful */
Michael J. Spencer 2:1df0b61d3b5a 796 }
Michael J. Spencer 2:1df0b61d3b5a 797
Michael J. Spencer 2:1df0b61d3b5a 798 #endif
Michael J. Spencer 2:1df0b61d3b5a 799
Michael J. Spencer 2:1df0b61d3b5a 800
Michael J. Spencer 2:1df0b61d3b5a 801
Michael J. Spencer 2:1df0b61d3b5a 802
Michael J. Spencer 2:1df0b61d3b5a 803
Michael J. Spencer 2:1df0b61d3b5a 804 /* ################################## Reset function ############################################ */
Michael J. Spencer 2:1df0b61d3b5a 805
Michael J. Spencer 2:1df0b61d3b5a 806 /**
Michael J. Spencer 2:1df0b61d3b5a 807 * @brief Initiate a system reset request.
Michael J. Spencer 2:1df0b61d3b5a 808 *
Michael J. Spencer 2:1df0b61d3b5a 809 * @param none
Michael J. Spencer 2:1df0b61d3b5a 810 * @return none
Michael J. Spencer 2:1df0b61d3b5a 811 *
Michael J. Spencer 2:1df0b61d3b5a 812 * Initialize a system reset request to reset the MCU
Michael J. Spencer 2:1df0b61d3b5a 813 */
Michael J. Spencer 2:1df0b61d3b5a 814 static __INLINE void NVIC_SystemReset(void)
Michael J. Spencer 2:1df0b61d3b5a 815 {
Michael J. Spencer 2:1df0b61d3b5a 816 SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
Michael J. Spencer 2:1df0b61d3b5a 817 __DSB(); /* Ensure completion of memory access */
Michael J. Spencer 2:1df0b61d3b5a 818 while(1); /* wait until reset */
Michael J. Spencer 2:1df0b61d3b5a 819 }
Michael J. Spencer 2:1df0b61d3b5a 820
Michael J. Spencer 2:1df0b61d3b5a 821
Michael J. Spencer 2:1df0b61d3b5a 822 /* ##################################### Debug In/Output function ########################################### */
Michael J. Spencer 2:1df0b61d3b5a 823
Michael J. Spencer 2:1df0b61d3b5a 824 extern volatile int ITM_RxBuffer; /* variable to receive characters */
Michael J. Spencer 2:1df0b61d3b5a 825 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
Michael J. Spencer 2:1df0b61d3b5a 826
Michael J. Spencer 2:1df0b61d3b5a 827
Michael J. Spencer 2:1df0b61d3b5a 828 /**
Michael J. Spencer 2:1df0b61d3b5a 829 * @brief Outputs a character via the ITM channel 0
Michael J. Spencer 2:1df0b61d3b5a 830 *
Michael J. Spencer 2:1df0b61d3b5a 831 * @param uint32_t character to output
Michael J. Spencer 2:1df0b61d3b5a 832 * @return uint32_t input character
Michael J. Spencer 2:1df0b61d3b5a 833 *
Michael J. Spencer 2:1df0b61d3b5a 834 * The function outputs a character via the ITM channel 0.
Michael J. Spencer 2:1df0b61d3b5a 835 * The function returns when no debugger is connected that has booked the output.
Michael J. Spencer 2:1df0b61d3b5a 836 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
Michael J. Spencer 2:1df0b61d3b5a 837 */
Michael J. Spencer 2:1df0b61d3b5a 838 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
Michael J. Spencer 2:1df0b61d3b5a 839 {
Michael J. Spencer 2:1df0b61d3b5a 840 if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
Michael J. Spencer 2:1df0b61d3b5a 841 (ITM->TCR & ITM_TCR_ITMENA) &&
Michael J. Spencer 2:1df0b61d3b5a 842 (ITM->TER & (1UL << 0)) )
Michael J. Spencer 2:1df0b61d3b5a 843 {
Michael J. Spencer 2:1df0b61d3b5a 844 while (ITM->PORT[0].u32 == 0);
Michael J. Spencer 2:1df0b61d3b5a 845 ITM->PORT[0].u8 = (uint8_t) ch;
Michael J. Spencer 2:1df0b61d3b5a 846 }
Michael J. Spencer 2:1df0b61d3b5a 847 return (ch);
Michael J. Spencer 2:1df0b61d3b5a 848 }
Michael J. Spencer 2:1df0b61d3b5a 849
Michael J. Spencer 2:1df0b61d3b5a 850
Michael J. Spencer 2:1df0b61d3b5a 851 /**
Michael J. Spencer 2:1df0b61d3b5a 852 * @brief Inputs a character via variable ITM_RxBuffer
Michael J. Spencer 2:1df0b61d3b5a 853 *
Michael J. Spencer 2:1df0b61d3b5a 854 * @param none
Michael J. Spencer 2:1df0b61d3b5a 855 * @return uint32_t input character
Michael J. Spencer 2:1df0b61d3b5a 856 *
Michael J. Spencer 2:1df0b61d3b5a 857 * The function inputs a character via variable ITM_RxBuffer.
Michael J. Spencer 2:1df0b61d3b5a 858 * The function returns when no debugger is connected that has booked the output.
Michael J. Spencer 2:1df0b61d3b5a 859 * It is blocking when a debugger is connected, but the previous character send is not transmitted.
Michael J. Spencer 2:1df0b61d3b5a 860 */
Michael J. Spencer 2:1df0b61d3b5a 861 static __INLINE int ITM_ReceiveChar (void) {
Michael J. Spencer 2:1df0b61d3b5a 862 int ch = -1; /* no character available */
Michael J. Spencer 2:1df0b61d3b5a 863
Michael J. Spencer 2:1df0b61d3b5a 864 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Michael J. Spencer 2:1df0b61d3b5a 865 ch = ITM_RxBuffer;
Michael J. Spencer 2:1df0b61d3b5a 866 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Michael J. Spencer 2:1df0b61d3b5a 867 }
Michael J. Spencer 2:1df0b61d3b5a 868
Michael J. Spencer 2:1df0b61d3b5a 869 return (ch);
Michael J. Spencer 2:1df0b61d3b5a 870 }
Michael J. Spencer 2:1df0b61d3b5a 871
Michael J. Spencer 2:1df0b61d3b5a 872
Michael J. Spencer 2:1df0b61d3b5a 873 /**
Michael J. Spencer 2:1df0b61d3b5a 874 * @brief Check if a character via variable ITM_RxBuffer is available
Michael J. Spencer 2:1df0b61d3b5a 875 *
Michael J. Spencer 2:1df0b61d3b5a 876 * @param none
Michael J. Spencer 2:1df0b61d3b5a 877 * @return int 1 = character available, 0 = no character available
Michael J. Spencer 2:1df0b61d3b5a 878 *
Michael J. Spencer 2:1df0b61d3b5a 879 * The function checks variable ITM_RxBuffer whether a character is available or not.
Michael J. Spencer 2:1df0b61d3b5a 880 * The function returns '1' if a character is available and '0' if no character is available.
Michael J. Spencer 2:1df0b61d3b5a 881 */
Michael J. Spencer 2:1df0b61d3b5a 882 static __INLINE int ITM_CheckChar (void) {
Michael J. Spencer 2:1df0b61d3b5a 883
Michael J. Spencer 2:1df0b61d3b5a 884 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Michael J. Spencer 2:1df0b61d3b5a 885 return (0); /* no character available */
Michael J. Spencer 2:1df0b61d3b5a 886 } else {
Michael J. Spencer 2:1df0b61d3b5a 887 return (1); /* character available */
Michael J. Spencer 2:1df0b61d3b5a 888 }
Michael J. Spencer 2:1df0b61d3b5a 889 }
Michael J. Spencer 2:1df0b61d3b5a 890
Michael J. Spencer 2:1df0b61d3b5a 891
Michael J. Spencer 2:1df0b61d3b5a 892
Michael J. Spencer 2:1df0b61d3b5a 893 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 894 }
Michael J. Spencer 2:1df0b61d3b5a 895 #endif
Michael J. Spencer 2:1df0b61d3b5a 896
Michael J. Spencer 2:1df0b61d3b5a 897 #endif /* __CM3_CORE_H__ */
Michael J. Spencer 2:1df0b61d3b5a 898
Michael J. Spencer 2:1df0b61d3b5a 899 /*lint -restore */