Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/sLPC17xx.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /****************************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * @file: LPC17xx.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File for |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * NXP LPC17xx Device Series |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @version: V1.04 |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * @date: 2. July 2009 |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | *---------------------------------------------------------------------------- |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * Copyright (C) 2008 ARM Limited. All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * processor based microcontrollers. This file can be freely distributed |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * within development tools that are supporting such ARM based processors. |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | ******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | #ifndef __LPC17xx_H__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | #define __LPC17xx_H__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | * ========================================================================== |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * ---------- Interrupt Number Definition ----------------------------------- |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * ========================================================================== |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | typedef enum IRQn |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | /****** LPC17xx Specific Interrupt Numbers *******************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | UART0_IRQn = 5, /*!< UART0 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | UART1_IRQn = 6, /*!< UART1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | UART2_IRQn = 7, /*!< UART2 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | UART3_IRQn = 8, /*!< UART3 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | PWM1_IRQn = 9, /*!< PWM1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | I2C0_IRQn = 10, /*!< I2C0 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | I2C1_IRQn = 11, /*!< I2C1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | I2C2_IRQn = 12, /*!< I2C2 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | SPI_IRQn = 13, /*!< SPI Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | SSP0_IRQn = 14, /*!< SSP0 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | SSP1_IRQn = 15, /*!< SSP1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | ADC_IRQn = 22, /*!< A/D Converter Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | USB_IRQn = 24, /*!< USB Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | CAN_IRQn = 25, /*!< CAN Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | I2S_IRQn = 27, /*!< I2S Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | ENET_IRQn = 28, /*!< Ethernet Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | } IRQn_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | /* |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | * ========================================================================== |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | * ----------- Processor and Core Peripheral Section ------------------------ |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | * ========================================================================== |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | /* Configuration of the Cortex-M3 Processor and Core Peripherals */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | #include "score_cm3.h" /* Cortex-M3 processor and core peripherals */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | //#include "system_LPC17xx.h" /* System Header */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | /* Device Specific Peripheral registers structures */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | #if defined ( __CC_ARM ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | #pragma anon_unions |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | /*------------- System Control (SC) ------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | __IO uint32_t FLASHCFG; /* Flash Accelerator Module */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | uint32_t RESERVED0[31]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | __IO uint32_t PLL0CON; /* Clocking and Power Control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | __IO uint32_t PLL0CFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | __I uint32_t PLL0STAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | __O uint32_t PLL0FEED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | uint32_t RESERVED1[4]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | __IO uint32_t PLL1CON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | __IO uint32_t PLL1CFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | __I uint32_t PLL1STAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | __O uint32_t PLL1FEED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | uint32_t RESERVED2[4]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | __IO uint32_t PCON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | __IO uint32_t PCONP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | uint32_t RESERVED3[15]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | __IO uint32_t CCLKCFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | __IO uint32_t USBCLKCFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | __IO uint32_t CLKSRCSEL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | uint32_t RESERVED4[12]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | __IO uint32_t EXTINT; /* External Interrupts */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | uint32_t RESERVED5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | __IO uint32_t EXTMODE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | __IO uint32_t EXTPOLAR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | uint32_t RESERVED6[12]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | __IO uint32_t RSID; /* Reset */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | uint32_t RESERVED7[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | __IO uint32_t SCS; /* Syscon Miscellaneous Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | __IO uint32_t IRCTRIM; /* Clock Dividers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | __IO uint32_t PCLKSEL0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | __IO uint32_t PCLKSEL1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | uint32_t RESERVED8[4]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | uint32_t RESERVED9; |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | } LPC_SC_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | /*------------- Pin Connect Block (PINCON) -----------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | __IO uint32_t PINSEL0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | __IO uint32_t PINSEL1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | __IO uint32_t PINSEL2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | __IO uint32_t PINSEL3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | __IO uint32_t PINSEL4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | __IO uint32_t PINSEL5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | __IO uint32_t PINSEL6; |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | __IO uint32_t PINSEL7; |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | __IO uint32_t PINSEL8; |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | __IO uint32_t PINSEL9; |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | __IO uint32_t PINSEL10; |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | uint32_t RESERVED0[5]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | __IO uint32_t PINMODE0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | __IO uint32_t PINMODE1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | __IO uint32_t PINMODE2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | __IO uint32_t PINMODE3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | __IO uint32_t PINMODE4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | __IO uint32_t PINMODE5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | __IO uint32_t PINMODE6; |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | __IO uint32_t PINMODE7; |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | __IO uint32_t PINMODE8; |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | __IO uint32_t PINMODE9; |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | __IO uint32_t PINMODE_OD0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | __IO uint32_t PINMODE_OD1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | __IO uint32_t PINMODE_OD2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | __IO uint32_t PINMODE_OD3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | __IO uint32_t PINMODE_OD4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | __IO uint32_t I2CPADCFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | } LPC_PINCON_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | /*------------- General Purpose Input/Output (GPIO) --------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | __IO uint32_t FIODIR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | uint32_t RESERVED0[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | __IO uint32_t FIOMASK; |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | __IO uint32_t FIOPIN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | __IO uint32_t FIOSET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | __O uint32_t FIOCLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | } LPC_GPIO_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | __I uint32_t IntStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | __I uint32_t IO0IntStatR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | __I uint32_t IO0IntStatF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | __O uint32_t IO0IntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | __IO uint32_t IO0IntEnR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | __IO uint32_t IO0IntEnF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | uint32_t RESERVED0[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | __I uint32_t IO2IntStatR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | __I uint32_t IO2IntStatF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | __O uint32_t IO2IntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | __IO uint32_t IO2IntEnR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | __IO uint32_t IO2IntEnF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | } LPC_GPIOINT_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | /*------------- Timer (TIM) --------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | __IO uint32_t IR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | __IO uint32_t TCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | __IO uint32_t TC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | __IO uint32_t PR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | __IO uint32_t PC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | __IO uint32_t MCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | __IO uint32_t MR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | __IO uint32_t MR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | __IO uint32_t MR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | __IO uint32_t MR3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | __IO uint32_t CCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | __I uint32_t CR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | __I uint32_t CR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | uint32_t RESERVED0[2]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | __IO uint32_t EMR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | uint32_t RESERVED1[12]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | __IO uint32_t CTCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | } LPC_TIM_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | __IO uint32_t IR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | __IO uint32_t TCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | __IO uint32_t TC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | __IO uint32_t PR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | __IO uint32_t PC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | __IO uint32_t MCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | __IO uint32_t MR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | __IO uint32_t MR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | __IO uint32_t MR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | __IO uint32_t MR3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | __IO uint32_t CCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | __I uint32_t CR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | __I uint32_t CR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | __I uint32_t CR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | __I uint32_t CR3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | uint32_t RESERVED0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | __IO uint32_t MR4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | __IO uint32_t MR5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | __IO uint32_t MR6; |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | __IO uint32_t PCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | __IO uint32_t LER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | uint32_t RESERVED1[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | __IO uint32_t CTCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | } LPC_PWM_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | __I uint8_t RBR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | __O uint8_t THR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | __IO uint8_t DLL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | uint32_t RESERVED0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | __IO uint8_t DLM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | __IO uint32_t IER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | __I uint32_t IIR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | __O uint8_t FCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | __IO uint8_t LCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | uint8_t RESERVED1[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | __I uint8_t LSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | uint8_t RESERVED2[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | __IO uint8_t SCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | uint8_t RESERVED3[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | __IO uint32_t ACR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | __IO uint8_t ICR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | uint8_t RESERVED4[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | __IO uint8_t FDR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | uint8_t RESERVED5[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | __IO uint8_t TER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | uint8_t RESERVED6[39]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | __I uint8_t FIFOLVL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | } LPC_UART_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | __I uint8_t RBR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | __O uint8_t THR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | __IO uint8_t DLL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | uint32_t RESERVED0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | __IO uint8_t DLM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | __IO uint32_t IER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | __I uint32_t IIR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | __O uint8_t FCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | __IO uint8_t LCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | uint8_t RESERVED1[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | __I uint8_t LSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | uint8_t RESERVED2[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | __IO uint8_t SCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | uint8_t RESERVED3[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | __IO uint32_t ACR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | __IO uint8_t ICR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | uint8_t RESERVED4[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | __IO uint8_t FDR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | uint8_t RESERVED5[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | __IO uint8_t TER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | uint8_t RESERVED6[39]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | __I uint8_t FIFOLVL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | uint8_t RESERVED7[363]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | __IO uint32_t DMAREQSEL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | } LPC_UART0_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | __I uint8_t RBR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | __O uint8_t THR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | __IO uint8_t DLL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | uint32_t RESERVED0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | __IO uint8_t DLM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | __IO uint32_t IER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | __I uint32_t IIR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | __O uint8_t FCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | __IO uint8_t LCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | uint8_t RESERVED1[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | __IO uint8_t MCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | uint8_t RESERVED2[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | __I uint8_t LSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | uint8_t RESERVED3[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | __I uint8_t MSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | uint8_t RESERVED4[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | __IO uint8_t SCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | uint8_t RESERVED5[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | __IO uint32_t ACR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | uint32_t RESERVED6; |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | __IO uint32_t FDR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | uint32_t RESERVED7; |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | __IO uint8_t TER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | uint8_t RESERVED8[27]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | __IO uint8_t RS485CTRL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | uint8_t RESERVED9[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | __IO uint8_t ADRMATCH; |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | uint8_t RESERVED10[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | __IO uint8_t RS485DLY; |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | uint8_t RESERVED11[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | __I uint8_t FIFOLVL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | } LPC_UART1_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | /*------------- Serial Peripheral Interface (SPI) ----------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | __IO uint32_t SPCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | __I uint32_t SPSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | __IO uint32_t SPDR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | __IO uint32_t SPCCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | uint32_t RESERVED0[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | __IO uint32_t SPINT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | } LPC_SPI_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | /*------------- Synchronous Serial Communication (SSP) -----------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | __IO uint32_t CR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | __IO uint32_t CR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | __IO uint32_t DR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | __I uint32_t SR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | __IO uint32_t CPSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | __IO uint32_t IMSC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | __IO uint32_t RIS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | __IO uint32_t MIS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | __IO uint32_t ICR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | __IO uint32_t DMACR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | } LPC_SSP_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | __IO uint32_t I2CONSET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | __I uint32_t I2STAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | __IO uint32_t I2DAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | __IO uint32_t I2ADR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | __IO uint32_t I2SCLH; |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | __IO uint32_t I2SCLL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | __O uint32_t I2CONCLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | __IO uint32_t MMCTRL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | __IO uint32_t I2ADR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 401 | __IO uint32_t I2ADR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 402 | __IO uint32_t I2ADR3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 403 | __I uint32_t I2DATA_BUFFER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 404 | __IO uint32_t I2MASK0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 405 | __IO uint32_t I2MASK1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 406 | __IO uint32_t I2MASK2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 407 | __IO uint32_t I2MASK3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 408 | } LPC_I2C_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 409 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 410 | /*------------- Inter IC Sound (I2S) -----------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 411 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 412 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 413 | __IO uint32_t I2SDAO; |
| Michael J. Spencer |
2:1df0b61d3b5a | 414 | __IO uint32_t I2SDAI; |
| Michael J. Spencer |
2:1df0b61d3b5a | 415 | __O uint32_t I2STXFIFO; |
| Michael J. Spencer |
2:1df0b61d3b5a | 416 | __I uint32_t I2SRXFIFO; |
| Michael J. Spencer |
2:1df0b61d3b5a | 417 | __I uint32_t I2SSTATE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 418 | __IO uint32_t I2SDMA1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 419 | __IO uint32_t I2SDMA2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 420 | __IO uint32_t I2SIRQ; |
| Michael J. Spencer |
2:1df0b61d3b5a | 421 | __IO uint32_t I2STXRATE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 422 | __IO uint32_t I2SRXRATE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 423 | __IO uint32_t I2STXBITRATE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 424 | __IO uint32_t I2SRXBITRATE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 425 | __IO uint32_t I2STXMODE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 426 | __IO uint32_t I2SRXMODE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 427 | } LPC_I2S_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 428 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 429 | /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 430 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 431 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 432 | __IO uint32_t RICOMPVAL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 433 | __IO uint32_t RIMASK; |
| Michael J. Spencer |
2:1df0b61d3b5a | 434 | __IO uint8_t RICTRL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 435 | uint8_t RESERVED0[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 436 | __IO uint32_t RICOUNTER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 437 | } LPC_RIT_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 438 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 439 | /*------------- Real-Time Clock (RTC) ----------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 440 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 441 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 442 | __IO uint8_t ILR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 443 | uint8_t RESERVED0[7]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 444 | __IO uint8_t CCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 445 | uint8_t RESERVED1[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 446 | __IO uint8_t CIIR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 447 | uint8_t RESERVED2[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 448 | __IO uint8_t AMR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 449 | uint8_t RESERVED3[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 450 | __I uint32_t CTIME0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 451 | __I uint32_t CTIME1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 452 | __I uint32_t CTIME2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 453 | __IO uint8_t SEC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 454 | uint8_t RESERVED4[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 455 | __IO uint8_t MIN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 456 | uint8_t RESERVED5[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 457 | __IO uint8_t HOUR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 458 | uint8_t RESERVED6[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 459 | __IO uint8_t DOM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 460 | uint8_t RESERVED7[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 461 | __IO uint8_t DOW; |
| Michael J. Spencer |
2:1df0b61d3b5a | 462 | uint8_t RESERVED8[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 463 | __IO uint16_t DOY; |
| Michael J. Spencer |
2:1df0b61d3b5a | 464 | uint16_t RESERVED9; |
| Michael J. Spencer |
2:1df0b61d3b5a | 465 | __IO uint8_t MONTH; |
| Michael J. Spencer |
2:1df0b61d3b5a | 466 | uint8_t RESERVED10[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 467 | __IO uint16_t YEAR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 468 | uint16_t RESERVED11; |
| Michael J. Spencer |
2:1df0b61d3b5a | 469 | __IO uint32_t CALIBRATION; |
| Michael J. Spencer |
2:1df0b61d3b5a | 470 | __IO uint32_t GPREG0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 471 | __IO uint32_t GPREG1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 472 | __IO uint32_t GPREG2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 473 | __IO uint32_t GPREG3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 474 | __IO uint32_t GPREG4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 475 | __IO uint8_t RTC_AUXEN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 476 | uint8_t RESERVED12[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 477 | __IO uint8_t RTC_AUX; |
| Michael J. Spencer |
2:1df0b61d3b5a | 478 | uint8_t RESERVED13[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 479 | __IO uint8_t ALSEC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 480 | uint8_t RESERVED14[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 481 | __IO uint8_t ALMIN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 482 | uint8_t RESERVED15[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 483 | __IO uint8_t ALHOUR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 484 | uint8_t RESERVED16[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 485 | __IO uint8_t ALDOM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 486 | uint8_t RESERVED17[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 487 | __IO uint8_t ALDOW; |
| Michael J. Spencer |
2:1df0b61d3b5a | 488 | uint8_t RESERVED18[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 489 | __IO uint16_t ALDOY; |
| Michael J. Spencer |
2:1df0b61d3b5a | 490 | uint16_t RESERVED19; |
| Michael J. Spencer |
2:1df0b61d3b5a | 491 | __IO uint8_t ALMON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 492 | uint8_t RESERVED20[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 493 | __IO uint16_t ALYEAR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 494 | uint16_t RESERVED21; |
| Michael J. Spencer |
2:1df0b61d3b5a | 495 | } LPC_RTC_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 496 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 497 | /*------------- Watchdog Timer (WDT) -----------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 498 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 499 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 500 | __IO uint8_t WDMOD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 501 | uint8_t RESERVED0[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 502 | __IO uint32_t WDTC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 503 | __O uint8_t WDFEED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 504 | uint8_t RESERVED1[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 505 | __I uint32_t WDTV; |
| Michael J. Spencer |
2:1df0b61d3b5a | 506 | __IO uint32_t WDCLKSEL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 507 | } LPC_WDT_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 508 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 509 | /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 510 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 511 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 512 | __IO uint32_t ADCR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 513 | __IO uint32_t ADGDR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 514 | uint32_t RESERVED0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 515 | __IO uint32_t ADINTEN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 516 | __I uint32_t ADDR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 517 | __I uint32_t ADDR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 518 | __I uint32_t ADDR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 519 | __I uint32_t ADDR3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 520 | __I uint32_t ADDR4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 521 | __I uint32_t ADDR5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 522 | __I uint32_t ADDR6; |
| Michael J. Spencer |
2:1df0b61d3b5a | 523 | __I uint32_t ADDR7; |
| Michael J. Spencer |
2:1df0b61d3b5a | 524 | __I uint32_t ADSTAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 525 | __IO uint32_t ADTRM; |
| Michael J. Spencer |
2:1df0b61d3b5a | 526 | } LPC_ADC_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 527 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 528 | /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 529 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 530 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 531 | __IO uint32_t DACR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 532 | __IO uint32_t DACCTRL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 533 | __IO uint16_t DACCNTVAL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 534 | } LPC_DAC_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 535 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 536 | /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 537 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 538 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 539 | __I uint32_t MCCON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 540 | __O uint32_t MCCON_SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 541 | __O uint32_t MCCON_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 542 | __I uint32_t MCCAPCON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 543 | __O uint32_t MCCAPCON_SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 544 | __O uint32_t MCCAPCON_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 545 | __IO uint32_t MCTIM0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 546 | __IO uint32_t MCTIM1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 547 | __IO uint32_t MCTIM2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 548 | __IO uint32_t MCPER0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 549 | __IO uint32_t MCPER1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 550 | __IO uint32_t MCPER2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 551 | __IO uint32_t MCPW0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 552 | __IO uint32_t MCPW1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 553 | __IO uint32_t MCPW2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 554 | __IO uint32_t MCDEADTIME; |
| Michael J. Spencer |
2:1df0b61d3b5a | 555 | __IO uint32_t MCCCP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 556 | __IO uint32_t MCCR0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 557 | __IO uint32_t MCCR1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 558 | __IO uint32_t MCCR2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 559 | __I uint32_t MCINTEN; |
| Michael J. Spencer |
2:1df0b61d3b5a | 560 | __O uint32_t MCINTEN_SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 561 | __O uint32_t MCINTEN_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 562 | __I uint32_t MCCNTCON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 563 | __O uint32_t MCCNTCON_SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 564 | __O uint32_t MCCNTCON_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 565 | __I uint32_t MCINTFLAG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 566 | __O uint32_t MCINTFLAG_SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 567 | __O uint32_t MCINTFLAG_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 568 | __O uint32_t MCCAP_CLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 569 | } LPC_MCPWM_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 570 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 571 | /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 572 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 573 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 574 | __O uint32_t QEICON; |
| Michael J. Spencer |
2:1df0b61d3b5a | 575 | __I uint32_t QEISTAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 576 | __IO uint32_t QEICONF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 577 | __I uint32_t QEIPOS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 578 | __IO uint32_t QEIMAXPOS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 579 | __IO uint32_t CMPOS0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 580 | __IO uint32_t CMPOS1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 581 | __IO uint32_t CMPOS2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 582 | __I uint32_t INXCNT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 583 | __IO uint32_t INXCMP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 584 | __IO uint32_t QEILOAD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 585 | __I uint32_t QEITIME; |
| Michael J. Spencer |
2:1df0b61d3b5a | 586 | __I uint32_t QEIVEL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 587 | __I uint32_t QEICAP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 588 | __IO uint32_t VELCOMP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 589 | __IO uint32_t FILTER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 590 | uint32_t RESERVED0[998]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 591 | __O uint32_t QEIIEC; |
| Michael J. Spencer |
2:1df0b61d3b5a | 592 | __O uint32_t QEIIES; |
| Michael J. Spencer |
2:1df0b61d3b5a | 593 | __I uint32_t QEIINTSTAT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 594 | __I uint32_t QEIIE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 595 | __O uint32_t QEICLR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 596 | __O uint32_t QEISET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 597 | } LPC_QEI_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 598 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 599 | /*------------- Controller Area Network (CAN) --------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 600 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 601 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 602 | __IO uint32_t mask[512]; /* ID Masks */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 603 | } LPC_CANAF_RAM_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 604 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 605 | typedef struct /* Acceptance Filter Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 606 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 607 | __IO uint32_t AFMR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 608 | __IO uint32_t SFF_sa; |
| Michael J. Spencer |
2:1df0b61d3b5a | 609 | __IO uint32_t SFF_GRP_sa; |
| Michael J. Spencer |
2:1df0b61d3b5a | 610 | __IO uint32_t EFF_sa; |
| Michael J. Spencer |
2:1df0b61d3b5a | 611 | __IO uint32_t EFF_GRP_sa; |
| Michael J. Spencer |
2:1df0b61d3b5a | 612 | __IO uint32_t ENDofTable; |
| Michael J. Spencer |
2:1df0b61d3b5a | 613 | __I uint32_t LUTerrAd; |
| Michael J. Spencer |
2:1df0b61d3b5a | 614 | __I uint32_t LUTerr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 615 | __IO uint32_t FCANIE; |
| Michael J. Spencer |
2:1df0b61d3b5a | 616 | __IO uint32_t FCANIC0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 617 | __IO uint32_t FCANIC1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 618 | } LPC_CANAF_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 619 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 620 | typedef struct /* Central Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 621 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 622 | __I uint32_t CANTxSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 623 | __I uint32_t CANRxSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 624 | __I uint32_t CANMSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 625 | } LPC_CANCR_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 626 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 627 | typedef struct /* Controller Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 628 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 629 | __IO uint32_t MOD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 630 | __O uint32_t CMR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 631 | __IO uint32_t GSR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 632 | __I uint32_t ICR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 633 | __IO uint32_t IER; |
| Michael J. Spencer |
2:1df0b61d3b5a | 634 | __IO uint32_t BTR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 635 | __IO uint32_t EWL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 636 | __I uint32_t SR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 637 | __IO uint32_t RFS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 638 | __IO uint32_t RID; |
| Michael J. Spencer |
2:1df0b61d3b5a | 639 | __IO uint32_t RDA; |
| Michael J. Spencer |
2:1df0b61d3b5a | 640 | __IO uint32_t RDB; |
| Michael J. Spencer |
2:1df0b61d3b5a | 641 | __IO uint32_t TFI1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 642 | __IO uint32_t TID1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 643 | __IO uint32_t TDA1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 644 | __IO uint32_t TDB1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 645 | __IO uint32_t TFI2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 646 | __IO uint32_t TID2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 647 | __IO uint32_t TDA2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 648 | __IO uint32_t TDB2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 649 | __IO uint32_t TFI3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 650 | __IO uint32_t TID3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 651 | __IO uint32_t TDA3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 652 | __IO uint32_t TDB3; |
| Michael J. Spencer |
2:1df0b61d3b5a | 653 | } LPC_CAN_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 654 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 655 | /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 656 | typedef struct /* Common Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 657 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 658 | __I uint32_t DMACIntStat; |
| Michael J. Spencer |
2:1df0b61d3b5a | 659 | __I uint32_t DMACIntTCStat; |
| Michael J. Spencer |
2:1df0b61d3b5a | 660 | __O uint32_t DMACIntTCClear; |
| Michael J. Spencer |
2:1df0b61d3b5a | 661 | __I uint32_t DMACIntErrStat; |
| Michael J. Spencer |
2:1df0b61d3b5a | 662 | __O uint32_t DMACIntErrClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 663 | __I uint32_t DMACRawIntTCStat; |
| Michael J. Spencer |
2:1df0b61d3b5a | 664 | __I uint32_t DMACRawIntErrStat; |
| Michael J. Spencer |
2:1df0b61d3b5a | 665 | __I uint32_t DMACEnbldChns; |
| Michael J. Spencer |
2:1df0b61d3b5a | 666 | __IO uint32_t DMACSoftBReq; |
| Michael J. Spencer |
2:1df0b61d3b5a | 667 | __IO uint32_t DMACSoftSReq; |
| Michael J. Spencer |
2:1df0b61d3b5a | 668 | __IO uint32_t DMACSoftLBReq; |
| Michael J. Spencer |
2:1df0b61d3b5a | 669 | __IO uint32_t DMACSoftLSReq; |
| Michael J. Spencer |
2:1df0b61d3b5a | 670 | __IO uint32_t DMACConfig; |
| Michael J. Spencer |
2:1df0b61d3b5a | 671 | __IO uint32_t DMACSync; |
| Michael J. Spencer |
2:1df0b61d3b5a | 672 | } LPC_GPDMA_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 673 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 674 | typedef struct /* Channel Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 675 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 676 | __IO uint32_t DMACCSrcAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 677 | __IO uint32_t DMACCDestAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 678 | __IO uint32_t DMACCLLI; |
| Michael J. Spencer |
2:1df0b61d3b5a | 679 | __IO uint32_t DMACCControl; |
| Michael J. Spencer |
2:1df0b61d3b5a | 680 | __IO uint32_t DMACCConfig; |
| Michael J. Spencer |
2:1df0b61d3b5a | 681 | } LPC_GPDMACH_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 682 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 683 | /*------------- Universal Serial Bus (USB) -----------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 684 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 685 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 686 | __I uint32_t HcRevision; /* USB Host Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 687 | __IO uint32_t HcControl; |
| Michael J. Spencer |
2:1df0b61d3b5a | 688 | __IO uint32_t HcCommandStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 689 | __IO uint32_t HcInterruptStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 690 | __IO uint32_t HcInterruptEnable; |
| Michael J. Spencer |
2:1df0b61d3b5a | 691 | __IO uint32_t HcInterruptDisable; |
| Michael J. Spencer |
2:1df0b61d3b5a | 692 | __IO uint32_t HcHCCA; |
| Michael J. Spencer |
2:1df0b61d3b5a | 693 | __I uint32_t HcPeriodCurrentED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 694 | __IO uint32_t HcControlHeadED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 695 | __IO uint32_t HcControlCurrentED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 696 | __IO uint32_t HcBulkHeadED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 697 | __IO uint32_t HcBulkCurrentED; |
| Michael J. Spencer |
2:1df0b61d3b5a | 698 | __I uint32_t HcDoneHead; |
| Michael J. Spencer |
2:1df0b61d3b5a | 699 | __IO uint32_t HcFmInterval; |
| Michael J. Spencer |
2:1df0b61d3b5a | 700 | __I uint32_t HcFmRemaining; |
| Michael J. Spencer |
2:1df0b61d3b5a | 701 | __I uint32_t HcFmNumber; |
| Michael J. Spencer |
2:1df0b61d3b5a | 702 | __IO uint32_t HcPeriodicStart; |
| Michael J. Spencer |
2:1df0b61d3b5a | 703 | __IO uint32_t HcLSTreshold; |
| Michael J. Spencer |
2:1df0b61d3b5a | 704 | __IO uint32_t HcRhDescriptorA; |
| Michael J. Spencer |
2:1df0b61d3b5a | 705 | __IO uint32_t HcRhDescriptorB; |
| Michael J. Spencer |
2:1df0b61d3b5a | 706 | __IO uint32_t HcRhStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 707 | __IO uint32_t HcRhPortStatus1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 708 | __IO uint32_t HcRhPortStatus2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 709 | uint32_t RESERVED0[40]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 710 | __I uint32_t Module_ID; |
| Michael J. Spencer |
2:1df0b61d3b5a | 711 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 712 | __I uint32_t OTGIntSt; /* USB On-The-Go Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 713 | __IO uint32_t OTGIntEn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 714 | __O uint32_t OTGIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 715 | __O uint32_t OTGIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 716 | __IO uint32_t OTGStCtrl; |
| Michael J. Spencer |
2:1df0b61d3b5a | 717 | __IO uint32_t OTGTmr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 718 | uint32_t RESERVED1[58]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 719 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 720 | __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 721 | __IO uint32_t USBDevIntEn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 722 | __O uint32_t USBDevIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 723 | __O uint32_t USBDevIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 724 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 725 | __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 726 | __I uint32_t USBCmdData; |
| Michael J. Spencer |
2:1df0b61d3b5a | 727 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 728 | __I uint32_t USBRxData; /* USB Device Transfer Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 729 | __O uint32_t USBTxData; |
| Michael J. Spencer |
2:1df0b61d3b5a | 730 | __I uint32_t USBRxPLen; |
| Michael J. Spencer |
2:1df0b61d3b5a | 731 | __O uint32_t USBTxPLen; |
| Michael J. Spencer |
2:1df0b61d3b5a | 732 | __IO uint32_t USBCtrl; |
| Michael J. Spencer |
2:1df0b61d3b5a | 733 | __O uint32_t USBDevIntPri; |
| Michael J. Spencer |
2:1df0b61d3b5a | 734 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 735 | __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 736 | __IO uint32_t USBEpIntEn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 737 | __O uint32_t USBEpIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 738 | __O uint32_t USBEpIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 739 | __O uint32_t USBEpIntPri; |
| Michael J. Spencer |
2:1df0b61d3b5a | 740 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 741 | __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 742 | __O uint32_t USBEpInd; |
| Michael J. Spencer |
2:1df0b61d3b5a | 743 | __IO uint32_t USBMaxPSize; |
| Michael J. Spencer |
2:1df0b61d3b5a | 744 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 745 | __I uint32_t USBDMARSt; /* USB Device DMA Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 746 | __O uint32_t USBDMARClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 747 | __O uint32_t USBDMARSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 748 | uint32_t RESERVED2[9]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 749 | __IO uint32_t USBUDCAH; |
| Michael J. Spencer |
2:1df0b61d3b5a | 750 | __I uint32_t USBEpDMASt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 751 | __O uint32_t USBEpDMAEn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 752 | __O uint32_t USBEpDMADis; |
| Michael J. Spencer |
2:1df0b61d3b5a | 753 | __I uint32_t USBDMAIntSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 754 | __IO uint32_t USBDMAIntEn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 755 | uint32_t RESERVED3[2]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 756 | __I uint32_t USBEoTIntSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 757 | __O uint32_t USBEoTIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 758 | __O uint32_t USBEoTIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 759 | __I uint32_t USBNDDRIntSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 760 | __O uint32_t USBNDDRIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 761 | __O uint32_t USBNDDRIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 762 | __I uint32_t USBSysErrIntSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 763 | __O uint32_t USBSysErrIntClr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 764 | __O uint32_t USBSysErrIntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 765 | uint32_t RESERVED4[15]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 766 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 767 | __I uint32_t I2C_RX; /* USB OTG I2C Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 768 | __O uint32_t I2C_WO; |
| Michael J. Spencer |
2:1df0b61d3b5a | 769 | __I uint32_t I2C_STS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 770 | __IO uint32_t I2C_CTL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 771 | __IO uint32_t I2C_CLKHI; |
| Michael J. Spencer |
2:1df0b61d3b5a | 772 | __O uint32_t I2C_CLKLO; |
| Michael J. Spencer |
2:1df0b61d3b5a | 773 | uint32_t RESERVED5[823]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 774 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 775 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 776 | __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 777 | __IO uint32_t OTGClkCtrl; |
| Michael J. Spencer |
2:1df0b61d3b5a | 778 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 779 | union { |
| Michael J. Spencer |
2:1df0b61d3b5a | 780 | __I uint32_t USBClkSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 781 | __I uint32_t OTGClkSt; |
| Michael J. Spencer |
2:1df0b61d3b5a | 782 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 783 | } LPC_USB_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 784 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 785 | /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 786 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 787 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 788 | __IO uint32_t MAC1; /* MAC Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 789 | __IO uint32_t MAC2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 790 | __IO uint32_t IPGT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 791 | __IO uint32_t IPGR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 792 | __IO uint32_t CLRT; |
| Michael J. Spencer |
2:1df0b61d3b5a | 793 | __IO uint32_t MAXF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 794 | __IO uint32_t SUPP; |
| Michael J. Spencer |
2:1df0b61d3b5a | 795 | __IO uint32_t TEST; |
| Michael J. Spencer |
2:1df0b61d3b5a | 796 | __IO uint32_t MCFG; |
| Michael J. Spencer |
2:1df0b61d3b5a | 797 | __IO uint32_t MCMD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 798 | __IO uint32_t MADR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 799 | __O uint32_t MWTD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 800 | __I uint32_t MRDD; |
| Michael J. Spencer |
2:1df0b61d3b5a | 801 | __I uint32_t MIND; |
| Michael J. Spencer |
2:1df0b61d3b5a | 802 | uint32_t RESERVED0[2]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 803 | __IO uint32_t SA0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 804 | __IO uint32_t SA1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 805 | __IO uint32_t SA2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 806 | uint32_t RESERVED1[45]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 807 | __IO uint32_t Command; /* Control Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 808 | __I uint32_t Status; |
| Michael J. Spencer |
2:1df0b61d3b5a | 809 | __IO uint32_t RxDescriptor; |
| Michael J. Spencer |
2:1df0b61d3b5a | 810 | __IO uint32_t RxStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 811 | __IO uint32_t RxDescriptorNumber; |
| Michael J. Spencer |
2:1df0b61d3b5a | 812 | __I uint32_t RxProduceIndex; |
| Michael J. Spencer |
2:1df0b61d3b5a | 813 | __IO uint32_t RxConsumeIndex; |
| Michael J. Spencer |
2:1df0b61d3b5a | 814 | __IO uint32_t TxDescriptor; |
| Michael J. Spencer |
2:1df0b61d3b5a | 815 | __IO uint32_t TxStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 816 | __IO uint32_t TxDescriptorNumber; |
| Michael J. Spencer |
2:1df0b61d3b5a | 817 | __IO uint32_t TxProduceIndex; |
| Michael J. Spencer |
2:1df0b61d3b5a | 818 | __I uint32_t TxConsumeIndex; |
| Michael J. Spencer |
2:1df0b61d3b5a | 819 | uint32_t RESERVED2[10]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 820 | __I uint32_t TSV0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 821 | __I uint32_t TSV1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 822 | __I uint32_t RSV; |
| Michael J. Spencer |
2:1df0b61d3b5a | 823 | uint32_t RESERVED3[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 824 | __IO uint32_t FlowControlCounter; |
| Michael J. Spencer |
2:1df0b61d3b5a | 825 | __I uint32_t FlowControlStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 826 | uint32_t RESERVED4[34]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 827 | __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 828 | __IO uint32_t RxFilterWoLStatus; |
| Michael J. Spencer |
2:1df0b61d3b5a | 829 | __IO uint32_t RxFilterWoLClear; |
| Michael J. Spencer |
2:1df0b61d3b5a | 830 | uint32_t RESERVED5; |
| Michael J. Spencer |
2:1df0b61d3b5a | 831 | __IO uint32_t HashFilterL; |
| Michael J. Spencer |
2:1df0b61d3b5a | 832 | __IO uint32_t HashFilterH; |
| Michael J. Spencer |
2:1df0b61d3b5a | 833 | uint32_t RESERVED6[882]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 834 | __I uint32_t IntStatus; /* Module Control Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 835 | __IO uint32_t IntEnable; |
| Michael J. Spencer |
2:1df0b61d3b5a | 836 | __O uint32_t IntClear; |
| Michael J. Spencer |
2:1df0b61d3b5a | 837 | __O uint32_t IntSet; |
| Michael J. Spencer |
2:1df0b61d3b5a | 838 | uint32_t RESERVED7; |
| Michael J. Spencer |
2:1df0b61d3b5a | 839 | __IO uint32_t PowerDown; |
| Michael J. Spencer |
2:1df0b61d3b5a | 840 | uint32_t RESERVED8; |
| Michael J. Spencer |
2:1df0b61d3b5a | 841 | __IO uint32_t Module_ID; |
| Michael J. Spencer |
2:1df0b61d3b5a | 842 | } LPC_EMAC_TypeDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 843 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 844 | #if defined ( __CC_ARM ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 845 | #pragma anon_unions |
| Michael J. Spencer |
2:1df0b61d3b5a | 846 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 847 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 848 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 849 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 850 | /* Peripheral memory map */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 851 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 852 | /* Base addresses */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 853 | #define LPC_FLASH_BASE (0x00000000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 854 | #define LPC_RAM_BASE (0x10000000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 855 | #define LPC_GPIO_BASE (0x2009C000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 856 | #define LPC_APB0_BASE (0x40000000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 857 | #define LPC_APB1_BASE (0x40080000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 858 | #define LPC_AHB_BASE (0x50000000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 859 | #define LPC_CM3_BASE (0xE0000000UL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 860 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 861 | /* APB0 peripherals */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 862 | #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 863 | #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 864 | #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 865 | #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 866 | #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 867 | #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 868 | #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 869 | #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 870 | #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 871 | #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) |
| Michael J. Spencer |
2:1df0b61d3b5a | 872 | #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 873 | #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 874 | #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 875 | #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 876 | #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 877 | #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 878 | #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 879 | #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 880 | #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 881 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 882 | /* APB1 peripherals */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 883 | #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 884 | #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 885 | #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 886 | #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 887 | #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 888 | #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 889 | #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 890 | #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 891 | #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 892 | #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 893 | #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 894 | #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 895 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 896 | /* AHB peripherals */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 897 | #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 898 | #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 899 | #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) |
| Michael J. Spencer |
2:1df0b61d3b5a | 900 | #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) |
| Michael J. Spencer |
2:1df0b61d3b5a | 901 | #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) |
| Michael J. Spencer |
2:1df0b61d3b5a | 902 | #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) |
| Michael J. Spencer |
2:1df0b61d3b5a | 903 | #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) |
| Michael J. Spencer |
2:1df0b61d3b5a | 904 | #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) |
| Michael J. Spencer |
2:1df0b61d3b5a | 905 | #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) |
| Michael J. Spencer |
2:1df0b61d3b5a | 906 | #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) |
| Michael J. Spencer |
2:1df0b61d3b5a | 907 | #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 908 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 909 | /* GPIOs */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 910 | #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) |
| Michael J. Spencer |
2:1df0b61d3b5a | 911 | #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) |
| Michael J. Spencer |
2:1df0b61d3b5a | 912 | #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) |
| Michael J. Spencer |
2:1df0b61d3b5a | 913 | #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) |
| Michael J. Spencer |
2:1df0b61d3b5a | 914 | #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) |
| Michael J. Spencer |
2:1df0b61d3b5a | 915 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 916 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 917 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 918 | /* Peripheral declaration */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 919 | /******************************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 920 | #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 921 | #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 922 | #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 923 | #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 924 | #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 925 | #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 926 | #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 927 | #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 928 | #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 929 | #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 930 | #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 931 | #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 932 | #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 933 | #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 934 | #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 935 | #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 936 | #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 937 | #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 938 | #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 939 | #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 940 | #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 941 | #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 942 | #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 943 | #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 944 | #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 945 | #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 946 | #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 947 | #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 948 | #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 949 | #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) |
| Michael J. Spencer |
2:1df0b61d3b5a | 950 | #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 951 | #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 952 | #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 953 | #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 954 | #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 955 | #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 956 | #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 957 | #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 958 | #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 959 | #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 960 | #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 961 | #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 962 | #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 963 | #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 964 | #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 965 | #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 966 | #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) |
| Michael J. Spencer |
2:1df0b61d3b5a | 967 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 968 | #endif // __LPC17xx_H__ |