Fork of Smoothie to port to mbed non-LPC targets.
Fork of Smoothie by
libs/LPC17xx/LPC17xxLib/src/lpc17xx_rit.c@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Michael J. Spencer |
2:1df0b61d3b5a | 1 | #ifdef __LPC17XX__ |
Michael J. Spencer |
2:1df0b61d3b5a | 2 | |
Michael J. Spencer |
2:1df0b61d3b5a | 3 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 4 | * $Id$ lpc17xx_rit.c 2010-05-21 |
Michael J. Spencer |
2:1df0b61d3b5a | 5 | *//** |
Michael J. Spencer |
2:1df0b61d3b5a | 6 | * @file lpc17xx_rit.c |
Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @brief Contains all functions support for RIT firmware library on LPC17xx |
Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @version 2.0 |
Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @date 21. May. 2010 |
Michael J. Spencer |
2:1df0b61d3b5a | 10 | * @author NXP MCU SW Application Team |
Michael J. Spencer |
2:1df0b61d3b5a | 11 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 12 | * Copyright(C) 2010, NXP Semiconductor |
Michael J. Spencer |
2:1df0b61d3b5a | 13 | * All rights reserved. |
Michael J. Spencer |
2:1df0b61d3b5a | 14 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 15 | *********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 16 | * Software that is described herein is for illustrative purposes only |
Michael J. Spencer |
2:1df0b61d3b5a | 17 | * which provides customers with programming information regarding the |
Michael J. Spencer |
2:1df0b61d3b5a | 18 | * products. This software is supplied "AS IS" without any warranties. |
Michael J. Spencer |
2:1df0b61d3b5a | 19 | * NXP Semiconductors assumes no responsibility or liability for the |
Michael J. Spencer |
2:1df0b61d3b5a | 20 | * use of the software, conveys no license or title under any patent, |
Michael J. Spencer |
2:1df0b61d3b5a | 21 | * copyright, or mask work right to the product. NXP Semiconductors |
Michael J. Spencer |
2:1df0b61d3b5a | 22 | * reserves the right to make changes in the software without |
Michael J. Spencer |
2:1df0b61d3b5a | 23 | * notification. NXP Semiconductors also make no representation or |
Michael J. Spencer |
2:1df0b61d3b5a | 24 | * warranty that such application will be suitable for the specified |
Michael J. Spencer |
2:1df0b61d3b5a | 25 | * use without further testing or modification. |
Michael J. Spencer |
2:1df0b61d3b5a | 26 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 27 | |
Michael J. Spencer |
2:1df0b61d3b5a | 28 | /* Peripheral group ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 29 | /** @addtogroup RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
Michael J. Spencer |
2:1df0b61d3b5a | 33 | /* Includes ------------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 34 | #include "lpc17xx_rit.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 35 | #include "lpc17xx_clkpwr.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 36 | |
Michael J. Spencer |
2:1df0b61d3b5a | 37 | /* If this source file built with example, the LPC17xx FW library configuration |
Michael J. Spencer |
2:1df0b61d3b5a | 38 | * file in each example directory ("lpc17xx_libcfg.h") must be included, |
Michael J. Spencer |
2:1df0b61d3b5a | 39 | * otherwise the default FW library configuration file must be included instead |
Michael J. Spencer |
2:1df0b61d3b5a | 40 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __BUILD_WITH_EXAMPLE__ |
Michael J. Spencer |
2:1df0b61d3b5a | 42 | #include "lpc17xx_libcfg.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 43 | #else |
Michael J. Spencer |
2:1df0b61d3b5a | 44 | #include "lpc17xx_libcfg_default.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 45 | #endif /* __BUILD_WITH_EXAMPLE__ */ |
Michael J. Spencer |
2:1df0b61d3b5a | 46 | |
Michael J. Spencer |
2:1df0b61d3b5a | 47 | #ifdef _RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 48 | |
Michael J. Spencer |
2:1df0b61d3b5a | 49 | /* Public Functions ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 50 | /** @addtogroup RIT_Public_Functions |
Michael J. Spencer |
2:1df0b61d3b5a | 51 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 52 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 53 | |
Michael J. Spencer |
2:1df0b61d3b5a | 54 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 55 | * @brief Initial for RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 56 | * - Turn on power and clock |
Michael J. Spencer |
2:1df0b61d3b5a | 57 | * - Setup default register values |
Michael J. Spencer |
2:1df0b61d3b5a | 58 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 59 | * @return None |
Michael J. Spencer |
2:1df0b61d3b5a | 60 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 61 | void RIT_Init(LPC_RIT_TypeDef *RITx) |
Michael J. Spencer |
2:1df0b61d3b5a | 62 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 63 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 64 | CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRIT, ENABLE); |
Michael J. Spencer |
2:1df0b61d3b5a | 65 | //Set up default register values |
Michael J. Spencer |
2:1df0b61d3b5a | 66 | RITx->RICOMPVAL = 0xFFFFFFFF; |
Michael J. Spencer |
2:1df0b61d3b5a | 67 | RITx->RIMASK = 0x00000000; |
Michael J. Spencer |
2:1df0b61d3b5a | 68 | RITx->RICTRL = 0x0C; |
Michael J. Spencer |
2:1df0b61d3b5a | 69 | RITx->RICOUNTER = 0x00000000; |
Michael J. Spencer |
2:1df0b61d3b5a | 70 | // Turn on power and clock |
Michael J. Spencer |
2:1df0b61d3b5a | 71 | |
Michael J. Spencer |
2:1df0b61d3b5a | 72 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 73 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 74 | * @brief DeInitial for RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 75 | * - Turn off power and clock |
Michael J. Spencer |
2:1df0b61d3b5a | 76 | * - ReSetup default register values |
Michael J. Spencer |
2:1df0b61d3b5a | 77 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 78 | * @return None |
Michael J. Spencer |
2:1df0b61d3b5a | 79 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 80 | void RIT_DeInit(LPC_RIT_TypeDef *RITx) |
Michael J. Spencer |
2:1df0b61d3b5a | 81 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 82 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 83 | |
Michael J. Spencer |
2:1df0b61d3b5a | 84 | // Turn off power and clock |
Michael J. Spencer |
2:1df0b61d3b5a | 85 | CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCRIT, DISABLE); |
Michael J. Spencer |
2:1df0b61d3b5a | 86 | //ReSetup default register values |
Michael J. Spencer |
2:1df0b61d3b5a | 87 | RITx->RICOMPVAL = 0xFFFFFFFF; |
Michael J. Spencer |
2:1df0b61d3b5a | 88 | RITx->RIMASK = 0x00000000; |
Michael J. Spencer |
2:1df0b61d3b5a | 89 | RITx->RICTRL = 0x0C; |
Michael J. Spencer |
2:1df0b61d3b5a | 90 | RITx->RICOUNTER = 0x00000000; |
Michael J. Spencer |
2:1df0b61d3b5a | 91 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 92 | |
Michael J. Spencer |
2:1df0b61d3b5a | 93 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 94 | * @brief Set compare value, mask value and time counter value |
Michael J. Spencer |
2:1df0b61d3b5a | 95 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 96 | * @param[in] time_interval: timer interval value (ms) |
Michael J. Spencer |
2:1df0b61d3b5a | 97 | * @return None |
Michael J. Spencer |
2:1df0b61d3b5a | 98 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 99 | void RIT_TimerConfig(LPC_RIT_TypeDef *RITx, uint32_t time_interval) |
Michael J. Spencer |
2:1df0b61d3b5a | 100 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 101 | uint32_t clock_rate, cmp_value; |
Michael J. Spencer |
2:1df0b61d3b5a | 102 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 103 | |
Michael J. Spencer |
2:1df0b61d3b5a | 104 | // Get PCLK value of RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 105 | clock_rate = CLKPWR_GetPCLK(CLKPWR_PCLKSEL_RIT); |
Michael J. Spencer |
2:1df0b61d3b5a | 106 | |
Michael J. Spencer |
2:1df0b61d3b5a | 107 | /* calculate compare value for RIT to generate interrupt at |
Michael J. Spencer |
2:1df0b61d3b5a | 108 | * specified time interval |
Michael J. Spencer |
2:1df0b61d3b5a | 109 | * COMPVAL = (RIT_PCLK * time_interval)/1000 |
Michael J. Spencer |
2:1df0b61d3b5a | 110 | * (with time_interval unit is millisecond) |
Michael J. Spencer |
2:1df0b61d3b5a | 111 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 112 | cmp_value = (clock_rate /1000) * time_interval; |
Michael J. Spencer |
2:1df0b61d3b5a | 113 | RITx->RICOMPVAL = cmp_value; |
Michael J. Spencer |
2:1df0b61d3b5a | 114 | |
Michael J. Spencer |
2:1df0b61d3b5a | 115 | /* Set timer enable clear bit to clear timer to 0 whenever |
Michael J. Spencer |
2:1df0b61d3b5a | 116 | * counter value equals the contents of RICOMPVAL |
Michael J. Spencer |
2:1df0b61d3b5a | 117 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 118 | RITx->RICTRL |= (1<<1); |
Michael J. Spencer |
2:1df0b61d3b5a | 119 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 120 | |
Michael J. Spencer |
2:1df0b61d3b5a | 121 | |
Michael J. Spencer |
2:1df0b61d3b5a | 122 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 123 | * @brief Enable/Disable Timer |
Michael J. Spencer |
2:1df0b61d3b5a | 124 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 125 | * @param[in] NewState New State of this function |
Michael J. Spencer |
2:1df0b61d3b5a | 126 | * -ENABLE: Enable Timer |
Michael J. Spencer |
2:1df0b61d3b5a | 127 | * -DISABLE: Disable Timer |
Michael J. Spencer |
2:1df0b61d3b5a | 128 | * @return None |
Michael J. Spencer |
2:1df0b61d3b5a | 129 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 130 | void RIT_Cmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState) |
Michael J. Spencer |
2:1df0b61d3b5a | 131 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 132 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 133 | CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); |
Michael J. Spencer |
2:1df0b61d3b5a | 134 | |
Michael J. Spencer |
2:1df0b61d3b5a | 135 | //Enable or Disable Timer |
Michael J. Spencer |
2:1df0b61d3b5a | 136 | if(NewState==ENABLE) |
Michael J. Spencer |
2:1df0b61d3b5a | 137 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 138 | RITx->RICTRL |= RIT_CTRL_TEN; |
Michael J. Spencer |
2:1df0b61d3b5a | 139 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 140 | else |
Michael J. Spencer |
2:1df0b61d3b5a | 141 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 142 | RITx->RICTRL &= ~RIT_CTRL_TEN; |
Michael J. Spencer |
2:1df0b61d3b5a | 143 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 144 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 145 | |
Michael J. Spencer |
2:1df0b61d3b5a | 146 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 147 | * @brief Timer Enable/Disable on debug |
Michael J. Spencer |
2:1df0b61d3b5a | 148 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 149 | * @param[in] NewState New State of this function |
Michael J. Spencer |
2:1df0b61d3b5a | 150 | * -ENABLE: The timer is halted whenever a hardware break condition occurs |
Michael J. Spencer |
2:1df0b61d3b5a | 151 | * -DISABLE: Hardware break has no effect on the timer operation |
Michael J. Spencer |
2:1df0b61d3b5a | 152 | * @return None |
Michael J. Spencer |
2:1df0b61d3b5a | 153 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 154 | void RIT_TimerDebugCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState) |
Michael J. Spencer |
2:1df0b61d3b5a | 155 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 156 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 157 | CHECK_PARAM(PARAM_FUNCTIONALSTATE(NewState)); |
Michael J. Spencer |
2:1df0b61d3b5a | 158 | |
Michael J. Spencer |
2:1df0b61d3b5a | 159 | //Timer Enable/Disable on break |
Michael J. Spencer |
2:1df0b61d3b5a | 160 | if(NewState==ENABLE) |
Michael J. Spencer |
2:1df0b61d3b5a | 161 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 162 | RITx->RICTRL |= RIT_CTRL_ENBR; |
Michael J. Spencer |
2:1df0b61d3b5a | 163 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 164 | else |
Michael J. Spencer |
2:1df0b61d3b5a | 165 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 166 | RITx->RICTRL &= ~RIT_CTRL_ENBR; |
Michael J. Spencer |
2:1df0b61d3b5a | 167 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 168 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 169 | /******************************************************************************//* |
Michael J. Spencer |
2:1df0b61d3b5a | 170 | * @brief Check whether interrupt flag is set or not |
Michael J. Spencer |
2:1df0b61d3b5a | 171 | * @param[in] RITx is RIT peripheral selected, should be: LPC_RIT |
Michael J. Spencer |
2:1df0b61d3b5a | 172 | * @return Current interrupt status, could be: SET/RESET |
Michael J. Spencer |
2:1df0b61d3b5a | 173 | *******************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 174 | IntStatus RIT_GetIntStatus(LPC_RIT_TypeDef *RITx) |
Michael J. Spencer |
2:1df0b61d3b5a | 175 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 176 | uint8_t result; |
Michael J. Spencer |
2:1df0b61d3b5a | 177 | CHECK_PARAM(PARAM_RITx(RITx)); |
Michael J. Spencer |
2:1df0b61d3b5a | 178 | if((RITx->RICTRL&RIT_CTRL_INTEN)==1) result= SET; |
Michael J. Spencer |
2:1df0b61d3b5a | 179 | else return RESET; |
Michael J. Spencer |
2:1df0b61d3b5a | 180 | //clear interrupt flag |
Michael J. Spencer |
2:1df0b61d3b5a | 181 | RITx->RICTRL |= RIT_CTRL_INTEN; |
Michael J. Spencer |
2:1df0b61d3b5a | 182 | return (IntStatus)result; |
Michael J. Spencer |
2:1df0b61d3b5a | 183 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 184 | |
Michael J. Spencer |
2:1df0b61d3b5a | 185 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 186 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 187 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 188 | |
Michael J. Spencer |
2:1df0b61d3b5a | 189 | #endif /* _RIT */ |
Michael J. Spencer |
2:1df0b61d3b5a | 190 | |
Michael J. Spencer |
2:1df0b61d3b5a | 191 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 192 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 193 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 194 | |
Michael J. Spencer |
2:1df0b61d3b5a | 195 | /* --------------------------------- End Of File ------------------------------ */ |
Michael J. Spencer |
2:1df0b61d3b5a | 196 | #endif /* __LPC17XX__ */ |