Fork of Smoothie to port to mbed non-LPC targets.
Fork of Smoothie by
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_i2s.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_i2s.h 2011-06-06 |
Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_i2s.h |
Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for I2S firmware library on LPC17xx |
Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 3.1 |
Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 06. June. 2011 |
Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2011, NXP Semiconductor |
Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup I2S I2S (Inter-IC Sound bus) |
Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_I2S_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_I2S_H_ |
Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
Michael J. Spencer |
2:1df0b61d3b5a | 46 | /* Public Macros -------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 47 | /** @defgroup I2S_Public_Macros I2S Public Macros |
Michael J. Spencer |
2:1df0b61d3b5a | 48 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 49 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 50 | |
Michael J. Spencer |
2:1df0b61d3b5a | 51 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 52 | * I2S configuration parameter defines |
Michael J. Spencer |
2:1df0b61d3b5a | 53 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 54 | /** I2S Wordwidth bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 55 | #define I2S_WORDWIDTH_8 ((uint32_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 56 | #define I2S_WORDWIDTH_16 ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 57 | #define I2S_WORDWIDTH_32 ((uint32_t)(3)) |
Michael J. Spencer |
2:1df0b61d3b5a | 58 | /** I2S Channel bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 59 | #define I2S_STEREO ((uint32_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 60 | #define I2S_MONO ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 61 | /** I2S Master/Slave mode bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 62 | #define I2S_MASTER_MODE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 63 | #define I2S_SLAVE_MODE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 64 | /** I2S Stop bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 65 | #define I2S_STOP_ENABLE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define I2S_STOP_DISABLE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 67 | /** I2S Reset bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 68 | #define I2S_RESET_ENABLE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 69 | #define I2S_RESET_DISABLE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 70 | /** I2S Mute bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 71 | #define I2S_MUTE_ENABLE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 72 | #define I2S_MUTE_DISABLE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 73 | /** I2S Transmit/Receive bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 74 | #define I2S_TX_MODE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 75 | #define I2S_RX_MODE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 76 | /** I2S Clock Select bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 77 | #define I2S_CLKSEL_FRDCLK ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define I2S_CLKSEL_MCLK ((uint8_t)(2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 79 | /** I2S 4-pin Mode bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 80 | #define I2S_4PIN_ENABLE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 81 | #define I2S_4PIN_DISABLE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 82 | /** I2S MCLK Enable bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 83 | #define I2S_MCLK_ENABLE ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 84 | #define I2S_MCLK_DISABLE ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 85 | /** I2S select DMA bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 86 | #define I2S_DMA_1 ((uint8_t)(0)) |
Michael J. Spencer |
2:1df0b61d3b5a | 87 | #define I2S_DMA_2 ((uint8_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 88 | |
Michael J. Spencer |
2:1df0b61d3b5a | 89 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 90 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 91 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 92 | |
Michael J. Spencer |
2:1df0b61d3b5a | 93 | /* Private Macros ------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 94 | /** @defgroup I2S_Private_Macros I2S Private Macros |
Michael J. Spencer |
2:1df0b61d3b5a | 95 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 96 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 97 | |
Michael J. Spencer |
2:1df0b61d3b5a | 98 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 99 | * Macro defines for DAO-Digital Audio Output register |
Michael J. Spencer |
2:1df0b61d3b5a | 100 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 101 | /** I2S wordwide - the number of bytes in data*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 103 | #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 104 | #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 105 | /** I2S control mono or stereo format */ |
Michael J. Spencer |
2:1df0b61d3b5a | 106 | #define I2S_DAO_MONO ((uint32_t)(1<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 107 | /** I2S control stop mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 108 | #define I2S_DAO_STOP ((uint32_t)(1<<3)) |
Michael J. Spencer |
2:1df0b61d3b5a | 109 | /** I2S control reset mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 110 | #define I2S_DAO_RESET ((uint32_t)(1<<4)) |
Michael J. Spencer |
2:1df0b61d3b5a | 111 | /** I2S control master/slave mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 112 | #define I2S_DAO_SLAVE ((uint32_t)(1<<5)) |
Michael J. Spencer |
2:1df0b61d3b5a | 113 | /** I2S word select half period minus one */ |
Michael J. Spencer |
2:1df0b61d3b5a | 114 | #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6)) |
Michael J. Spencer |
2:1df0b61d3b5a | 115 | /** I2S control mute mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 116 | #define I2S_DAO_MUTE ((uint32_t)(1<<15)) |
Michael J. Spencer |
2:1df0b61d3b5a | 117 | |
Michael J. Spencer |
2:1df0b61d3b5a | 118 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 119 | * Macro defines for DAI-Digital Audio Input register |
Michael J. Spencer |
2:1df0b61d3b5a | 120 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 121 | /** I2S wordwide - the number of bytes in data*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 122 | #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 123 | #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 124 | #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 125 | /** I2S control mono or stereo format */ |
Michael J. Spencer |
2:1df0b61d3b5a | 126 | #define I2S_DAI_MONO ((uint32_t)(1<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 127 | /** I2S control stop mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 128 | #define I2S_DAI_STOP ((uint32_t)(1<<3)) |
Michael J. Spencer |
2:1df0b61d3b5a | 129 | /** I2S control reset mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 130 | #define I2S_DAI_RESET ((uint32_t)(1<<4)) |
Michael J. Spencer |
2:1df0b61d3b5a | 131 | /** I2S control master/slave mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 132 | #define I2S_DAI_SLAVE ((uint32_t)(1<<5)) |
Michael J. Spencer |
2:1df0b61d3b5a | 133 | /** I2S word select half period minus one (9 bits)*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 134 | #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6)) |
Michael J. Spencer |
2:1df0b61d3b5a | 135 | /** I2S control mute mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 136 | #define I2S_DAI_MUTE ((uint32_t)(1<<15)) |
Michael J. Spencer |
2:1df0b61d3b5a | 137 | |
Michael J. Spencer |
2:1df0b61d3b5a | 138 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 139 | * Macro defines for STAT register (Status Feedback register) |
Michael J. Spencer |
2:1df0b61d3b5a | 140 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 141 | /** I2S Status Receive or Transmit Interrupt */ |
Michael J. Spencer |
2:1df0b61d3b5a | 142 | #define I2S_STATE_IRQ ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 143 | /** I2S Status Receive or Transmit DMA1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 144 | #define I2S_STATE_DMA1 ((uint32_t)(1<<1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 145 | /** I2S Status Receive or Transmit DMA2 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 146 | #define I2S_STATE_DMA2 ((uint32_t)(1<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 147 | /** I2S Status Current level of the Receive FIFO (5 bits)*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 148 | #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 149 | /** I2S Status Current level of the Transmit FIFO (5 bits)*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 150 | #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16)) |
Michael J. Spencer |
2:1df0b61d3b5a | 151 | |
Michael J. Spencer |
2:1df0b61d3b5a | 152 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 153 | * Macro defines for DMA1 register (DMA1 Configuration register) |
Michael J. Spencer |
2:1df0b61d3b5a | 154 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 155 | /** I2S control DMA1 for I2S receive */ |
Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define I2S_DMA1_RX_ENABLE ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 157 | /** I2S control DMA1 for I2S transmit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 159 | /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 160 | #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 161 | /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 162 | #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
Michael J. Spencer |
2:1df0b61d3b5a | 163 | |
Michael J. Spencer |
2:1df0b61d3b5a | 164 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 165 | * Macro defines for DMA2 register (DMA2 Configuration register) |
Michael J. Spencer |
2:1df0b61d3b5a | 166 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 167 | /** I2S control DMA2 for I2S receive */ |
Michael J. Spencer |
2:1df0b61d3b5a | 168 | #define I2S_DMA2_RX_ENABLE ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 169 | /** I2S control DMA1 for I2S transmit */ |
Michael J. Spencer |
2:1df0b61d3b5a | 170 | #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 171 | /** I2S set FIFO level that trigger a receive DMA request on DMA1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 173 | /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 174 | #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
Michael J. Spencer |
2:1df0b61d3b5a | 175 | |
Michael J. Spencer |
2:1df0b61d3b5a | 176 | /*********************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 177 | * Macro defines for IRQ register (Interrupt Request Control register) |
Michael J. Spencer |
2:1df0b61d3b5a | 178 | **********************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 179 | /** I2S control I2S receive interrupt */ |
Michael J. Spencer |
2:1df0b61d3b5a | 180 | #define I2S_IRQ_RX_ENABLE ((uint32_t)(1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 181 | /** I2S control I2S transmit interrupt */ |
Michael J. Spencer |
2:1df0b61d3b5a | 182 | #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1)) |
Michael J. Spencer |
2:1df0b61d3b5a | 183 | /** I2S set the FIFO level on which to create an irq request */ |
Michael J. Spencer |
2:1df0b61d3b5a | 184 | #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 185 | /** I2S set the FIFO level on which to create an irq request */ |
Michael J. Spencer |
2:1df0b61d3b5a | 186 | #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16)) |
Michael J. Spencer |
2:1df0b61d3b5a | 187 | |
Michael J. Spencer |
2:1df0b61d3b5a | 188 | /********************************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 189 | * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register) |
Michael J. Spencer |
2:1df0b61d3b5a | 190 | *********************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 191 | /** I2S Transmit MCLK rate denominator */ |
Michael J. Spencer |
2:1df0b61d3b5a | 192 | #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
Michael J. Spencer |
2:1df0b61d3b5a | 193 | /** I2S Transmit MCLK rate denominator */ |
Michael J. Spencer |
2:1df0b61d3b5a | 194 | #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 195 | /** I2S Receive MCLK rate denominator */ |
Michael J. Spencer |
2:1df0b61d3b5a | 196 | #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF)) |
Michael J. Spencer |
2:1df0b61d3b5a | 197 | /** I2S Receive MCLK rate denominator */ |
Michael J. Spencer |
2:1df0b61d3b5a | 198 | #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8)) |
Michael J. Spencer |
2:1df0b61d3b5a | 199 | |
Michael J. Spencer |
2:1df0b61d3b5a | 200 | /*************************************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 201 | * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register) |
Michael J. Spencer |
2:1df0b61d3b5a | 202 | **************************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 203 | #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 204 | #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F)) |
Michael J. Spencer |
2:1df0b61d3b5a | 205 | |
Michael J. Spencer |
2:1df0b61d3b5a | 206 | /**********************************************************************************//** |
Michael J. Spencer |
2:1df0b61d3b5a | 207 | * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register) |
Michael J. Spencer |
2:1df0b61d3b5a | 208 | ************************************************************************************/ |
Michael J. Spencer |
2:1df0b61d3b5a | 209 | /** I2S Transmit select clock source (2 bits)*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 210 | #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
Michael J. Spencer |
2:1df0b61d3b5a | 211 | /** I2S Transmit control 4-pin mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 212 | #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 213 | /** I2S Transmit control the TX_MCLK output */ |
Michael J. Spencer |
2:1df0b61d3b5a | 214 | #define I2S_TXMODE_MCENA ((uint32_t)(1<<3)) |
Michael J. Spencer |
2:1df0b61d3b5a | 215 | /** I2S Receive select clock source */ |
Michael J. Spencer |
2:1df0b61d3b5a | 216 | #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03)) |
Michael J. Spencer |
2:1df0b61d3b5a | 217 | /** I2S Receive control 4-pin mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 218 | #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 219 | /** I2S Receive control the TX_MCLK output */ |
Michael J. Spencer |
2:1df0b61d3b5a | 220 | #define I2S_RXMODE_MCENA ((uint32_t)(1<<3)) |
Michael J. Spencer |
2:1df0b61d3b5a | 221 | |
Michael J. Spencer |
2:1df0b61d3b5a | 222 | |
Michael J. Spencer |
2:1df0b61d3b5a | 223 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 224 | /** Macro to determine if it is valid I2S peripheral */ |
Michael J. Spencer |
2:1df0b61d3b5a | 225 | #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S)) |
Michael J. Spencer |
2:1df0b61d3b5a | 226 | /** Macro to check Data to send valid */ |
Michael J. Spencer |
2:1df0b61d3b5a | 227 | #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) |
Michael J. Spencer |
2:1df0b61d3b5a | 228 | /* Macro check I2S word width type */ |
Michael J. Spencer |
2:1df0b61d3b5a | 229 | #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\ |
Michael J. Spencer |
2:1df0b61d3b5a | 230 | ||(n==I2S_WORDWIDTH_32)) |
Michael J. Spencer |
2:1df0b61d3b5a | 231 | /* Macro check I2S channel type */ |
Michael J. Spencer |
2:1df0b61d3b5a | 232 | #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO)) |
Michael J. Spencer |
2:1df0b61d3b5a | 233 | /* Macro check I2S master/slave mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 234 | #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 235 | /* Macro check I2S stop mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 236 | #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 237 | /* Macro check I2S reset mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 238 | #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 239 | /* Macro check I2S reset mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 240 | #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 241 | /* Macro check I2S transmit/receive mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 242 | #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 243 | /* Macro check I2S clock select mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 244 | #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK)) |
Michael J. Spencer |
2:1df0b61d3b5a | 245 | /* Macro check I2S 4-pin mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 246 | #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 247 | /* Macro check I2S MCLK mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 248 | #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE)) |
Michael J. Spencer |
2:1df0b61d3b5a | 249 | /* Macro check I2S DMA mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 250 | #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2)) |
Michael J. Spencer |
2:1df0b61d3b5a | 251 | /* Macro check I2S DMA depth value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 252 | #define PARAM_I2S_DMA_DEPTH(n) (n<=31) |
Michael J. Spencer |
2:1df0b61d3b5a | 253 | /* Macro check I2S irq level value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 254 | #define PARAM_I2S_IRQ_LEVEL(n) (n<=31) |
Michael J. Spencer |
2:1df0b61d3b5a | 255 | /* Macro check I2S half-period value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 256 | #define PARAM_I2S_HALFPERIOD(n) (n<512) |
Michael J. Spencer |
2:1df0b61d3b5a | 257 | /* Macro check I2S bit-rate value */ |
Michael J. Spencer |
2:1df0b61d3b5a | 258 | #define PARAM_I2S_BITRATE(n) (n<=63) |
Michael J. Spencer |
2:1df0b61d3b5a | 259 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 260 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 261 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 262 | |
Michael J. Spencer |
2:1df0b61d3b5a | 263 | |
Michael J. Spencer |
2:1df0b61d3b5a | 264 | |
Michael J. Spencer |
2:1df0b61d3b5a | 265 | /* Public Types --------------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 266 | /** @defgroup I2S_Public_Types I2S Public Types |
Michael J. Spencer |
2:1df0b61d3b5a | 267 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 268 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 269 | |
Michael J. Spencer |
2:1df0b61d3b5a | 270 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 271 | * @brief I2S configuration structure definition |
Michael J. Spencer |
2:1df0b61d3b5a | 272 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 273 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 274 | uint8_t wordwidth; /** the number of bytes in data as follow: |
Michael J. Spencer |
2:1df0b61d3b5a | 275 | -I2S_WORDWIDTH_8: 8 bit data |
Michael J. Spencer |
2:1df0b61d3b5a | 276 | -I2S_WORDWIDTH_16: 16 bit data |
Michael J. Spencer |
2:1df0b61d3b5a | 277 | -I2S_WORDWIDTH_32: 32 bit data */ |
Michael J. Spencer |
2:1df0b61d3b5a | 278 | uint8_t mono; /** Set mono/stereo mode, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 279 | - I2S_STEREO: stereo mode |
Michael J. Spencer |
2:1df0b61d3b5a | 280 | - I2S_MONO: mono mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 281 | uint8_t stop; /** Disables accesses on FIFOs, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 282 | - I2S_STOP_ENABLE: enable stop mode |
Michael J. Spencer |
2:1df0b61d3b5a | 283 | - I2S_STOP_DISABLE: disable stop mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 284 | uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 285 | - I2S_RESET_ENABLE: enable reset mode |
Michael J. Spencer |
2:1df0b61d3b5a | 286 | - I2S_RESET_DISABLE: disable reset mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 287 | uint8_t ws_sel; /** Set Master/Slave mode, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 288 | - I2S_MASTER_MODE: I2S master mode |
Michael J. Spencer |
2:1df0b61d3b5a | 289 | - I2S_SLAVE_MODE: I2S slave mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 290 | uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be: |
Michael J. Spencer |
2:1df0b61d3b5a | 291 | - I2S_MUTE_ENABLE: enable mute mode |
Michael J. Spencer |
2:1df0b61d3b5a | 292 | - I2S_MUTE_DISABLE: disable mute mode */ |
Michael J. Spencer |
2:1df0b61d3b5a | 293 | uint8_t Reserved0[2]; |
Michael J. Spencer |
2:1df0b61d3b5a | 294 | } I2S_CFG_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 295 | |
Michael J. Spencer |
2:1df0b61d3b5a | 296 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 297 | * @brief I2S DMA configuration structure definition |
Michael J. Spencer |
2:1df0b61d3b5a | 298 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 299 | typedef struct { |
Michael J. Spencer |
2:1df0b61d3b5a | 300 | uint8_t DMAIndex; /** Select DMA1 or DMA2, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 301 | - I2S_DMA_1: DMA1 |
Michael J. Spencer |
2:1df0b61d3b5a | 302 | - I2S_DMA_2: DMA2 */ |
Michael J. Spencer |
2:1df0b61d3b5a | 303 | uint8_t depth; /** FIFO level that triggers a DMA request */ |
Michael J. Spencer |
2:1df0b61d3b5a | 304 | uint8_t Reserved0[2]; |
Michael J. Spencer |
2:1df0b61d3b5a | 305 | }I2S_DMAConf_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 306 | |
Michael J. Spencer |
2:1df0b61d3b5a | 307 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 308 | * @brief I2S mode configuration structure definition |
Michael J. Spencer |
2:1df0b61d3b5a | 309 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 310 | typedef struct{ |
Michael J. Spencer |
2:1df0b61d3b5a | 311 | uint8_t clksel; /** Clock source selection, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 312 | - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output |
Michael J. Spencer |
2:1df0b61d3b5a | 313 | - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */ |
Michael J. Spencer |
2:1df0b61d3b5a | 314 | uint8_t fpin; /** Select four pin mode, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 315 | - I2S_4PIN_ENABLE: 4-pin enable |
Michael J. Spencer |
2:1df0b61d3b5a | 316 | - I2S_4PIN_DISABLE: 4-pin disable */ |
Michael J. Spencer |
2:1df0b61d3b5a | 317 | uint8_t mcena; /** Select MCLK mode, should be: |
Michael J. Spencer |
2:1df0b61d3b5a | 318 | - I2S_MCLK_ENABLE: MCLK enable for output |
Michael J. Spencer |
2:1df0b61d3b5a | 319 | - I2S_MCLK_DISABLE: MCLK disable for output */ |
Michael J. Spencer |
2:1df0b61d3b5a | 320 | uint8_t Reserved; |
Michael J. Spencer |
2:1df0b61d3b5a | 321 | }I2S_MODEConf_Type; |
Michael J. Spencer |
2:1df0b61d3b5a | 322 | |
Michael J. Spencer |
2:1df0b61d3b5a | 323 | |
Michael J. Spencer |
2:1df0b61d3b5a | 324 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 325 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 326 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 327 | |
Michael J. Spencer |
2:1df0b61d3b5a | 328 | |
Michael J. Spencer |
2:1df0b61d3b5a | 329 | /* Public Functions ----------------------------------------------------------- */ |
Michael J. Spencer |
2:1df0b61d3b5a | 330 | /** @defgroup I2S_Public_Functions I2S Public Functions |
Michael J. Spencer |
2:1df0b61d3b5a | 331 | * @{ |
Michael J. Spencer |
2:1df0b61d3b5a | 332 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 333 | /* I2S Init/DeInit functions ---------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 334 | void I2S_Init(LPC_I2S_TypeDef *I2Sx); |
Michael J. Spencer |
2:1df0b61d3b5a | 335 | void I2S_DeInit(LPC_I2S_TypeDef *I2Sx); |
Michael J. Spencer |
2:1df0b61d3b5a | 336 | |
Michael J. Spencer |
2:1df0b61d3b5a | 337 | /* I2S configuration functions --------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 338 | void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct); |
Michael J. Spencer |
2:1df0b61d3b5a | 339 | Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 340 | void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 341 | void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 342 | uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 343 | |
Michael J. Spencer |
2:1df0b61d3b5a | 344 | /* I2S operate functions -------------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 345 | void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData); |
Michael J. Spencer |
2:1df0b61d3b5a | 346 | uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx); |
Michael J. Spencer |
2:1df0b61d3b5a | 347 | void I2S_Start(LPC_I2S_TypeDef *I2Sx); |
Michael J. Spencer |
2:1df0b61d3b5a | 348 | void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 349 | void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 350 | void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 351 | |
Michael J. Spencer |
2:1df0b61d3b5a | 352 | /* I2S DMA functions ----------------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 353 | void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 354 | void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState); |
Michael J. Spencer |
2:1df0b61d3b5a | 355 | |
Michael J. Spencer |
2:1df0b61d3b5a | 356 | /* I2S IRQ functions ----------------*/ |
Michael J. Spencer |
2:1df0b61d3b5a | 357 | void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState); |
Michael J. Spencer |
2:1df0b61d3b5a | 358 | void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level); |
Michael J. Spencer |
2:1df0b61d3b5a | 359 | FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 360 | uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode); |
Michael J. Spencer |
2:1df0b61d3b5a | 361 | |
Michael J. Spencer |
2:1df0b61d3b5a | 362 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 363 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 364 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 365 | |
Michael J. Spencer |
2:1df0b61d3b5a | 366 | |
Michael J. Spencer |
2:1df0b61d3b5a | 367 | #ifdef __cplusplus |
Michael J. Spencer |
2:1df0b61d3b5a | 368 | } |
Michael J. Spencer |
2:1df0b61d3b5a | 369 | #endif |
Michael J. Spencer |
2:1df0b61d3b5a | 370 | |
Michael J. Spencer |
2:1df0b61d3b5a | 371 | |
Michael J. Spencer |
2:1df0b61d3b5a | 372 | #endif /* LPC17XX_SSP_H_ */ |
Michael J. Spencer |
2:1df0b61d3b5a | 373 | |
Michael J. Spencer |
2:1df0b61d3b5a | 374 | /** |
Michael J. Spencer |
2:1df0b61d3b5a | 375 | * @} |
Michael J. Spencer |
2:1df0b61d3b5a | 376 | */ |
Michael J. Spencer |
2:1df0b61d3b5a | 377 | |
Michael J. Spencer |
2:1df0b61d3b5a | 378 | /* --------------------------------- End Of File ------------------------------ */ |