Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/src/lpc17xx_nvic.c@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 #ifdef __LPC17XX__
Michael J. Spencer 2:1df0b61d3b5a 2
Michael J. Spencer 2:1df0b61d3b5a 3 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 4 * $Id$ lpc17xx_nvic.c 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 5 *//**
Michael J. Spencer 2:1df0b61d3b5a 6 * @file lpc17xx_nvic.c
Michael J. Spencer 2:1df0b61d3b5a 7 * @brief Contains all expansion functions support for
Michael J. Spencer 2:1df0b61d3b5a 8 * NVIC firmware library on LPC17xx. The main
Michael J. Spencer 2:1df0b61d3b5a 9 * NVIC functions are defined in core_cm3.h
Michael J. Spencer 2:1df0b61d3b5a 10 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 11 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 12 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 15 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 16 *
Michael J. Spencer 2:1df0b61d3b5a 17 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 18 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 19 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 20 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 21 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 22 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 23 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 24 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 25 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 26 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 27 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 28 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 29
Michael J. Spencer 2:1df0b61d3b5a 30 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 31 /** @addtogroup NVIC
Michael J. Spencer 2:1df0b61d3b5a 32 * @{
Michael J. Spencer 2:1df0b61d3b5a 33 */
Michael J. Spencer 2:1df0b61d3b5a 34
Michael J. Spencer 2:1df0b61d3b5a 35 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 36 #include "lpc17xx_nvic.h"
Michael J. Spencer 2:1df0b61d3b5a 37
Michael J. Spencer 2:1df0b61d3b5a 38
Michael J. Spencer 2:1df0b61d3b5a 39 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 40 /** @addtogroup NVIC_Private_Macros
Michael J. Spencer 2:1df0b61d3b5a 41 * @{
Michael J. Spencer 2:1df0b61d3b5a 42 */
Michael J. Spencer 2:1df0b61d3b5a 43
Michael J. Spencer 2:1df0b61d3b5a 44 /* Vector table offset bit mask */
Michael J. Spencer 2:1df0b61d3b5a 45 #define NVIC_VTOR_MASK 0x3FFFFF80
Michael J. Spencer 2:1df0b61d3b5a 46
Michael J. Spencer 2:1df0b61d3b5a 47 /**
Michael J. Spencer 2:1df0b61d3b5a 48 * @}
Michael J. Spencer 2:1df0b61d3b5a 49 */
Michael J. Spencer 2:1df0b61d3b5a 50
Michael J. Spencer 2:1df0b61d3b5a 51
Michael J. Spencer 2:1df0b61d3b5a 52 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 53 /** @addtogroup NVIC_Public_Functions
Michael J. Spencer 2:1df0b61d3b5a 54 * @{
Michael J. Spencer 2:1df0b61d3b5a 55 */
Michael J. Spencer 2:1df0b61d3b5a 56
Michael J. Spencer 2:1df0b61d3b5a 57
Michael J. Spencer 2:1df0b61d3b5a 58 /*****************************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 59 * @brief De-initializes the NVIC peripheral registers to their default
Michael J. Spencer 2:1df0b61d3b5a 60 * reset values.
Michael J. Spencer 2:1df0b61d3b5a 61 * @param None
Michael J. Spencer 2:1df0b61d3b5a 62 * @return None
Michael J. Spencer 2:1df0b61d3b5a 63 *
Michael J. Spencer 2:1df0b61d3b5a 64 * These following NVIC peripheral registers will be de-initialized:
Michael J. Spencer 2:1df0b61d3b5a 65 * - Disable Interrupt (32 IRQ interrupt sources that matched with LPC17xx)
Michael J. Spencer 2:1df0b61d3b5a 66 * - Clear all Pending Interrupts (32 IRQ interrupt source that matched with LPC17xx)
Michael J. Spencer 2:1df0b61d3b5a 67 * - Clear all Interrupt Priorities (32 IRQ interrupt source that matched with LPC17xx)
Michael J. Spencer 2:1df0b61d3b5a 68 *******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 69 void NVIC_DeInit(void)
Michael J. Spencer 2:1df0b61d3b5a 70 {
Michael J. Spencer 2:1df0b61d3b5a 71 uint8_t tmp;
Michael J. Spencer 2:1df0b61d3b5a 72
Michael J. Spencer 2:1df0b61d3b5a 73 /* Disable all interrupts */
Michael J. Spencer 2:1df0b61d3b5a 74 NVIC->ICER[0] = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 75 NVIC->ICER[1] = 0x00000001;
Michael J. Spencer 2:1df0b61d3b5a 76 /* Clear all pending interrupts */
Michael J. Spencer 2:1df0b61d3b5a 77 NVIC->ICPR[0] = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 78 NVIC->ICPR[1] = 0x00000001;
Michael J. Spencer 2:1df0b61d3b5a 79
Michael J. Spencer 2:1df0b61d3b5a 80 /* Clear all interrupt priority */
Michael J. Spencer 2:1df0b61d3b5a 81 for (tmp = 0; tmp < 32; tmp++) {
Michael J. Spencer 2:1df0b61d3b5a 82 NVIC->IP[tmp] = 0x00;
Michael J. Spencer 2:1df0b61d3b5a 83 }
Michael J. Spencer 2:1df0b61d3b5a 84 }
Michael J. Spencer 2:1df0b61d3b5a 85
Michael J. Spencer 2:1df0b61d3b5a 86 /*****************************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 87 * @brief De-initializes the SCB peripheral registers to their default
Michael J. Spencer 2:1df0b61d3b5a 88 * reset values.
Michael J. Spencer 2:1df0b61d3b5a 89 * @param none
Michael J. Spencer 2:1df0b61d3b5a 90 * @return none
Michael J. Spencer 2:1df0b61d3b5a 91 *
Michael J. Spencer 2:1df0b61d3b5a 92 * These following SCB NVIC peripheral registers will be de-initialized:
Michael J. Spencer 2:1df0b61d3b5a 93 * - Interrupt Control State register
Michael J. Spencer 2:1df0b61d3b5a 94 * - Interrupt Vector Table Offset register
Michael J. Spencer 2:1df0b61d3b5a 95 * - Application Interrupt/Reset Control register
Michael J. Spencer 2:1df0b61d3b5a 96 * - System Control register
Michael J. Spencer 2:1df0b61d3b5a 97 * - Configuration Control register
Michael J. Spencer 2:1df0b61d3b5a 98 * - System Handlers Priority Registers
Michael J. Spencer 2:1df0b61d3b5a 99 * - System Handler Control and State Register
Michael J. Spencer 2:1df0b61d3b5a 100 * - Configurable Fault Status Register
Michael J. Spencer 2:1df0b61d3b5a 101 * - Hard Fault Status Register
Michael J. Spencer 2:1df0b61d3b5a 102 * - Debug Fault Status Register
Michael J. Spencer 2:1df0b61d3b5a 103 *******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 104 void NVIC_SCBDeInit(void)
Michael J. Spencer 2:1df0b61d3b5a 105 {
Michael J. Spencer 2:1df0b61d3b5a 106 uint8_t tmp;
Michael J. Spencer 2:1df0b61d3b5a 107
Michael J. Spencer 2:1df0b61d3b5a 108 SCB->ICSR = 0x0A000000;
Michael J. Spencer 2:1df0b61d3b5a 109 SCB->VTOR = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 110 SCB->AIRCR = 0x05FA0000;
Michael J. Spencer 2:1df0b61d3b5a 111 SCB->SCR = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 112 SCB->CCR = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 113
Michael J. Spencer 2:1df0b61d3b5a 114 for (tmp = 0; tmp < 32; tmp++) {
Michael J. Spencer 2:1df0b61d3b5a 115 SCB->SHP[tmp] = 0x00;
Michael J. Spencer 2:1df0b61d3b5a 116 }
Michael J. Spencer 2:1df0b61d3b5a 117
Michael J. Spencer 2:1df0b61d3b5a 118 SCB->SHCSR = 0x00000000;
Michael J. Spencer 2:1df0b61d3b5a 119 SCB->CFSR = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 120 SCB->HFSR = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 121 SCB->DFSR = 0xFFFFFFFF;
Michael J. Spencer 2:1df0b61d3b5a 122 }
Michael J. Spencer 2:1df0b61d3b5a 123
Michael J. Spencer 2:1df0b61d3b5a 124
Michael J. Spencer 2:1df0b61d3b5a 125 /*****************************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 126 * @brief Set Vector Table Offset value
Michael J. Spencer 2:1df0b61d3b5a 127 * @param offset Offset value
Michael J. Spencer 2:1df0b61d3b5a 128 * @return None
Michael J. Spencer 2:1df0b61d3b5a 129 *******************************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 130 void NVIC_SetVTOR(uint32_t offset)
Michael J. Spencer 2:1df0b61d3b5a 131 {
Michael J. Spencer 2:1df0b61d3b5a 132 // SCB->VTOR = (offset & NVIC_VTOR_MASK);
Michael J. Spencer 2:1df0b61d3b5a 133 SCB->VTOR = offset;
Michael J. Spencer 2:1df0b61d3b5a 134 }
Michael J. Spencer 2:1df0b61d3b5a 135
Michael J. Spencer 2:1df0b61d3b5a 136 /**
Michael J. Spencer 2:1df0b61d3b5a 137 * @}
Michael J. Spencer 2:1df0b61d3b5a 138 */
Michael J. Spencer 2:1df0b61d3b5a 139
Michael J. Spencer 2:1df0b61d3b5a 140 /**
Michael J. Spencer 2:1df0b61d3b5a 141 * @}
Michael J. Spencer 2:1df0b61d3b5a 142 */
Michael J. Spencer 2:1df0b61d3b5a 143
Michael J. Spencer 2:1df0b61d3b5a 144 /* --------------------------------- End Of File ------------------------------ */
Michael J. Spencer 2:1df0b61d3b5a 145 #endif /* __LPC17XX__ */