Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/src/lpc17xx_gpdma.c@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | #ifdef __LPC17XX__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * $Id$ lpc17xx_gpdma.c 2010-03-21 |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * @file lpc17xx_gpdma.c |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @brief Contains all functions support for GPDMA firmware |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @version 2.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * @date 25. July. 2011 |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | /** @addtogroup GPDMA |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | #include "lpc17xx_gpdma.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | #include "lpc17xx_clkpwr.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | /* If this source file built with example, the LPC17xx FW library configuration |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | * file in each example directory ("lpc17xx_libcfg.h") must be included, |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | * otherwise the default FW library configuration file must be included instead |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | #ifdef __BUILD_WITH_EXAMPLE__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | #include "lpc17xx_libcfg.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | #else |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | #include "lpc17xx_libcfg_default.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | #endif /* __BUILD_WITH_EXAMPLE__ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | #ifdef _GPDMA |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | /* Private Variables ---------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | /** @defgroup GPDMA_Private_Variables GPDMA Private Variables |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | * @brief Lookup Table of Connection Type matched with |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | * Peripheral Data (FIFO) register base address |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | #ifdef __IAR_SYSTEMS_ICC__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | volatile const void *GPDMA_LUTPerAddr[] = { |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | (&LPC_SSP0->DR), // SSP0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | (&LPC_SSP0->DR), // SSP0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | (&LPC_SSP1->DR), // SSP1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | (&LPC_SSP1->DR), // SSP1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | (&LPC_ADC->ADGDR), // ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | (&LPC_I2S->I2STXFIFO), // I2S Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | (&LPC_I2S->I2SRXFIFO), // I2S Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | (&LPC_DAC->DACR), // DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | (&LPC_TIM0->MR0), // MAT0.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | (&LPC_TIM0->MR1), // MAT0.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | (&LPC_TIM1->MR0), // MAT1.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | (&LPC_TIM1->MR1), // MAT1.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | (&LPC_TIM2->MR0), // MAT2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | (&LPC_TIM2->MR1), // MAT2.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | (&LPC_TIM3->MR0), // MAT3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | (&LPC_TIM3->MR1) // MAT3.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | #else |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | const uint32_t GPDMA_LUTPerAddr[] = { |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | ((uint32_t)&LPC_ADC->ADGDR), // ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | ((uint32_t)&LPC_DAC->DACR), // DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | ((uint32_t)&LPC_TIM0->MR0), // MAT0.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | ((uint32_t)&LPC_TIM0->MR1), // MAT0.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | ((uint32_t)&LPC_TIM1->MR0), // MAT1.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | ((uint32_t)&LPC_TIM1->MR1), // MAT1.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | ((uint32_t)&LPC_TIM2->MR0), // MAT2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | ((uint32_t)&LPC_TIM2->MR1), // MAT2.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | ((uint32_t)&LPC_TIM3->MR0), // MAT3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | ((uint32_t)&LPC_TIM3->MR1) // MAT3.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | * @brief Lookup Table of GPDMA Channel Number matched with |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | * GPDMA channel pointer |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | const LPC_GPDMACH_TypeDef *pGPDMACh[8] = { |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | LPC_GPDMACH0, // GPDMA Channel 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | LPC_GPDMACH1, // GPDMA Channel 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | LPC_GPDMACH2, // GPDMA Channel 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | LPC_GPDMACH3, // GPDMA Channel 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | LPC_GPDMACH4, // GPDMA Channel 4 |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | LPC_GPDMACH5, // GPDMA Channel 5 |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | LPC_GPDMACH6, // GPDMA Channel 6 |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | LPC_GPDMACH7 // GPDMA Channel 7 |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | * @brief Optimized Peripheral Source and Destination burst size |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | const uint8_t GPDMA_LUTPerBurst[] = { |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | GPDMA_BSIZE_4, // SSP0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | GPDMA_BSIZE_4, // SSP0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | GPDMA_BSIZE_4, // SSP1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | GPDMA_BSIZE_4, // SSP1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | GPDMA_BSIZE_4, // ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | GPDMA_BSIZE_32, // I2S channel 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | GPDMA_BSIZE_32, // I2S channel 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | GPDMA_BSIZE_1, // DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | GPDMA_BSIZE_1, // UART0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | GPDMA_BSIZE_1, // UART0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | GPDMA_BSIZE_1, // UART1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | GPDMA_BSIZE_1, // UART1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | GPDMA_BSIZE_1, // UART2 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | GPDMA_BSIZE_1, // UART2 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | GPDMA_BSIZE_1, // UART3 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | GPDMA_BSIZE_1, // UART3 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | GPDMA_BSIZE_1, // MAT0.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | GPDMA_BSIZE_1, // MAT0.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | GPDMA_BSIZE_1, // MAT1.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | GPDMA_BSIZE_1, // MAT1.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | GPDMA_BSIZE_1, // MAT2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | GPDMA_BSIZE_1, // MAT2.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | GPDMA_BSIZE_1, // MAT3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | GPDMA_BSIZE_1 // MAT3.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | * @brief Optimized Peripheral Source and Destination transfer width |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | const uint8_t GPDMA_LUTPerWid[] = { |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | GPDMA_WIDTH_BYTE, // SSP0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | GPDMA_WIDTH_BYTE, // SSP0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | GPDMA_WIDTH_BYTE, // SSP1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | GPDMA_WIDTH_BYTE, // SSP1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | GPDMA_WIDTH_WORD, // ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | GPDMA_WIDTH_WORD, // I2S channel 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | GPDMA_WIDTH_WORD, // I2S channel 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | GPDMA_WIDTH_BYTE, // DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | GPDMA_WIDTH_BYTE, // UART0 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | GPDMA_WIDTH_BYTE, // UART0 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | GPDMA_WIDTH_BYTE, // UART1 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | GPDMA_WIDTH_BYTE, // UART1 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | GPDMA_WIDTH_BYTE, // UART2 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | GPDMA_WIDTH_BYTE, // UART2 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | GPDMA_WIDTH_BYTE, // UART3 Tx |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | GPDMA_WIDTH_BYTE, // UART3 Rx |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | GPDMA_WIDTH_WORD, // MAT0.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | GPDMA_WIDTH_WORD, // MAT0.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | GPDMA_WIDTH_WORD, // MAT1.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | GPDMA_WIDTH_WORD, // MAT1.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | GPDMA_WIDTH_WORD, // MAT2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | GPDMA_WIDTH_WORD, // MAT2.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | GPDMA_WIDTH_WORD, // MAT3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | GPDMA_WIDTH_WORD // MAT3.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | }; |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | /** @addtogroup GPDMA_Public_Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | * @brief Initialize GPDMA controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | * @param None |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | void GPDMA_Init(void) |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | /* Enable GPDMA clock */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE); |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | // Reset all channel configuration register |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | LPC_GPDMACH0->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | LPC_GPDMACH1->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | LPC_GPDMACH2->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | LPC_GPDMACH3->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | LPC_GPDMACH4->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | LPC_GPDMACH5->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | LPC_GPDMACH6->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | LPC_GPDMACH7->DMACCConfig = 0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | /* Clear all DMA interrupt and error flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | LPC_GPDMA->DMACIntTCClear = 0xFF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | LPC_GPDMA->DMACIntErrClr = 0xFF; |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | * @brief Setup GPDMA channel peripheral according to the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | * parameters in the GPDMAChannelConfig. |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | * structure that contains the configuration |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | * information for the specified GPDMA channel peripheral. |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | * @return ERROR if selected channel is enabled before |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | * or SUCCESS if channel is configured successfully |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig) |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | LPC_GPDMACH_TypeDef *pDMAch; |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | uint32_t tmp1, tmp2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) { |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | // This channel is enabled, return ERROR, need to release this channel first |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | return ERROR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | // Get Channel pointer |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | // Reset the Interrupt status |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum); |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum); |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | // Clear DMA configure |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | pDMAch->DMACCControl = 0x00; |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | pDMAch->DMACCConfig = 0x00; |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | /* Assign Linker List Item value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI; |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | /* Set value to Channel Control Registers */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | switch (GPDMAChannelConfig->TransferType) |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | // Memory to memory |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | case GPDMA_TRANSFERTYPE_M2M: |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | // Assign physical source and destination address |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | pDMAch->DMACCControl |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | | GPDMA_DMACCxControl_SI \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | | GPDMA_DMACCxControl_DI \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | | GPDMA_DMACCxControl_I; |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | // Memory to peripheral |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | case GPDMA_TRANSFERTYPE_M2P: |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | // Assign physical source |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | // Assign peripheral destination address |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | pDMAch->DMACCControl |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | | GPDMA_DMACCxControl_SI \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | | GPDMA_DMACCxControl_I; |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | // Peripheral to memory |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | case GPDMA_TRANSFERTYPE_P2M: |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | // Assign peripheral source address |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | // Assign memory destination address |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr; |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | pDMAch->DMACCControl |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | | GPDMA_DMACCxControl_DI \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | | GPDMA_DMACCxControl_I; |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | // Peripheral to peripheral |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | case GPDMA_TRANSFERTYPE_P2P: |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | // Assign peripheral source address |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | // Assign peripheral destination address |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | pDMAch->DMACCControl |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | | GPDMA_DMACCxControl_I; |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | // Do not support any more transfer type, return ERROR |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | default: |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | return ERROR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | /* Re-Configure DMA Request Select for source peripheral */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | if (GPDMAChannelConfig->SrcConn > 15) |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | } else { |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | /* Re-Configure DMA Request Select for Destination peripheral */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | if (GPDMAChannelConfig->DstConn > 15) |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | } else { |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | /* Enable DMA channels, little endian */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E; |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | // Calculate absolute value for Connection number |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | tmp1 = GPDMAChannelConfig->SrcConn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1); |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | tmp2 = GPDMAChannelConfig->DstConn; |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2); |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | // Configure DMA Channel, enable Error Counter and Terminate counter |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | | GPDMA_DMACCxConfig_DestPeripheral(tmp2); |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | return SUCCESS; |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | * @brief Enable/Disable DMA channel |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | * @param[in] channelNum GPDMA channel, should be in range from 0 to 7 |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | * @param[in] NewState New State of this command, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | * - ENABLE. |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | * - DISABLE. |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState) |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | LPC_GPDMACH_TypeDef *pDMAch; |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | // Get Channel pointer |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | pDMAch = (const LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | if (NewState == ENABLE) { |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E; |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | } else { |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E; |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | * @brief Check if corresponding channel does have an active interrupt |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | * request or not |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | * @param[in] type type of status, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | * - GPDMA_STAT_INT: GPDMA Interrupt Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | * @param[in] channel GPDMA channel, should be in range from 0 to 7 |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | * @return IntStatus status of DMA channel interrupt after masking |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | * Should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | * - SET: the corresponding channel has no active interrupt request |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | * - RESET: the corresponding channel does have an active interrupt request |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel) |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | CHECK_PARAM(PARAM_GPDMA_STAT(type)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | switch (type) |
| Michael J. Spencer |
2:1df0b61d3b5a | 401 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 402 | case GPDMA_STAT_INT: //check status of DMA channel interrupts |
| Michael J. Spencer |
2:1df0b61d3b5a | 403 | if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel))) |
| Michael J. Spencer |
2:1df0b61d3b5a | 404 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 405 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 406 | case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA |
| Michael J. Spencer |
2:1df0b61d3b5a | 407 | if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 408 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 409 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 410 | case GPDMA_STAT_INTERR: //check interrupt status for DMA channels |
| Michael J. Spencer |
2:1df0b61d3b5a | 411 | if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 412 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 413 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 414 | case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels |
| Michael J. Spencer |
2:1df0b61d3b5a | 415 | if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 416 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 417 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 418 | case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels |
| Michael J. Spencer |
2:1df0b61d3b5a | 419 | if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 420 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 421 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 422 | default: //check enable status for DMA channels |
| Michael J. Spencer |
2:1df0b61d3b5a | 423 | if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 424 | return SET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 425 | return RESET; |
| Michael J. Spencer |
2:1df0b61d3b5a | 426 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 427 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 428 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 429 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 430 | * @brief Clear one or more interrupt requests on DMA channels |
| Michael J. Spencer |
2:1df0b61d3b5a | 431 | * @param[in] type type of interrupt request, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 432 | * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear |
| Michael J. Spencer |
2:1df0b61d3b5a | 433 | * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear |
| Michael J. Spencer |
2:1df0b61d3b5a | 434 | * @param[in] channel GPDMA channel, should be in range from 0 to 7 |
| Michael J. Spencer |
2:1df0b61d3b5a | 435 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 436 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 437 | void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel) |
| Michael J. Spencer |
2:1df0b61d3b5a | 438 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 439 | CHECK_PARAM(PARAM_GPDMA_STATCLR(type)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 440 | CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 441 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 442 | if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel |
| Michael J. Spencer |
2:1df0b61d3b5a | 443 | LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel); |
| Michael J. Spencer |
2:1df0b61d3b5a | 444 | else // clear the error interrupt request |
| Michael J. Spencer |
2:1df0b61d3b5a | 445 | LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel); |
| Michael J. Spencer |
2:1df0b61d3b5a | 446 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 447 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 448 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 449 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 450 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 451 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 452 | #endif /* _GPDMA */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 453 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 454 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 455 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 456 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 457 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 458 | /* --------------------------------- End Of File ------------------------------ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 459 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 460 | #endif /* __LPC17XX__ */ |