Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/src/lpc17xx_clkpwr.c@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | #ifdef __LPC17XX__ |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * $Id$ lpc17xx_clkpwr.c 2010-06-18 |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * @file lpc17xx_clkpwr.c |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @brief Contains all functions support for Clock and Power Control |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @version 3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * @date 18. June. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | /** @addtogroup CLKPWR |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | #include "lpc17xx_clkpwr.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | /** @addtogroup CLKPWR_Public_Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | * @brief Set value of each Peripheral Clock Selection |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | * @param[in] ClkType Peripheral Clock Selection of each type, |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | * should be one of the following: |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | * - CLKPWR_PCLKSEL_WDT : WDT |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | - CLKPWR_PCLKSEL_TIMER0 : Timer 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | - CLKPWR_PCLKSEL_TIMER1 : Timer 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | - CLKPWR_PCLKSEL_UART0 : UART 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | - CLKPWR_PCLKSEL_UART1 : UART 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | - CLKPWR_PCLKSEL_PWM1 : PWM 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | - CLKPWR_PCLKSEL_I2C0 : I2C 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | - CLKPWR_PCLKSEL_SPI : SPI |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | - CLKPWR_PCLKSEL_SSP1 : SSP 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | - CLKPWR_PCLKSEL_DAC : DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | - CLKPWR_PCLKSEL_ADC : ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | - CLKPWR_PCLKSEL_CAN1 : CAN 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | - CLKPWR_PCLKSEL_CAN2 : CAN 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | - CLKPWR_PCLKSEL_ACF : ACF |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | - CLKPWR_PCLKSEL_QEI : QEI |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | - CLKPWR_PCLKSEL_PCB : PCB |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | - CLKPWR_PCLKSEL_I2C1 : I2C 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | - CLKPWR_PCLKSEL_SSP0 : SSP 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | - CLKPWR_PCLKSEL_TIMER2 : Timer 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | - CLKPWR_PCLKSEL_TIMER3 : Timer 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | - CLKPWR_PCLKSEL_UART2 : UART 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | - CLKPWR_PCLKSEL_UART3 : UART 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | - CLKPWR_PCLKSEL_I2C2 : I2C 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | - CLKPWR_PCLKSEL_I2S : I2S |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | - CLKPWR_PCLKSEL_RIT : RIT |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | - CLKPWR_PCLKSEL_SYSCON : SYSCON |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | - CLKPWR_PCLKSEL_MC : MC |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | * @param[in] DivVal Value of divider, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4 |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | * @return none |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal) |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | uint32_t bitpos; |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32); |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | /* PCLKSEL0 selected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | if (ClkType < 32) |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | /* Clear two bit at bit position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos))); |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | /* Set two selected bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | /* PCLKSEL1 selected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | else |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | /* Clear two bit at bit position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | /* Set two selected bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal)); |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | * @brief Get current value of each Peripheral Clock Selection |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | * @param[in] ClkType Peripheral Clock Selection of each type, |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | * should be one of the following: |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | * - CLKPWR_PCLKSEL_WDT : WDT |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | - CLKPWR_PCLKSEL_TIMER0 : Timer 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | - CLKPWR_PCLKSEL_TIMER1 : Timer 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | - CLKPWR_PCLKSEL_UART0 : UART 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | - CLKPWR_PCLKSEL_UART1 : UART 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | - CLKPWR_PCLKSEL_PWM1 : PWM 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | - CLKPWR_PCLKSEL_I2C0 : I2C 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | - CLKPWR_PCLKSEL_SPI : SPI |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | - CLKPWR_PCLKSEL_SSP1 : SSP 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | - CLKPWR_PCLKSEL_DAC : DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | - CLKPWR_PCLKSEL_ADC : ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | - CLKPWR_PCLKSEL_CAN1 : CAN 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | - CLKPWR_PCLKSEL_CAN2 : CAN 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | - CLKPWR_PCLKSEL_ACF : ACF |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | - CLKPWR_PCLKSEL_QEI : QEI |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | - CLKPWR_PCLKSEL_PCB : PCB |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | - CLKPWR_PCLKSEL_I2C1 : I2C 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | - CLKPWR_PCLKSEL_SSP0 : SSP 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | - CLKPWR_PCLKSEL_TIMER2 : Timer 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | - CLKPWR_PCLKSEL_TIMER3 : Timer 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | - CLKPWR_PCLKSEL_UART2 : UART 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | - CLKPWR_PCLKSEL_UART3 : UART 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | - CLKPWR_PCLKSEL_I2C2 : I2C 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | - CLKPWR_PCLKSEL_I2S : I2S |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | - CLKPWR_PCLKSEL_RIT : RIT |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | - CLKPWR_PCLKSEL_SYSCON : SYSCON |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | - CLKPWR_PCLKSEL_MC : MC |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | * @return Value of Selected Peripheral Clock Selection |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType) |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | uint32_t bitpos, retval; |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | if (ClkType < 32) |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | bitpos = ClkType; |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | retval = LPC_SC->PCLKSEL0; |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | else |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | bitpos = ClkType - 32; |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | retval = LPC_SC->PCLKSEL1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | retval = CLKPWR_PCLKSEL_GET(bitpos, retval); |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | return retval; |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | * @brief Get current value of each Peripheral Clock |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | * @param[in] ClkType Peripheral Clock Selection of each type, |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | * should be one of the following: |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | * - CLKPWR_PCLKSEL_WDT : WDT |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | - CLKPWR_PCLKSEL_TIMER0 : Timer 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | - CLKPWR_PCLKSEL_TIMER1 : Timer 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | - CLKPWR_PCLKSEL_UART0 : UART 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | - CLKPWR_PCLKSEL_UART1 : UART 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | - CLKPWR_PCLKSEL_PWM1 : PWM 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | - CLKPWR_PCLKSEL_I2C0 : I2C 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | - CLKPWR_PCLKSEL_SPI : SPI |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | - CLKPWR_PCLKSEL_SSP1 : SSP 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | - CLKPWR_PCLKSEL_DAC : DAC |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | - CLKPWR_PCLKSEL_ADC : ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | - CLKPWR_PCLKSEL_CAN1 : CAN 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | - CLKPWR_PCLKSEL_CAN2 : CAN 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | - CLKPWR_PCLKSEL_ACF : ACF |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | - CLKPWR_PCLKSEL_QEI : QEI |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | - CLKPWR_PCLKSEL_PCB : PCB |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | - CLKPWR_PCLKSEL_I2C1 : I2C 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | - CLKPWR_PCLKSEL_SSP0 : SSP 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | - CLKPWR_PCLKSEL_TIMER2 : Timer 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | - CLKPWR_PCLKSEL_TIMER3 : Timer 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | - CLKPWR_PCLKSEL_UART2 : UART 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | - CLKPWR_PCLKSEL_UART3 : UART 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | - CLKPWR_PCLKSEL_I2C2 : I2C 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | - CLKPWR_PCLKSEL_I2S : I2S |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | - CLKPWR_PCLKSEL_RIT : RIT |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | - CLKPWR_PCLKSEL_SYSCON : SYSCON |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | - CLKPWR_PCLKSEL_MC : MC |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | * @return Value of Selected Peripheral Clock |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | uint32_t CLKPWR_GetPCLK (uint32_t ClkType) |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | uint32_t retval, div; |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | retval = SystemCoreClock; |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | div = CLKPWR_GetPCLKSEL(ClkType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | switch (div) |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | case 0: |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | div = 4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | case 1: |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | div = 1; |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | case 2: |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | div = 2; |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | case 3: |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | div = 8; |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | break; |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | retval /= div; |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | return retval; |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | * @brief Configure power supply for each peripheral according to NewState |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | * @param[in] PPType Type of peripheral used to enable power, |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | * should be one of the following: |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | * - CLKPWR_PCONP_PCTIM0 : Timer 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | - CLKPWR_PCONP_PCTIM1 : Timer 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | - CLKPWR_PCONP_PCUART0 : UART 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | - CLKPWR_PCONP_PCUART1 : UART 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | - CLKPWR_PCONP_PCPWM1 : PWM 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | - CLKPWR_PCONP_PCI2C0 : I2C 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | - CLKPWR_PCONP_PCSPI : SPI |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | - CLKPWR_PCONP_PCRTC : RTC |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | - CLKPWR_PCONP_PCSSP1 : SSP 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | - CLKPWR_PCONP_PCAD : ADC |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | - CLKPWR_PCONP_PCAN1 : CAN 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | - CLKPWR_PCONP_PCAN2 : CAN 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | - CLKPWR_PCONP_PCGPIO : GPIO |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | - CLKPWR_PCONP_PCRIT : RIT |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | - CLKPWR_PCONP_PCMC : MC |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | - CLKPWR_PCONP_PCQEI : QEI |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | - CLKPWR_PCONP_PCI2C1 : I2C 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | - CLKPWR_PCONP_PCSSP0 : SSP 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | - CLKPWR_PCONP_PCTIM2 : Timer 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | - CLKPWR_PCONP_PCTIM3 : Timer 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | - CLKPWR_PCONP_PCUART2 : UART 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | - CLKPWR_PCONP_PCUART3 : UART 3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | - CLKPWR_PCONP_PCI2C2 : I2C 2 |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | - CLKPWR_PCONP_PCI2S : I2S |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | - CLKPWR_PCONP_PCGPDMA : GPDMA |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | - CLKPWR_PCONP_PCENET : Ethernet |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | - CLKPWR_PCONP_PCUSB : USB |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | * @param[in] NewState New state of Peripheral Power, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | * - ENABLE : Enable power for this peripheral |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | * - DISABLE : Disable power for this peripheral |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | * @return none |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState) |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | if (NewState == ENABLE) |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK; |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | else if (NewState == DISABLE) |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK; |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3. |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | * @param[in] None |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | void CLKPWR_Sleep(void) |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | LPC_SC->PCON = 0x00; |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | /* Sleep Mode*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | __WFI(); |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3. |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | * @param[in] None |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | void CLKPWR_DeepSleep(void) |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | /* Deep-Sleep Mode, set SLEEPDEEP bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | SCB->SCR = 0x4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | LPC_SC->PCON = 0x8; |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | /* Deep Sleep Mode*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | __WFI(); |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3. |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | * @param[in] None |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | void CLKPWR_PowerDown(void) |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | /* Deep-Sleep Mode, set SLEEPDEEP bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | SCB->SCR = 0x4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | LPC_SC->PCON = 0x09; |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | /* Power Down Mode*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | __WFI(); |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3. |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | * @param[in] None |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | * @return None |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | void CLKPWR_DeepPowerDown(void) |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | /* Deep-Sleep Mode, set SLEEPDEEP bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | SCB->SCR = 0x4; |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | LPC_SC->PCON = 0x03; |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | /* Deep Power Down Mode*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | __WFI(); |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | /* --------------------------------- End Of File ------------------------------ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | #endif /* __LPC17XX__ */ |