Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_uart.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_uart.h 2010-06-18 |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_uart.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for UART firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 18. June. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup UART UART (Universal Asynchronous Receiver/Transmitter) |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef __LPC17XX_UART_H |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define __LPC17XX_UART_H |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | /* Public Macros -------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | /** @defgroup UART_Public_Macros UART Public Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | /** UART time-out definitions in case of using Read() and Write function |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | * with Blocking Flag mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | #define UART_BLOCKING_TIMEOUT (0xFFFFFFFFUL) |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | /* Private Macros ------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | /** @defgroup UART_Private_Macros UART Private Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | /* Accepted Error baud rate value (in percent unit) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define UART_ACCEPTED_BAUDRATE_ERROR (3) /*!< Acceptable UART baudrate error */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | * Macro defines for Macro defines for UARTn Receiver Buffer Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | #define UART_RBR_MASKBIT ((uint8_t)0xFF) /*!< UART Received Buffer mask bit (8 bits) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | * Macro defines for Macro defines for UARTn Transmit Holding Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define UART_THR_MASKBIT ((uint8_t)0xFF) /*!< UART Transmit Holding mask bit (8 bits) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | * Macro defines for Macro defines for UARTn Divisor Latch LSB register |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | #define UART_LOAD_DLL(div) ((div) & 0xFF) /**< Macro for loading least significant halfs of divisors */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | #define UART_DLL_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch LSB bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | * Macro defines for Macro defines for UARTn Divisor Latch MSB register |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | #define UART_DLM_MASKBIT ((uint8_t)0xFF) /*!< Divisor latch MSB bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) /**< Macro for loading most significant halfs of divisors */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | * Macro defines for Macro defines for UART interrupt enable register |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | #define UART_IER_RBRINT_EN ((uint32_t)(1<<0)) /*!< RBR Interrupt enable*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | #define UART_IER_THREINT_EN ((uint32_t)(1<<1)) /*!< THR Interrupt enable*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | #define UART_IER_RLSINT_EN ((uint32_t)(1<<2)) /*!< RX line status interrupt enable*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | #define UART1_IER_MSINT_EN ((uint32_t)(1<<3)) /*!< Modem status interrupt enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | #define UART1_IER_CTSINT_EN ((uint32_t)(1<<7)) /*!< CTS1 signal transition interrupt enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | #define UART_IER_ABEOINT_EN ((uint32_t)(1<<8)) /*!< Enables the end of auto-baud interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | #define UART_IER_ABTOINT_EN ((uint32_t)(1<<9)) /*!< Enables the auto-baud time-out interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define UART_IER_BITMASK ((uint32_t)(0x307)) /*!< UART interrupt enable register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | #define UART1_IER_BITMASK ((uint32_t)(0x38F)) /*!< UART1 interrupt enable register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | * Macro defines for Macro defines for UART interrupt identification register |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | #define UART_IIR_INTSTAT_PEND ((uint32_t)(1<<0)) /*!<Interrupt Status - Active low */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | #define UART_IIR_INTID_RLS ((uint32_t)(3<<1)) /*!<Interrupt identification: Receive line status*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | #define UART_IIR_INTID_RDA ((uint32_t)(2<<1)) /*!<Interrupt identification: Receive data available*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | #define UART_IIR_INTID_CTI ((uint32_t)(6<<1)) /*!<Interrupt identification: Character time-out indicator*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | #define UART_IIR_INTID_THRE ((uint32_t)(1<<1)) /*!<Interrupt identification: THRE interrupt*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | #define UART1_IIR_INTID_MODEM ((uint32_t)(0<<1)) /*!<Interrupt identification: Modem interrupt*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | #define UART_IIR_INTID_MASK ((uint32_t)(7<<1)) /*!<Interrupt identification: Interrupt ID mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | #define UART_IIR_FIFO_EN ((uint32_t)(3<<6)) /*!<These bits are equivalent to UnFCR[0] */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | #define UART_IIR_ABEO_INT ((uint32_t)(1<<8)) /*!< End of auto-baud interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | #define UART_IIR_ABTO_INT ((uint32_t)(1<<9)) /*!< Auto-baud time-out interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | #define UART_IIR_BITMASK ((uint32_t)(0x3CF)) /*!< UART interrupt identification register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | * Macro defines for Macro defines for UART FIFO control register |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | #define UART_FCR_FIFO_EN ((uint8_t)(1<<0)) /*!< UART FIFO enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | #define UART_FCR_RX_RS ((uint8_t)(1<<1)) /*!< UART FIFO RX reset */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | #define UART_FCR_TX_RS ((uint8_t)(1<<2)) /*!< UART FIFO TX reset */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | #define UART_FCR_DMAMODE_SEL ((uint8_t)(1<<3)) /*!< UART DMA mode selection */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | #define UART_FCR_TRG_LEV0 ((uint8_t)(0)) /*!< UART FIFO trigger level 0: 1 character */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | #define UART_FCR_TRG_LEV1 ((uint8_t)(1<<6)) /*!< UART FIFO trigger level 1: 4 character */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | #define UART_FCR_TRG_LEV2 ((uint8_t)(2<<6)) /*!< UART FIFO trigger level 2: 8 character */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | #define UART_FCR_TRG_LEV3 ((uint8_t)(3<<6)) /*!< UART FIFO trigger level 3: 14 character */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | #define UART_FCR_BITMASK ((uint8_t)(0xCF)) /*!< UART FIFO control bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | #define UART_TX_FIFO_SIZE (16) |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | * Macro defines for Macro defines for UART line control register |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | #define UART_LCR_WLEN5 ((uint8_t)(0)) /*!< UART 5 bit data mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | #define UART_LCR_WLEN6 ((uint8_t)(1<<0)) /*!< UART 6 bit data mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | #define UART_LCR_WLEN7 ((uint8_t)(2<<0)) /*!< UART 7 bit data mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | #define UART_LCR_WLEN8 ((uint8_t)(3<<0)) /*!< UART 8 bit data mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | #define UART_LCR_STOPBIT_SEL ((uint8_t)(1<<2)) /*!< UART Two Stop Bits Select */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | #define UART_LCR_PARITY_EN ((uint8_t)(1<<3)) /*!< UART Parity Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | #define UART_LCR_PARITY_ODD ((uint8_t)(0)) /*!< UART Odd Parity Select */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | #define UART_LCR_PARITY_EVEN ((uint8_t)(1<<4)) /*!< UART Even Parity Select */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | #define UART_LCR_PARITY_F_1 ((uint8_t)(2<<4)) /*!< UART force 1 stick parity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | #define UART_LCR_PARITY_F_0 ((uint8_t)(3<<4)) /*!< UART force 0 stick parity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | #define UART_LCR_BREAK_EN ((uint8_t)(1<<6)) /*!< UART Transmission Break enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | #define UART_LCR_DLAB_EN ((uint8_t)(1<<7)) /*!< UART Divisor Latches Access bit enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | #define UART_LCR_BITMASK ((uint8_t)(0xFF)) /*!< UART line control bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | * Macro defines for Macro defines for UART1 Modem Control Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | #define UART1_MCR_DTR_CTRL ((uint8_t)(1<<0)) /*!< Source for modem output pin DTR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | #define UART1_MCR_RTS_CTRL ((uint8_t)(1<<1)) /*!< Source for modem output pin RTS */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define UART1_MCR_LOOPB_EN ((uint8_t)(1<<4)) /*!< Loop back mode select */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | #define UART1_MCR_AUTO_RTS_EN ((uint8_t)(1<<6)) /*!< Enable Auto RTS flow-control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define UART1_MCR_AUTO_CTS_EN ((uint8_t)(1<<7)) /*!< Enable Auto CTS flow-control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | #define UART1_MCR_BITMASK ((uint8_t)(0x0F3)) /*!< UART1 bit mask value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | * Macro defines for Macro defines for UART line status register |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | #define UART_LSR_RDR ((uint8_t)(1<<0)) /*!<Line status register: Receive data ready*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | #define UART_LSR_OE ((uint8_t)(1<<1)) /*!<Line status register: Overrun error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | #define UART_LSR_PE ((uint8_t)(1<<2)) /*!<Line status register: Parity error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | #define UART_LSR_FE ((uint8_t)(1<<3)) /*!<Line status register: Framing error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | #define UART_LSR_BI ((uint8_t)(1<<4)) /*!<Line status register: Break interrupt*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | #define UART_LSR_THRE ((uint8_t)(1<<5)) /*!<Line status register: Transmit holding register empty*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | #define UART_LSR_TEMT ((uint8_t)(1<<6)) /*!<Line status register: Transmitter empty*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | #define UART_LSR_RXFE ((uint8_t)(1<<7)) /*!<Error in RX FIFO*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define UART_LSR_BITMASK ((uint8_t)(0xFF)) /*!<UART Line status bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | * Macro defines for Macro defines for UART Modem (UART1 only) status register |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | #define UART1_MSR_DELTA_CTS ((uint8_t)(1<<0)) /*!< Set upon state change of input CTS */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | #define UART1_MSR_DELTA_DSR ((uint8_t)(1<<1)) /*!< Set upon state change of input DSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | #define UART1_MSR_LO2HI_RI ((uint8_t)(1<<2)) /*!< Set upon low to high transition of input RI */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | #define UART1_MSR_DELTA_DCD ((uint8_t)(1<<3)) /*!< Set upon state change of input DCD */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | #define UART1_MSR_CTS ((uint8_t)(1<<4)) /*!< Clear To Send State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | #define UART1_MSR_DSR ((uint8_t)(1<<5)) /*!< Data Set Ready State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | #define UART1_MSR_RI ((uint8_t)(1<<6)) /*!< Ring Indicator State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | #define UART1_MSR_DCD ((uint8_t)(1<<7)) /*!< Data Carrier Detect State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | #define UART1_MSR_BITMASK ((uint8_t)(0xFF)) /*!< MSR register bit-mask value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | * Macro defines for Macro defines for UART Scratch Pad Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | #define UART_SCR_BIMASK ((uint8_t)(0xFF)) /*!< UART Scratch Pad bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | |
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2:1df0b61d3b5a | 192 | /*********************************************************************//** |
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2:1df0b61d3b5a | 193 | * Macro defines for Macro defines for UART Auto baudrate control register |
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2:1df0b61d3b5a | 194 | **********************************************************************/ |
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2:1df0b61d3b5a | 195 | #define UART_ACR_START ((uint32_t)(1<<0)) /**< UART Auto-baud start */ |
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2:1df0b61d3b5a | 196 | #define UART_ACR_MODE ((uint32_t)(1<<1)) /**< UART Auto baudrate Mode 1 */ |
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2:1df0b61d3b5a | 197 | #define UART_ACR_AUTO_RESTART ((uint32_t)(1<<2)) /**< UART Auto baudrate restart */ |
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2:1df0b61d3b5a | 198 | #define UART_ACR_ABEOINT_CLR ((uint32_t)(1<<8)) /**< UART End of auto-baud interrupt clear */ |
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2:1df0b61d3b5a | 199 | #define UART_ACR_ABTOINT_CLR ((uint32_t)(1<<9)) /**< UART Auto-baud time-out interrupt clear */ |
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2:1df0b61d3b5a | 200 | #define UART_ACR_BITMASK ((uint32_t)(0x307)) /**< UART Auto Baudrate register bit mask */ |
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2:1df0b61d3b5a | 201 | |
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2:1df0b61d3b5a | 202 | /*********************************************************************//** |
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2:1df0b61d3b5a | 203 | * Macro defines for Macro defines for UART IrDA control register |
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2:1df0b61d3b5a | 204 | **********************************************************************/ |
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2:1df0b61d3b5a | 205 | #define UART_ICR_IRDAEN ((uint32_t)(1<<0)) /**< IrDA mode enable */ |
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2:1df0b61d3b5a | 206 | #define UART_ICR_IRDAINV ((uint32_t)(1<<1)) /**< IrDA serial input inverted */ |
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2:1df0b61d3b5a | 207 | #define UART_ICR_FIXPULSE_EN ((uint32_t)(1<<2)) /**< IrDA fixed pulse width mode */ |
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2:1df0b61d3b5a | 208 | #define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) /**< PulseDiv - Configures the pulse when FixPulseEn = 1 */ |
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2:1df0b61d3b5a | 209 | #define UART_ICR_BITMASK ((uint32_t)(0x3F)) /*!< UART IRDA bit mask */ |
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2:1df0b61d3b5a | 210 | |
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2:1df0b61d3b5a | 211 | /*********************************************************************//** |
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2:1df0b61d3b5a | 212 | * Macro defines for Macro defines for UART Fractional divider register |
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2:1df0b61d3b5a | 213 | **********************************************************************/ |
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2:1df0b61d3b5a | 214 | #define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) /**< Baud-rate generation pre-scaler divisor */ |
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2:1df0b61d3b5a | 215 | #define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) /**< Baud-rate pre-scaler multiplier value */ |
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2:1df0b61d3b5a | 216 | #define UART_FDR_BITMASK ((uint32_t)(0xFF)) /**< UART Fractional Divider register bit mask */ |
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2:1df0b61d3b5a | 217 | |
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2:1df0b61d3b5a | 218 | /*********************************************************************//** |
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2:1df0b61d3b5a | 219 | * Macro defines for Macro defines for UART Tx Enable register |
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2:1df0b61d3b5a | 220 | **********************************************************************/ |
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2:1df0b61d3b5a | 221 | #define UART_TER_TXEN ((uint8_t)(1<<7)) /*!< Transmit enable bit */ |
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2:1df0b61d3b5a | 222 | #define UART_TER_BITMASK ((uint8_t)(0x80)) /**< UART Transmit Enable Register bit mask */ |
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2:1df0b61d3b5a | 223 | |
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2:1df0b61d3b5a | 224 | /*********************************************************************//** |
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2:1df0b61d3b5a | 225 | * Macro defines for Macro defines for UART1 RS485 Control register |
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2:1df0b61d3b5a | 226 | **********************************************************************/ |
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2:1df0b61d3b5a | 227 | #define UART1_RS485CTRL_NMM_EN ((uint32_t)(1<<0)) /*!< RS-485/EIA-485 Normal Multi-drop Mode (NMM) |
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2:1df0b61d3b5a | 228 | is disabled */ |
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2:1df0b61d3b5a | 229 | #define UART1_RS485CTRL_RX_DIS ((uint32_t)(1<<1)) /*!< The receiver is disabled */ |
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2:1df0b61d3b5a | 230 | #define UART1_RS485CTRL_AADEN ((uint32_t)(1<<2)) /*!< Auto Address Detect (AAD) is enabled */ |
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2:1df0b61d3b5a | 231 | #define UART1_RS485CTRL_SEL_DTR ((uint32_t)(1<<3)) /*!< If direction control is enabled |
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2:1df0b61d3b5a | 232 | (bit DCTRL = 1), pin DTR is used for direction control */ |
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2:1df0b61d3b5a | 233 | #define UART1_RS485CTRL_DCTRL_EN ((uint32_t)(1<<4)) /*!< Enable Auto Direction Control */ |
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2:1df0b61d3b5a | 234 | #define UART1_RS485CTRL_OINV_1 ((uint32_t)(1<<5)) /*!< This bit reverses the polarity of the direction |
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2:1df0b61d3b5a | 235 | control signal on the RTS (or DTR) pin. The direction control pin |
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2:1df0b61d3b5a | 236 | will be driven to logic "1" when the transmitter has data to be sent */ |
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2:1df0b61d3b5a | 237 | #define UART1_RS485CTRL_BITMASK ((uint32_t)(0x3F)) /**< RS485 control bit-mask value */ |
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2:1df0b61d3b5a | 238 | |
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2:1df0b61d3b5a | 239 | /*********************************************************************//** |
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2:1df0b61d3b5a | 240 | * Macro defines for Macro defines for UART1 RS-485 Address Match register |
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2:1df0b61d3b5a | 241 | **********************************************************************/ |
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2:1df0b61d3b5a | 242 | #define UART1_RS485ADRMATCH_BITMASK ((uint8_t)(0xFF)) /**< Bit mask value */ |
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2:1df0b61d3b5a | 243 | |
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2:1df0b61d3b5a | 244 | /*********************************************************************//** |
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2:1df0b61d3b5a | 245 | * Macro defines for Macro defines for UART1 RS-485 Delay value register |
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2:1df0b61d3b5a | 246 | **********************************************************************/ |
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2:1df0b61d3b5a | 247 | /* Macro defines for UART1 RS-485 Delay value register */ |
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2:1df0b61d3b5a | 248 | #define UART1_RS485DLY_BITMASK ((uint8_t)(0xFF)) /** Bit mask value */ |
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2:1df0b61d3b5a | 249 | |
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2:1df0b61d3b5a | 250 | /*********************************************************************//** |
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2:1df0b61d3b5a | 251 | * Macro defines for Macro defines for UART FIFO Level register |
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2:1df0b61d3b5a | 252 | **********************************************************************/ |
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2:1df0b61d3b5a | 253 | #define UART_FIFOLVL_RXFIFOLVL(n) ((uint32_t)(n&0x0F)) /**< Reflects the current level of the UART receiver FIFO */ |
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2:1df0b61d3b5a | 254 | #define UART_FIFOLVL_TXFIFOLVL(n) ((uint32_t)((n>>8)&0x0F)) /**< Reflects the current level of the UART transmitter FIFO */ |
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2:1df0b61d3b5a | 255 | #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) /**< UART FIFO Level Register bit mask */ |
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2:1df0b61d3b5a | 256 | |
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2:1df0b61d3b5a | 257 | |
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2:1df0b61d3b5a | 258 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
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2:1df0b61d3b5a | 259 | |
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2:1df0b61d3b5a | 260 | /** Macro to check the input UART_DATABIT parameters */ |
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2:1df0b61d3b5a | 261 | #define PARAM_UART_DATABIT(databit) ((databit==UART_DATABIT_5) || (databit==UART_DATABIT_6)\ |
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2:1df0b61d3b5a | 262 | || (databit==UART_DATABIT_7) || (databit==UART_DATABIT_8)) |
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2:1df0b61d3b5a | 263 | |
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2:1df0b61d3b5a | 264 | /** Macro to check the input UART_STOPBIT parameters */ |
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2:1df0b61d3b5a | 265 | #define PARAM_UART_STOPBIT(stopbit) ((stopbit==UART_STOPBIT_1) || (stopbit==UART_STOPBIT_2)) |
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2:1df0b61d3b5a | 266 | |
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2:1df0b61d3b5a | 267 | /** Macro to check the input UART_PARITY parameters */ |
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2:1df0b61d3b5a | 268 | #define PARAM_UART_PARITY(parity) ((parity==UART_PARITY_NONE) || (parity==UART_PARITY_ODD) \ |
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2:1df0b61d3b5a | 269 | || (parity==UART_PARITY_EVEN) || (parity==UART_PARITY_SP_1) \ |
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2:1df0b61d3b5a | 270 | || (parity==UART_PARITY_SP_0)) |
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2:1df0b61d3b5a | 271 | |
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2:1df0b61d3b5a | 272 | /** Macro to check the input UART_FIFO parameters */ |
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2:1df0b61d3b5a | 273 | #define PARAM_UART_FIFO_LEVEL(fifo) ((fifo==UART_FIFO_TRGLEV0) \ |
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2:1df0b61d3b5a | 274 | || (fifo==UART_FIFO_TRGLEV1) || (fifo==UART_FIFO_TRGLEV2) \ |
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2:1df0b61d3b5a | 275 | || (fifo==UART_FIFO_TRGLEV3)) |
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2:1df0b61d3b5a | 276 | |
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2:1df0b61d3b5a | 277 | /** Macro to check the input UART_INTCFG parameters */ |
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2:1df0b61d3b5a | 278 | #define PARAM_UART_INTCFG(IntCfg) ((IntCfg==UART_INTCFG_RBR) || (IntCfg==UART_INTCFG_THRE) \ |
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2:1df0b61d3b5a | 279 | || (IntCfg==UART_INTCFG_RLS) || (IntCfg==UART_INTCFG_ABEO) \ |
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2:1df0b61d3b5a | 280 | || (IntCfg==UART_INTCFG_ABTO)) |
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2:1df0b61d3b5a | 281 | |
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2:1df0b61d3b5a | 282 | /** Macro to check the input UART1_INTCFG parameters - expansion input parameter for UART1 */ |
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2:1df0b61d3b5a | 283 | #define PARAM_UART1_INTCFG(IntCfg) ((IntCfg==UART1_INTCFG_MS) || (IntCfg==UART1_INTCFG_CTS)) |
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2:1df0b61d3b5a | 284 | |
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2:1df0b61d3b5a | 285 | /** Macro to check the input UART_AUTOBAUD_MODE parameters */ |
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2:1df0b61d3b5a | 286 | #define PARAM_UART_AUTOBAUD_MODE(ABmode) ((ABmode==UART_AUTOBAUD_MODE0) || (ABmode==UART_AUTOBAUD_MODE1)) |
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2:1df0b61d3b5a | 287 | |
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2:1df0b61d3b5a | 288 | /** Macro to check the input UART_AUTOBAUD_INTSTAT parameters */ |
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2:1df0b61d3b5a | 289 | #define PARAM_UART_AUTOBAUD_INTSTAT(ABIntStat) ((ABIntStat==UART_AUTOBAUD_INTSTAT_ABEO) || \ |
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2:1df0b61d3b5a | 290 | (ABIntStat==UART_AUTOBAUD_INTSTAT_ABTO)) |
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2:1df0b61d3b5a | 291 | |
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2:1df0b61d3b5a | 292 | /** Macro to check the input UART_IrDA_PULSEDIV parameters */ |
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2:1df0b61d3b5a | 293 | #define PARAM_UART_IrDA_PULSEDIV(PulseDiv) ((PulseDiv==UART_IrDA_PULSEDIV2) || (PulseDiv==UART_IrDA_PULSEDIV4) \ |
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2:1df0b61d3b5a | 294 | || (PulseDiv==UART_IrDA_PULSEDIV8) || (PulseDiv==UART_IrDA_PULSEDIV16) \ |
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2:1df0b61d3b5a | 295 | || (PulseDiv==UART_IrDA_PULSEDIV32) || (PulseDiv==UART_IrDA_PULSEDIV64) \ |
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2:1df0b61d3b5a | 296 | || (PulseDiv==UART_IrDA_PULSEDIV128) || (PulseDiv==UART_IrDA_PULSEDIV256)) |
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2:1df0b61d3b5a | 297 | |
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2:1df0b61d3b5a | 298 | /* Macro to check the input UART1_SignalState parameters */ |
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2:1df0b61d3b5a | 299 | #define PARAM_UART1_SIGNALSTATE(x) ((x==INACTIVE) || (x==ACTIVE)) |
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2:1df0b61d3b5a | 300 | |
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2:1df0b61d3b5a | 301 | /** Macro to check the input PARAM_UART1_MODEM_PIN parameters */ |
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2:1df0b61d3b5a | 302 | #define PARAM_UART1_MODEM_PIN(x) ((x==UART1_MODEM_PIN_DTR) || (x==UART1_MODEM_PIN_RTS)) |
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2:1df0b61d3b5a | 303 | |
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2:1df0b61d3b5a | 304 | /** Macro to check the input PARAM_UART1_MODEM_MODE parameters */ |
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2:1df0b61d3b5a | 305 | #define PARAM_UART1_MODEM_MODE(x) ((x==UART1_MODEM_MODE_LOOPBACK) || (x==UART1_MODEM_MODE_AUTO_RTS) \ |
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2:1df0b61d3b5a | 306 | || (x==UART1_MODEM_MODE_AUTO_CTS)) |
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2:1df0b61d3b5a | 307 | |
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2:1df0b61d3b5a | 308 | /** Macro to check the direction control pin type */ |
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2:1df0b61d3b5a | 309 | #define PARAM_UART_RS485_DIRCTRL_PIN(x) ((x==UART1_RS485_DIRCTRL_RTS) || (x==UART1_RS485_DIRCTRL_DTR)) |
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2:1df0b61d3b5a | 310 | |
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2:1df0b61d3b5a | 311 | /* Macro to determine if it is valid UART port number */ |
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2:1df0b61d3b5a | 312 | #define PARAM_UARTx(x) ((((uint32_t *)x)==((uint32_t *)LPC_UART0)) \ |
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2:1df0b61d3b5a | 313 | || (((uint32_t *)x)==((uint32_t *)LPC_UART1)) \ |
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2:1df0b61d3b5a | 314 | || (((uint32_t *)x)==((uint32_t *)LPC_UART2)) \ |
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2:1df0b61d3b5a | 315 | || (((uint32_t *)x)==((uint32_t *)LPC_UART3))) |
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2:1df0b61d3b5a | 316 | #define PARAM_UART_IrDA(x) (((uint32_t *)x)==((uint32_t *)LPC_UART3)) |
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2:1df0b61d3b5a | 317 | #define PARAM_UART1_MODEM(x) (((uint32_t *)x)==((uint32_t *)LPC_UART1)) |
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2:1df0b61d3b5a | 318 | |
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2:1df0b61d3b5a | 319 | /** Macro to check the input value for UART1_RS485_CFG_MATCHADDRVALUE parameter */ |
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2:1df0b61d3b5a | 320 | #define PARAM_UART1_RS485_CFG_MATCHADDRVALUE(x) ((x<0xFF)) |
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2:1df0b61d3b5a | 321 | |
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2:1df0b61d3b5a | 322 | /** Macro to check the input value for UART1_RS485_CFG_DELAYVALUE parameter */ |
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2:1df0b61d3b5a | 323 | #define PARAM_UART1_RS485_CFG_DELAYVALUE(x) ((x<0xFF)) |
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2:1df0b61d3b5a | 324 | |
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2:1df0b61d3b5a | 325 | /** |
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2:1df0b61d3b5a | 326 | * @} |
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2:1df0b61d3b5a | 327 | */ |
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2:1df0b61d3b5a | 328 | |
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2:1df0b61d3b5a | 329 | |
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2:1df0b61d3b5a | 330 | /* Public Types --------------------------------------------------------------- */ |
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2:1df0b61d3b5a | 331 | /** @defgroup UART_Public_Types UART Public Types |
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2:1df0b61d3b5a | 332 | * @{ |
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2:1df0b61d3b5a | 333 | */ |
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2:1df0b61d3b5a | 334 | |
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2:1df0b61d3b5a | 335 | /** |
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2:1df0b61d3b5a | 336 | * @brief UART Databit type definitions |
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2:1df0b61d3b5a | 337 | */ |
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2:1df0b61d3b5a | 338 | typedef enum { |
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2:1df0b61d3b5a | 339 | UART_DATABIT_5 = 0, /*!< UART 5 bit data mode */ |
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2:1df0b61d3b5a | 340 | UART_DATABIT_6, /*!< UART 6 bit data mode */ |
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2:1df0b61d3b5a | 341 | UART_DATABIT_7, /*!< UART 7 bit data mode */ |
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2:1df0b61d3b5a | 342 | UART_DATABIT_8 /*!< UART 8 bit data mode */ |
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2:1df0b61d3b5a | 343 | } UART_DATABIT_Type; |
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2:1df0b61d3b5a | 344 | |
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2:1df0b61d3b5a | 345 | /** |
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2:1df0b61d3b5a | 346 | * @brief UART Stop bit type definitions |
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2:1df0b61d3b5a | 347 | */ |
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2:1df0b61d3b5a | 348 | typedef enum { |
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2:1df0b61d3b5a | 349 | UART_STOPBIT_1 = (0), /*!< UART 1 Stop Bits Select */ |
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2:1df0b61d3b5a | 350 | UART_STOPBIT_2 /*!< UART Two Stop Bits Select */ |
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2:1df0b61d3b5a | 351 | } UART_STOPBIT_Type; |
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2:1df0b61d3b5a | 352 | |
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2:1df0b61d3b5a | 353 | /** |
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2:1df0b61d3b5a | 354 | * @brief UART Parity type definitions |
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2:1df0b61d3b5a | 355 | */ |
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2:1df0b61d3b5a | 356 | typedef enum { |
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2:1df0b61d3b5a | 357 | UART_PARITY_NONE = 0, /*!< No parity */ |
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2:1df0b61d3b5a | 358 | UART_PARITY_ODD, /*!< Odd parity */ |
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2:1df0b61d3b5a | 359 | UART_PARITY_EVEN, /*!< Even parity */ |
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2:1df0b61d3b5a | 360 | UART_PARITY_SP_1, /*!< Forced "1" stick parity */ |
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2:1df0b61d3b5a | 361 | UART_PARITY_SP_0 /*!< Forced "0" stick parity */ |
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2:1df0b61d3b5a | 362 | } UART_PARITY_Type; |
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2:1df0b61d3b5a | 363 | |
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2:1df0b61d3b5a | 364 | /** |
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2:1df0b61d3b5a | 365 | * @brief FIFO Level type definitions |
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2:1df0b61d3b5a | 366 | */ |
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2:1df0b61d3b5a | 367 | typedef enum { |
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2:1df0b61d3b5a | 368 | UART_FIFO_TRGLEV0 = 0, /*!< UART FIFO trigger level 0: 1 character */ |
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2:1df0b61d3b5a | 369 | UART_FIFO_TRGLEV1, /*!< UART FIFO trigger level 1: 4 character */ |
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2:1df0b61d3b5a | 370 | UART_FIFO_TRGLEV2, /*!< UART FIFO trigger level 2: 8 character */ |
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2:1df0b61d3b5a | 371 | UART_FIFO_TRGLEV3 /*!< UART FIFO trigger level 3: 14 character */ |
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2:1df0b61d3b5a | 372 | } UART_FITO_LEVEL_Type; |
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2:1df0b61d3b5a | 373 | |
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2:1df0b61d3b5a | 374 | /********************************************************************//** |
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2:1df0b61d3b5a | 375 | * @brief UART Interrupt Type definitions |
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2:1df0b61d3b5a | 376 | **********************************************************************/ |
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2:1df0b61d3b5a | 377 | typedef enum { |
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2:1df0b61d3b5a | 378 | UART_INTCFG_RBR = 0, /*!< RBR Interrupt enable*/ |
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2:1df0b61d3b5a | 379 | UART_INTCFG_THRE, /*!< THR Interrupt enable*/ |
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2:1df0b61d3b5a | 380 | UART_INTCFG_RLS, /*!< RX line status interrupt enable*/ |
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2:1df0b61d3b5a | 381 | UART1_INTCFG_MS, /*!< Modem status interrupt enable (UART1 only) */ |
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2:1df0b61d3b5a | 382 | UART1_INTCFG_CTS, /*!< CTS1 signal transition interrupt enable (UART1 only) */ |
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2:1df0b61d3b5a | 383 | UART_INTCFG_ABEO, /*!< Enables the end of auto-baud interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | UART_INTCFG_ABTO /*!< Enables the auto-baud time-out interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | } UART_INT_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | * @brief UART Line Status Type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | UART_LINESTAT_RDR = UART_LSR_RDR, /*!<Line status register: Receive data ready*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | UART_LINESTAT_OE = UART_LSR_OE, /*!<Line status register: Overrun error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | UART_LINESTAT_PE = UART_LSR_PE, /*!<Line status register: Parity error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | UART_LINESTAT_FE = UART_LSR_FE, /*!<Line status register: Framing error*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | UART_LINESTAT_BI = UART_LSR_BI, /*!<Line status register: Break interrupt*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | UART_LINESTAT_THRE = UART_LSR_THRE, /*!<Line status register: Transmit holding register empty*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | UART_LINESTAT_TEMT = UART_LSR_TEMT, /*!<Line status register: Transmitter empty*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | UART_LINESTAT_RXFE = UART_LSR_RXFE /*!<Error in RX FIFO*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | } UART_LS_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 401 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 402 | * @brief UART Auto-baudrate mode type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 403 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 404 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 405 | UART_AUTOBAUD_MODE0 = 0, /**< UART Auto baudrate Mode 0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 406 | UART_AUTOBAUD_MODE1 /**< UART Auto baudrate Mode 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 407 | } UART_AB_MODE_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 408 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 409 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 410 | * @brief Auto Baudrate mode configuration type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 411 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 412 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 413 | UART_AB_MODE_Type ABMode; /**< Autobaudrate mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 414 | FunctionalState AutoRestart; /**< Auto Restart state */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 415 | } UART_AB_CFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 416 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 417 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 418 | * @brief UART End of Auto-baudrate type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 419 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 420 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 421 | UART_AUTOBAUD_INTSTAT_ABEO = UART_IIR_ABEO_INT, /**< UART End of auto-baud interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 422 | UART_AUTOBAUD_INTSTAT_ABTO = UART_IIR_ABTO_INT /**< UART Auto-baud time-out interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 423 | }UART_ABEO_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 424 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 425 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 426 | * UART IrDA Control type Definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 427 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 428 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 429 | UART_IrDA_PULSEDIV2 = 0, /**< Pulse width = 2 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 430 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 431 | UART_IrDA_PULSEDIV4, /**< Pulse width = 4 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 432 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 433 | UART_IrDA_PULSEDIV8, /**< Pulse width = 8 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 434 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 435 | UART_IrDA_PULSEDIV16, /**< Pulse width = 16 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 436 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 437 | UART_IrDA_PULSEDIV32, /**< Pulse width = 32 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 438 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 439 | UART_IrDA_PULSEDIV64, /**< Pulse width = 64 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 440 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 441 | UART_IrDA_PULSEDIV128, /**< Pulse width = 128 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 442 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 443 | UART_IrDA_PULSEDIV256 /**< Pulse width = 256 * Tpclk |
| Michael J. Spencer |
2:1df0b61d3b5a | 444 | - Configures the pulse when FixPulseEn = 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 445 | } UART_IrDA_PULSE_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 446 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 447 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 448 | * @brief UART1 Full modem - Signal states definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 449 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 450 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 451 | INACTIVE = 0, /* In-active state */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 452 | ACTIVE = !INACTIVE /* Active state */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 453 | }UART1_SignalState; |
| Michael J. Spencer |
2:1df0b61d3b5a | 454 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 455 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 456 | * @brief UART modem status type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 457 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 458 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 459 | UART1_MODEM_STAT_DELTA_CTS = UART1_MSR_DELTA_CTS, /*!< Set upon state change of input CTS */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 460 | UART1_MODEM_STAT_DELTA_DSR = UART1_MSR_DELTA_DSR, /*!< Set upon state change of input DSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 461 | UART1_MODEM_STAT_LO2HI_RI = UART1_MSR_LO2HI_RI, /*!< Set upon low to high transition of input RI */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 462 | UART1_MODEM_STAT_DELTA_DCD = UART1_MSR_DELTA_DCD, /*!< Set upon state change of input DCD */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 463 | UART1_MODEM_STAT_CTS = UART1_MSR_CTS, /*!< Clear To Send State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 464 | UART1_MODEM_STAT_DSR = UART1_MSR_DSR, /*!< Data Set Ready State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 465 | UART1_MODEM_STAT_RI = UART1_MSR_RI, /*!< Ring Indicator State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 466 | UART1_MODEM_STAT_DCD = UART1_MSR_DCD /*!< Data Carrier Detect State */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 467 | } UART_MODEM_STAT_type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 468 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 469 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 470 | * @brief Modem output pin type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 471 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 472 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 473 | UART1_MODEM_PIN_DTR = 0, /*!< Source for modem output pin DTR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 474 | UART1_MODEM_PIN_RTS /*!< Source for modem output pin RTS */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 475 | } UART_MODEM_PIN_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 476 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 477 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 478 | * @brief UART Modem mode type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 479 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 480 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 481 | UART1_MODEM_MODE_LOOPBACK = 0, /*!< Loop back mode select */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 482 | UART1_MODEM_MODE_AUTO_RTS, /*!< Enable Auto RTS flow-control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 483 | UART1_MODEM_MODE_AUTO_CTS /*!< Enable Auto CTS flow-control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 484 | } UART_MODEM_MODE_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 485 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 486 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 487 | * @brief UART Direction Control Pin type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 488 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 489 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 490 | UART1_RS485_DIRCTRL_RTS = 0, /**< Pin RTS is used for direction control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 491 | UART1_RS485_DIRCTRL_DTR /**< Pin DTR is used for direction control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 492 | } UART_RS485_DIRCTRL_PIN_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 493 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 494 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 495 | * @brief UART Configuration Structure definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 496 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 497 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 498 | uint32_t Baud_rate; /**< UART baud rate */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 499 | UART_PARITY_Type Parity; /**< Parity selection, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 500 | - UART_PARITY_NONE: No parity |
| Michael J. Spencer |
2:1df0b61d3b5a | 501 | - UART_PARITY_ODD: Odd parity |
| Michael J. Spencer |
2:1df0b61d3b5a | 502 | - UART_PARITY_EVEN: Even parity |
| Michael J. Spencer |
2:1df0b61d3b5a | 503 | - UART_PARITY_SP_1: Forced "1" stick parity |
| Michael J. Spencer |
2:1df0b61d3b5a | 504 | - UART_PARITY_SP_0: Forced "0" stick parity |
| Michael J. Spencer |
2:1df0b61d3b5a | 505 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 506 | UART_DATABIT_Type Databits; /**< Number of data bits, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 507 | - UART_DATABIT_5: UART 5 bit data mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 508 | - UART_DATABIT_6: UART 6 bit data mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 509 | - UART_DATABIT_7: UART 7 bit data mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 510 | - UART_DATABIT_8: UART 8 bit data mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 511 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 512 | UART_STOPBIT_Type Stopbits; /**< Number of stop bits, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 513 | - UART_STOPBIT_1: UART 1 Stop Bits Select |
| Michael J. Spencer |
2:1df0b61d3b5a | 514 | - UART_STOPBIT_2: UART 2 Stop Bits Select |
| Michael J. Spencer |
2:1df0b61d3b5a | 515 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 516 | } UART_CFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 517 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 518 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 519 | * @brief UART FIFO Configuration Structure definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 520 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 521 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 522 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 523 | FunctionalState FIFO_ResetRxBuf; /**< Reset Rx FIFO command state , should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 524 | - ENABLE: Reset Rx FIFO in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 525 | - DISABLE: Do not reset Rx FIFO in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 526 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 527 | FunctionalState FIFO_ResetTxBuf; /**< Reset Tx FIFO command state , should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 528 | - ENABLE: Reset Tx FIFO in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 529 | - DISABLE: Do not reset Tx FIFO in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 530 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 531 | FunctionalState FIFO_DMAMode; /**< DMA mode, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 532 | - ENABLE: Enable DMA mode in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 533 | - DISABLE: Disable DMA mode in UART |
| Michael J. Spencer |
2:1df0b61d3b5a | 534 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 535 | UART_FITO_LEVEL_Type FIFO_Level; /**< Rx FIFO trigger level, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 536 | - UART_FIFO_TRGLEV0: UART FIFO trigger level 0: 1 character |
| Michael J. Spencer |
2:1df0b61d3b5a | 537 | - UART_FIFO_TRGLEV1: UART FIFO trigger level 1: 4 character |
| Michael J. Spencer |
2:1df0b61d3b5a | 538 | - UART_FIFO_TRGLEV2: UART FIFO trigger level 2: 8 character |
| Michael J. Spencer |
2:1df0b61d3b5a | 539 | - UART_FIFO_TRGLEV3: UART FIFO trigger level 3: 14 character |
| Michael J. Spencer |
2:1df0b61d3b5a | 540 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 541 | } UART_FIFO_CFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 542 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 543 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 544 | * @brief UART1 Full modem - RS485 Control configuration type |
| Michael J. Spencer |
2:1df0b61d3b5a | 545 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 546 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 547 | FunctionalState NormalMultiDropMode_State; /*!< Normal MultiDrop mode State: |
| Michael J. Spencer |
2:1df0b61d3b5a | 548 | - ENABLE: Enable this function. |
| Michael J. Spencer |
2:1df0b61d3b5a | 549 | - DISABLE: Disable this function. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 550 | FunctionalState Rx_State; /*!< Receiver State: |
| Michael J. Spencer |
2:1df0b61d3b5a | 551 | - ENABLE: Enable Receiver. |
| Michael J. Spencer |
2:1df0b61d3b5a | 552 | - DISABLE: Disable Receiver. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 553 | FunctionalState AutoAddrDetect_State; /*!< Auto Address Detect mode state: |
| Michael J. Spencer |
2:1df0b61d3b5a | 554 | - ENABLE: ENABLE this function. |
| Michael J. Spencer |
2:1df0b61d3b5a | 555 | - DISABLE: Disable this function. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 556 | FunctionalState AutoDirCtrl_State; /*!< Auto Direction Control State: |
| Michael J. Spencer |
2:1df0b61d3b5a | 557 | - ENABLE: Enable this function. |
| Michael J. Spencer |
2:1df0b61d3b5a | 558 | - DISABLE: Disable this function. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 559 | UART_RS485_DIRCTRL_PIN_Type DirCtrlPin; /*!< If direction control is enabled, state: |
| Michael J. Spencer |
2:1df0b61d3b5a | 560 | - UART1_RS485_DIRCTRL_RTS: |
| Michael J. Spencer |
2:1df0b61d3b5a | 561 | pin RTS is used for direction control. |
| Michael J. Spencer |
2:1df0b61d3b5a | 562 | - UART1_RS485_DIRCTRL_DTR: |
| Michael J. Spencer |
2:1df0b61d3b5a | 563 | pin DTR is used for direction control. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 564 | SetState DirCtrlPol_Level; /*!< Polarity of the direction control signal on |
| Michael J. Spencer |
2:1df0b61d3b5a | 565 | the RTS (or DTR) pin: |
| Michael J. Spencer |
2:1df0b61d3b5a | 566 | - RESET: The direction control pin will be driven |
| Michael J. Spencer |
2:1df0b61d3b5a | 567 | to logic "0" when the transmitter has data to be sent. |
| Michael J. Spencer |
2:1df0b61d3b5a | 568 | - SET: The direction control pin will be driven |
| Michael J. Spencer |
2:1df0b61d3b5a | 569 | to logic "1" when the transmitter has data to be sent. */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 570 | uint8_t MatchAddrValue; /*!< address match value for RS-485/EIA-485 mode, 8-bit long */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 571 | uint8_t DelayValue; /*!< delay time is in periods of the baud clock, 8-bit long */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 572 | } UART1_RS485_CTRLCFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 573 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 574 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 575 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 576 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 577 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 578 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 579 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 580 | /** @defgroup UART_Public_Functions UART Public Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 581 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 582 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 583 | /* UART Init/DeInit functions --------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 584 | void UART_Init(LPC_UART_TypeDef *UARTx, UART_CFG_Type *UART_ConfigStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 585 | void UART_DeInit(LPC_UART_TypeDef* UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 586 | void UART_ConfigStructInit(UART_CFG_Type *UART_InitStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 587 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 588 | /* UART Send/Receive functions -------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 589 | void UART_SendByte(LPC_UART_TypeDef* UARTx, uint8_t Data); |
| Michael J. Spencer |
2:1df0b61d3b5a | 590 | uint8_t UART_ReceiveByte(LPC_UART_TypeDef* UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 591 | uint32_t UART_Send(LPC_UART_TypeDef *UARTx, uint8_t *txbuf, |
| Michael J. Spencer |
2:1df0b61d3b5a | 592 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| Michael J. Spencer |
2:1df0b61d3b5a | 593 | uint32_t UART_Receive(LPC_UART_TypeDef *UARTx, uint8_t *rxbuf, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 594 | uint32_t buflen, TRANSFER_BLOCK_Type flag); |
| Michael J. Spencer |
2:1df0b61d3b5a | 595 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 596 | /* UART FIFO functions ----------------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 597 | void UART_FIFOConfig(LPC_UART_TypeDef *UARTx, UART_FIFO_CFG_Type *FIFOCfg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 598 | void UART_FIFOConfigStructInit(UART_FIFO_CFG_Type *UART_FIFOInitStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 599 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 600 | /* UART get information functions -----------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 601 | uint32_t UART_GetIntId(LPC_UART_TypeDef* UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 602 | uint8_t UART_GetLineStatus(LPC_UART_TypeDef* UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 603 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 604 | /* UART operate functions -------------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 605 | void UART_IntConfig(LPC_UART_TypeDef *UARTx, UART_INT_Type UARTIntCfg, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 606 | FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 607 | void UART_TxCmd(LPC_UART_TypeDef *UARTx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 608 | FlagStatus UART_CheckBusy(LPC_UART_TypeDef *UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 609 | void UART_ForceBreak(LPC_UART_TypeDef* UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 610 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 611 | /* UART Auto-baud functions -----------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 612 | void UART_ABClearIntPending(LPC_UART_TypeDef *UARTx, UART_ABEO_Type ABIntType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 613 | void UART_ABCmd(LPC_UART_TypeDef *UARTx, UART_AB_CFG_Type *ABConfigStruct, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 614 | FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 615 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 616 | /* UART1 FullModem functions ----------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 617 | void UART_FullModemForcePinState(LPC_UART1_TypeDef *UARTx, UART_MODEM_PIN_Type Pin, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 618 | UART1_SignalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 619 | void UART_FullModemConfigMode(LPC_UART1_TypeDef *UARTx, UART_MODEM_MODE_Type Mode, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 620 | FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 621 | uint8_t UART_FullModemGetStatus(LPC_UART1_TypeDef *UARTx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 622 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 623 | /* UART RS485 functions ----------------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 624 | void UART_RS485Config(LPC_UART1_TypeDef *UARTx, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 625 | UART1_RS485_CTRLCFG_Type *RS485ConfigStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 626 | void UART_RS485ReceiverCmd(LPC_UART1_TypeDef *UARTx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 627 | void UART_RS485SendSlvAddr(LPC_UART1_TypeDef *UARTx, uint8_t SlvAddr); |
| Michael J. Spencer |
2:1df0b61d3b5a | 628 | uint32_t UART_RS485SendData(LPC_UART1_TypeDef *UARTx, uint8_t *pData, uint32_t size); |
| Michael J. Spencer |
2:1df0b61d3b5a | 629 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 630 | /* UART IrDA functions-------------------------------------------------------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 631 | void UART_IrDAInvtInputCmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 632 | void UART_IrDACmd(LPC_UART_TypeDef* UARTx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 633 | void UART_IrDAPulseDivConfig(LPC_UART_TypeDef *UARTx, UART_IrDA_PULSE_Type PulseDiv); |
| Michael J. Spencer |
2:1df0b61d3b5a | 634 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 635 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 636 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 637 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 638 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 639 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 640 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 641 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 642 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 643 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 644 | #endif /* __LPC17XX_UART_H */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 645 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 646 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 647 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 648 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 649 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 650 | /* --------------------------------- End Of File ------------------------------ */ |