Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_ssp.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_ssp.h 2010-06-18
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_ssp.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for SSP firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 3.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 18. June. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup SSP SSP (Synchronous Serial Port)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_SSP_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_SSP_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46 /* Public Macros -------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 47 /** @defgroup SSP_Public_Macros SSP Public Macros
Michael J. Spencer 2:1df0b61d3b5a 48 * @{
Michael J. Spencer 2:1df0b61d3b5a 49 */
Michael J. Spencer 2:1df0b61d3b5a 50
Michael J. Spencer 2:1df0b61d3b5a 51 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 52 * SSP configuration parameter defines
Michael J. Spencer 2:1df0b61d3b5a 53 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 54 /** Clock phase control bit */
Michael J. Spencer 2:1df0b61d3b5a 55 #define SSP_CPHA_FIRST ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 56 #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
Michael J. Spencer 2:1df0b61d3b5a 57
Michael J. Spencer 2:1df0b61d3b5a 58
Michael J. Spencer 2:1df0b61d3b5a 59 /** Clock polarity control bit */
Michael J. Spencer 2:1df0b61d3b5a 60 /* There's no bug here!!!
Michael J. Spencer 2:1df0b61d3b5a 61 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
Michael J. Spencer 2:1df0b61d3b5a 62 * That means the active clock is in HI state.
Michael J. Spencer 2:1df0b61d3b5a 63 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
Michael J. Spencer 2:1df0b61d3b5a 64 * high between frames. That means the active clock is in LO state.
Michael J. Spencer 2:1df0b61d3b5a 65 */
Michael J. Spencer 2:1df0b61d3b5a 66 #define SSP_CPOL_HI ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 67 #define SSP_CPOL_LO SSP_CR0_CPOL_HI
Michael J. Spencer 2:1df0b61d3b5a 68
Michael J. Spencer 2:1df0b61d3b5a 69 /** SSP master mode enable */
Michael J. Spencer 2:1df0b61d3b5a 70 #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
Michael J. Spencer 2:1df0b61d3b5a 71 #define SSP_MASTER_MODE ((uint32_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 72
Michael J. Spencer 2:1df0b61d3b5a 73 /** SSP data bit number defines */
Michael J. Spencer 2:1df0b61d3b5a 74 #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
Michael J. Spencer 2:1df0b61d3b5a 75 #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
Michael J. Spencer 2:1df0b61d3b5a 76 #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
Michael J. Spencer 2:1df0b61d3b5a 77 #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
Michael J. Spencer 2:1df0b61d3b5a 78 #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
Michael J. Spencer 2:1df0b61d3b5a 79 #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
Michael J. Spencer 2:1df0b61d3b5a 80 #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
Michael J. Spencer 2:1df0b61d3b5a 81 #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
Michael J. Spencer 2:1df0b61d3b5a 82 #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
Michael J. Spencer 2:1df0b61d3b5a 83 #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
Michael J. Spencer 2:1df0b61d3b5a 84 #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
Michael J. Spencer 2:1df0b61d3b5a 85 #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
Michael J. Spencer 2:1df0b61d3b5a 86 #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
Michael J. Spencer 2:1df0b61d3b5a 87
Michael J. Spencer 2:1df0b61d3b5a 88 /** SSP Frame Format definition */
Michael J. Spencer 2:1df0b61d3b5a 89 /** Motorola SPI mode */
Michael J. Spencer 2:1df0b61d3b5a 90 #define SSP_FRAME_SPI SSP_CR0_FRF_SPI
Michael J. Spencer 2:1df0b61d3b5a 91 /** TI synchronous serial mode */
Michael J. Spencer 2:1df0b61d3b5a 92 #define SSP_FRAME_TI SSP_CR0_FRF_TI
Michael J. Spencer 2:1df0b61d3b5a 93 /** National Micro-wire mode */
Michael J. Spencer 2:1df0b61d3b5a 94 #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
Michael J. Spencer 2:1df0b61d3b5a 95
Michael J. Spencer 2:1df0b61d3b5a 96 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 97 * SSP Status defines
Michael J. Spencer 2:1df0b61d3b5a 98 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 99 /** SSP status TX FIFO Empty bit */
Michael J. Spencer 2:1df0b61d3b5a 100 #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
Michael J. Spencer 2:1df0b61d3b5a 101 /** SSP status TX FIFO not full bit */
Michael J. Spencer 2:1df0b61d3b5a 102 #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
Michael J. Spencer 2:1df0b61d3b5a 103 /** SSP status RX FIFO not empty bit */
Michael J. Spencer 2:1df0b61d3b5a 104 #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
Michael J. Spencer 2:1df0b61d3b5a 105 /** SSP status RX FIFO full bit */
Michael J. Spencer 2:1df0b61d3b5a 106 #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
Michael J. Spencer 2:1df0b61d3b5a 107 /** SSP status SSP Busy bit */
Michael J. Spencer 2:1df0b61d3b5a 108 #define SSP_STAT_BUSY SSP_SR_BSY
Michael J. Spencer 2:1df0b61d3b5a 109
Michael J. Spencer 2:1df0b61d3b5a 110 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 111 * SSP Interrupt Configuration defines
Michael J. Spencer 2:1df0b61d3b5a 112 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 113 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 114 #define SSP_INTCFG_ROR SSP_IMSC_ROR
Michael J. Spencer 2:1df0b61d3b5a 115 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 116 #define SSP_INTCFG_RT SSP_IMSC_RT
Michael J. Spencer 2:1df0b61d3b5a 117 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 118 #define SSP_INTCFG_RX SSP_IMSC_RX
Michael J. Spencer 2:1df0b61d3b5a 119 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 120 #define SSP_INTCFG_TX SSP_IMSC_TX
Michael J. Spencer 2:1df0b61d3b5a 121
Michael J. Spencer 2:1df0b61d3b5a 122 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 123 * SSP Configured Interrupt Status defines
Michael J. Spencer 2:1df0b61d3b5a 124 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 125 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 126 #define SSP_INTSTAT_ROR SSP_MIS_ROR
Michael J. Spencer 2:1df0b61d3b5a 127 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 128 #define SSP_INTSTAT_RT SSP_MIS_RT
Michael J. Spencer 2:1df0b61d3b5a 129 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 130 #define SSP_INTSTAT_RX SSP_MIS_RX
Michael J. Spencer 2:1df0b61d3b5a 131 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 132 #define SSP_INTSTAT_TX SSP_MIS_TX
Michael J. Spencer 2:1df0b61d3b5a 133
Michael J. Spencer 2:1df0b61d3b5a 134 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 135 * SSP Raw Interrupt Status defines
Michael J. Spencer 2:1df0b61d3b5a 136 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 137 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 138 #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
Michael J. Spencer 2:1df0b61d3b5a 139 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 140 #define SSP_INTSTAT_RAW_RT SSP_RIS_RT
Michael J. Spencer 2:1df0b61d3b5a 141 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 142 #define SSP_INTSTAT_RAW_RX SSP_RIS_RX
Michael J. Spencer 2:1df0b61d3b5a 143 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 144 #define SSP_INTSTAT_RAW_TX SSP_RIS_TX
Michael J. Spencer 2:1df0b61d3b5a 145
Michael J. Spencer 2:1df0b61d3b5a 146 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 147 * SSP Interrupt Clear defines
Michael J. Spencer 2:1df0b61d3b5a 148 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 149 /** Writing a 1 to this bit clears the "frame was received when
Michael J. Spencer 2:1df0b61d3b5a 150 * RxFIFO was full" interrupt */
Michael J. Spencer 2:1df0b61d3b5a 151 #define SSP_INTCLR_ROR SSP_ICR_ROR
Michael J. Spencer 2:1df0b61d3b5a 152 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
Michael J. Spencer 2:1df0b61d3b5a 153 * has not been read for a timeout period" interrupt */
Michael J. Spencer 2:1df0b61d3b5a 154 #define SSP_INTCLR_RT SSP_ICR_RT
Michael J. Spencer 2:1df0b61d3b5a 155
Michael J. Spencer 2:1df0b61d3b5a 156 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 157 * SSP DMA defines
Michael J. Spencer 2:1df0b61d3b5a 158 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 159 /** SSP bit for enabling RX DMA */
Michael J. Spencer 2:1df0b61d3b5a 160 #define SSP_DMA_RX SSP_DMA_RXDMA_EN
Michael J. Spencer 2:1df0b61d3b5a 161 /** SSP bit for enabling TX DMA */
Michael J. Spencer 2:1df0b61d3b5a 162 #define SSP_DMA_TX SSP_DMA_TXDMA_EN
Michael J. Spencer 2:1df0b61d3b5a 163
Michael J. Spencer 2:1df0b61d3b5a 164 /* SSP Status Implementation definitions */
Michael J. Spencer 2:1df0b61d3b5a 165 #define SSP_STAT_DONE (1UL<<8) /**< Done */
Michael J. Spencer 2:1df0b61d3b5a 166 #define SSP_STAT_ERROR (1UL<<9) /**< Error */
Michael J. Spencer 2:1df0b61d3b5a 167
Michael J. Spencer 2:1df0b61d3b5a 168 /**
Michael J. Spencer 2:1df0b61d3b5a 169 * @}
Michael J. Spencer 2:1df0b61d3b5a 170 */
Michael J. Spencer 2:1df0b61d3b5a 171
Michael J. Spencer 2:1df0b61d3b5a 172 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 173 /** @defgroup SSP_Private_Macros SSP Private Macros
Michael J. Spencer 2:1df0b61d3b5a 174 * @{
Michael J. Spencer 2:1df0b61d3b5a 175 */
Michael J. Spencer 2:1df0b61d3b5a 176
Michael J. Spencer 2:1df0b61d3b5a 177 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 178 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 179 * Macro defines for CR0 register
Michael J. Spencer 2:1df0b61d3b5a 180 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 181 /** SSP data size select, must be 4 bits to 16 bits */
Michael J. Spencer 2:1df0b61d3b5a 182 #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
Michael J. Spencer 2:1df0b61d3b5a 183 /** SSP control 0 Motorola SPI mode */
Michael J. Spencer 2:1df0b61d3b5a 184 #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
Michael J. Spencer 2:1df0b61d3b5a 185 /** SSP control 0 TI synchronous serial mode */
Michael J. Spencer 2:1df0b61d3b5a 186 #define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 187 /** SSP control 0 National Micro-wire mode */
Michael J. Spencer 2:1df0b61d3b5a 188 #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
Michael J. Spencer 2:1df0b61d3b5a 189 /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
Michael J. Spencer 2:1df0b61d3b5a 190 bus clock high between frames, (0) = low */
Michael J. Spencer 2:1df0b61d3b5a 191 #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
Michael J. Spencer 2:1df0b61d3b5a 192 /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
Michael J. Spencer 2:1df0b61d3b5a 193 on the second clock transition of the frame, (0) = first */
Michael J. Spencer 2:1df0b61d3b5a 194 #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
Michael J. Spencer 2:1df0b61d3b5a 195 /** SSP serial clock rate value load macro, divider rate is
Michael J. Spencer 2:1df0b61d3b5a 196 PERIPH_CLK / (cpsr * (SCR + 1)) */
Michael J. Spencer 2:1df0b61d3b5a 197 #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
Michael J. Spencer 2:1df0b61d3b5a 198 /** SSP CR0 bit mask */
Michael J. Spencer 2:1df0b61d3b5a 199 #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 200
Michael J. Spencer 2:1df0b61d3b5a 201 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 202 * Macro defines for CR1 register
Michael J. Spencer 2:1df0b61d3b5a 203 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 204 /** SSP control 1 loopback mode enable bit */
Michael J. Spencer 2:1df0b61d3b5a 205 #define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 206 /** SSP control 1 enable bit */
Michael J. Spencer 2:1df0b61d3b5a 207 #define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 208 /** SSP control 1 slave enable */
Michael J. Spencer 2:1df0b61d3b5a 209 #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 210 /** SSP control 1 slave out disable bit, disables transmit line in slave
Michael J. Spencer 2:1df0b61d3b5a 211 mode */
Michael J. Spencer 2:1df0b61d3b5a 212 #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 213 /** SSP CR1 bit mask */
Michael J. Spencer 2:1df0b61d3b5a 214 #define SSP_CR1_BITMASK ((uint32_t)(0x0F))
Michael J. Spencer 2:1df0b61d3b5a 215
Michael J. Spencer 2:1df0b61d3b5a 216 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 217 * Macro defines for DR register
Michael J. Spencer 2:1df0b61d3b5a 218 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 219 /** SSP data bit mask */
Michael J. Spencer 2:1df0b61d3b5a 220 #define SSP_DR_BITMASK(n) ((n)&0xFFFF)
Michael J. Spencer 2:1df0b61d3b5a 221
Michael J. Spencer 2:1df0b61d3b5a 222 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 223 * Macro defines for SR register
Michael J. Spencer 2:1df0b61d3b5a 224 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 225 /** SSP status TX FIFO Empty bit */
Michael J. Spencer 2:1df0b61d3b5a 226 #define SSP_SR_TFE ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 227 /** SSP status TX FIFO not full bit */
Michael J. Spencer 2:1df0b61d3b5a 228 #define SSP_SR_TNF ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 229 /** SSP status RX FIFO not empty bit */
Michael J. Spencer 2:1df0b61d3b5a 230 #define SSP_SR_RNE ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 231 /** SSP status RX FIFO full bit */
Michael J. Spencer 2:1df0b61d3b5a 232 #define SSP_SR_RFF ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 233 /** SSP status SSP Busy bit */
Michael J. Spencer 2:1df0b61d3b5a 234 #define SSP_SR_BSY ((uint32_t)(1<<4))
Michael J. Spencer 2:1df0b61d3b5a 235 /** SSP SR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 236 #define SSP_SR_BITMASK ((uint32_t)(0x1F))
Michael J. Spencer 2:1df0b61d3b5a 237
Michael J. Spencer 2:1df0b61d3b5a 238 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 239 * Macro defines for CPSR register
Michael J. Spencer 2:1df0b61d3b5a 240 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 241 /** SSP clock prescaler */
Michael J. Spencer 2:1df0b61d3b5a 242 #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 243 /** SSP CPSR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 244 #define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
Michael J. Spencer 2:1df0b61d3b5a 245
Michael J. Spencer 2:1df0b61d3b5a 246 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 247 * Macro define for (IMSC) Interrupt Mask Set/Clear registers
Michael J. Spencer 2:1df0b61d3b5a 248 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 249 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 250 #define SSP_IMSC_ROR ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 251 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 252 #define SSP_IMSC_RT ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 253 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 254 #define SSP_IMSC_RX ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 255 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 256 #define SSP_IMSC_TX ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 257 /** IMSC bit mask */
Michael J. Spencer 2:1df0b61d3b5a 258 #define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
Michael J. Spencer 2:1df0b61d3b5a 259
Michael J. Spencer 2:1df0b61d3b5a 260 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 261 * Macro define for (RIS) Raw Interrupt Status registers
Michael J. Spencer 2:1df0b61d3b5a 262 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 263 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 264 #define SSP_RIS_ROR ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 265 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 266 #define SSP_RIS_RT ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 267 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 268 #define SSP_RIS_RX ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 269 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 270 #define SSP_RIS_TX ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 271 /** RIS bit mask */
Michael J. Spencer 2:1df0b61d3b5a 272 #define SSP_RIS_BITMASK ((uint32_t)(0x0F))
Michael J. Spencer 2:1df0b61d3b5a 273
Michael J. Spencer 2:1df0b61d3b5a 274 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 275 * Macro define for (MIS) Masked Interrupt Status registers
Michael J. Spencer 2:1df0b61d3b5a 276 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 277 /** Receive Overrun */
Michael J. Spencer 2:1df0b61d3b5a 278 #define SSP_MIS_ROR ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 279 /** Receive TimeOut */
Michael J. Spencer 2:1df0b61d3b5a 280 #define SSP_MIS_RT ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 281 /** Rx FIFO is at least half full */
Michael J. Spencer 2:1df0b61d3b5a 282 #define SSP_MIS_RX ((uint32_t)(1<<2))
Michael J. Spencer 2:1df0b61d3b5a 283 /** Tx FIFO is at least half empty */
Michael J. Spencer 2:1df0b61d3b5a 284 #define SSP_MIS_TX ((uint32_t)(1<<3))
Michael J. Spencer 2:1df0b61d3b5a 285 /** MIS bit mask */
Michael J. Spencer 2:1df0b61d3b5a 286 #define SSP_MIS_BITMASK ((uint32_t)(0x0F))
Michael J. Spencer 2:1df0b61d3b5a 287
Michael J. Spencer 2:1df0b61d3b5a 288 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 289 * Macro define for (ICR) Interrupt Clear registers
Michael J. Spencer 2:1df0b61d3b5a 290 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 291 /** Writing a 1 to this bit clears the "frame was received when
Michael J. Spencer 2:1df0b61d3b5a 292 * RxFIFO was full" interrupt */
Michael J. Spencer 2:1df0b61d3b5a 293 #define SSP_ICR_ROR ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 294 /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
Michael J. Spencer 2:1df0b61d3b5a 295 * has not been read for a timeout period" interrupt */
Michael J. Spencer 2:1df0b61d3b5a 296 #define SSP_ICR_RT ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 297 /** ICR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 298 #define SSP_ICR_BITMASK ((uint32_t)(0x03))
Michael J. Spencer 2:1df0b61d3b5a 299
Michael J. Spencer 2:1df0b61d3b5a 300 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 301 * Macro defines for DMACR register
Michael J. Spencer 2:1df0b61d3b5a 302 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 303 /** SSP bit for enabling RX DMA */
Michael J. Spencer 2:1df0b61d3b5a 304 #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
Michael J. Spencer 2:1df0b61d3b5a 305 /** SSP bit for enabling TX DMA */
Michael J. Spencer 2:1df0b61d3b5a 306 #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
Michael J. Spencer 2:1df0b61d3b5a 307 /** DMACR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 308 #define SSP_DMA_BITMASK ((uint32_t)(0x03))
Michael J. Spencer 2:1df0b61d3b5a 309
Michael J. Spencer 2:1df0b61d3b5a 310
Michael J. Spencer 2:1df0b61d3b5a 311 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 312 /** Macro to determine if it is valid SSP port number */
Michael J. Spencer 2:1df0b61d3b5a 313 #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
Michael J. Spencer 2:1df0b61d3b5a 314 || (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
Michael J. Spencer 2:1df0b61d3b5a 315
Michael J. Spencer 2:1df0b61d3b5a 316 /** Macro check clock phase control mode */
Michael J. Spencer 2:1df0b61d3b5a 317 #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
Michael J. Spencer 2:1df0b61d3b5a 318
Michael J. Spencer 2:1df0b61d3b5a 319 /** Macro check clock polarity mode */
Michael J. Spencer 2:1df0b61d3b5a 320 #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
Michael J. Spencer 2:1df0b61d3b5a 321
Michael J. Spencer 2:1df0b61d3b5a 322 /* Macro check master/slave mode */
Michael J. Spencer 2:1df0b61d3b5a 323 #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
Michael J. Spencer 2:1df0b61d3b5a 324
Michael J. Spencer 2:1df0b61d3b5a 325 /* Macro check databit value */
Michael J. Spencer 2:1df0b61d3b5a 326 #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
Michael J. Spencer 2:1df0b61d3b5a 327 || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
Michael J. Spencer 2:1df0b61d3b5a 328 || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
Michael J. Spencer 2:1df0b61d3b5a 329 || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
Michael J. Spencer 2:1df0b61d3b5a 330 || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
Michael J. Spencer 2:1df0b61d3b5a 331 || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
Michael J. Spencer 2:1df0b61d3b5a 332 || (n==SSP_DATABIT_15))
Michael J. Spencer 2:1df0b61d3b5a 333
Michael J. Spencer 2:1df0b61d3b5a 334 /* Macro check frame type */
Michael J. Spencer 2:1df0b61d3b5a 335 #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
Michael J. Spencer 2:1df0b61d3b5a 336 || (n==SSP_FRAME_MICROWIRE))
Michael J. Spencer 2:1df0b61d3b5a 337
Michael J. Spencer 2:1df0b61d3b5a 338 /* Macro check SSP status */
Michael J. Spencer 2:1df0b61d3b5a 339 #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
Michael J. Spencer 2:1df0b61d3b5a 340 || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
Michael J. Spencer 2:1df0b61d3b5a 341 || (n==SSP_STAT_BUSY))
Michael J. Spencer 2:1df0b61d3b5a 342
Michael J. Spencer 2:1df0b61d3b5a 343 /* Macro check interrupt configuration */
Michael J. Spencer 2:1df0b61d3b5a 344 #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
Michael J. Spencer 2:1df0b61d3b5a 345 || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
Michael J. Spencer 2:1df0b61d3b5a 346
Michael J. Spencer 2:1df0b61d3b5a 347 /* Macro check interrupt status value */
Michael J. Spencer 2:1df0b61d3b5a 348 #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
Michael J. Spencer 2:1df0b61d3b5a 349 || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
Michael J. Spencer 2:1df0b61d3b5a 350
Michael J. Spencer 2:1df0b61d3b5a 351 /* Macro check interrupt status raw value */
Michael J. Spencer 2:1df0b61d3b5a 352 #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
Michael J. Spencer 2:1df0b61d3b5a 353 || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
Michael J. Spencer 2:1df0b61d3b5a 354
Michael J. Spencer 2:1df0b61d3b5a 355 /* Macro check interrupt clear mode */
Michael J. Spencer 2:1df0b61d3b5a 356 #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
Michael J. Spencer 2:1df0b61d3b5a 357
Michael J. Spencer 2:1df0b61d3b5a 358 /* Macro check DMA mode */
Michael J. Spencer 2:1df0b61d3b5a 359 #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
Michael J. Spencer 2:1df0b61d3b5a 360 /**
Michael J. Spencer 2:1df0b61d3b5a 361 * @}
Michael J. Spencer 2:1df0b61d3b5a 362 */
Michael J. Spencer 2:1df0b61d3b5a 363
Michael J. Spencer 2:1df0b61d3b5a 364
Michael J. Spencer 2:1df0b61d3b5a 365 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 366 /** @defgroup SSP_Public_Types SSP Public Types
Michael J. Spencer 2:1df0b61d3b5a 367 * @{
Michael J. Spencer 2:1df0b61d3b5a 368 */
Michael J. Spencer 2:1df0b61d3b5a 369
Michael J. Spencer 2:1df0b61d3b5a 370 /** @brief SSP configuration structure */
Michael J. Spencer 2:1df0b61d3b5a 371 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 372 uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
Michael J. Spencer 2:1df0b61d3b5a 373 where x is in range from 4 - 16 */
Michael J. Spencer 2:1df0b61d3b5a 374 uint32_t CPHA; /** Clock phase, should be:
Michael J. Spencer 2:1df0b61d3b5a 375 - SSP_CPHA_FIRST: first clock edge
Michael J. Spencer 2:1df0b61d3b5a 376 - SSP_CPHA_SECOND: second clock edge */
Michael J. Spencer 2:1df0b61d3b5a 377 uint32_t CPOL; /** Clock polarity, should be:
Michael J. Spencer 2:1df0b61d3b5a 378 - SSP_CPOL_HI: high level
Michael J. Spencer 2:1df0b61d3b5a 379 - SSP_CPOL_LO: low level */
Michael J. Spencer 2:1df0b61d3b5a 380 uint32_t Mode; /** SSP mode, should be:
Michael J. Spencer 2:1df0b61d3b5a 381 - SSP_MASTER_MODE: Master mode
Michael J. Spencer 2:1df0b61d3b5a 382 - SSP_SLAVE_MODE: Slave mode */
Michael J. Spencer 2:1df0b61d3b5a 383 uint32_t FrameFormat; /** Frame Format:
Michael J. Spencer 2:1df0b61d3b5a 384 - SSP_FRAME_SPI: Motorola SPI frame format
Michael J. Spencer 2:1df0b61d3b5a 385 - SSP_FRAME_TI: TI frame format
Michael J. Spencer 2:1df0b61d3b5a 386 - SSP_FRAME_MICROWIRE: National Microwire frame format */
Michael J. Spencer 2:1df0b61d3b5a 387 uint32_t ClockRate; /** Clock rate,in Hz */
Michael J. Spencer 2:1df0b61d3b5a 388 } SSP_CFG_Type;
Michael J. Spencer 2:1df0b61d3b5a 389
Michael J. Spencer 2:1df0b61d3b5a 390 /**
Michael J. Spencer 2:1df0b61d3b5a 391 * @brief SSP Transfer Type definitions
Michael J. Spencer 2:1df0b61d3b5a 392 */
Michael J. Spencer 2:1df0b61d3b5a 393 typedef enum {
Michael J. Spencer 2:1df0b61d3b5a 394 SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
Michael J. Spencer 2:1df0b61d3b5a 395 SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
Michael J. Spencer 2:1df0b61d3b5a 396 } SSP_TRANSFER_Type;
Michael J. Spencer 2:1df0b61d3b5a 397
Michael J. Spencer 2:1df0b61d3b5a 398 /**
Michael J. Spencer 2:1df0b61d3b5a 399 * @brief SPI Data configuration structure definitions
Michael J. Spencer 2:1df0b61d3b5a 400 */
Michael J. Spencer 2:1df0b61d3b5a 401 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 402 void *tx_data; /**< Pointer to transmit data */
Michael J. Spencer 2:1df0b61d3b5a 403 uint32_t tx_cnt; /**< Transmit counter */
Michael J. Spencer 2:1df0b61d3b5a 404 void *rx_data; /**< Pointer to transmit data */
Michael J. Spencer 2:1df0b61d3b5a 405 uint32_t rx_cnt; /**< Receive counter */
Michael J. Spencer 2:1df0b61d3b5a 406 uint32_t length; /**< Length of transfer data */
Michael J. Spencer 2:1df0b61d3b5a 407 uint32_t status; /**< Current status of SSP activity */
Michael J. Spencer 2:1df0b61d3b5a 408 } SSP_DATA_SETUP_Type;
Michael J. Spencer 2:1df0b61d3b5a 409
Michael J. Spencer 2:1df0b61d3b5a 410
Michael J. Spencer 2:1df0b61d3b5a 411 /**
Michael J. Spencer 2:1df0b61d3b5a 412 * @}
Michael J. Spencer 2:1df0b61d3b5a 413 */
Michael J. Spencer 2:1df0b61d3b5a 414
Michael J. Spencer 2:1df0b61d3b5a 415
Michael J. Spencer 2:1df0b61d3b5a 416 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 417 /** @defgroup SSP_Public_Functions SSP Public Functions
Michael J. Spencer 2:1df0b61d3b5a 418 * @{
Michael J. Spencer 2:1df0b61d3b5a 419 */
Michael J. Spencer 2:1df0b61d3b5a 420
Michael J. Spencer 2:1df0b61d3b5a 421 /* SSP Init/DeInit functions --------------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 422 void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
Michael J. Spencer 2:1df0b61d3b5a 423 void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
Michael J. Spencer 2:1df0b61d3b5a 424
Michael J. Spencer 2:1df0b61d3b5a 425 /* SSP configure functions ----------------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 426 void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
Michael J. Spencer 2:1df0b61d3b5a 427
Michael J. Spencer 2:1df0b61d3b5a 428 /* SSP enable/disable functions -----------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 429 void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 430 void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 431 void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 432 void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 433
Michael J. Spencer 2:1df0b61d3b5a 434 /* SSP get information functions ----------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 435 FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
Michael J. Spencer 2:1df0b61d3b5a 436 uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
Michael J. Spencer 2:1df0b61d3b5a 437 IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
Michael J. Spencer 2:1df0b61d3b5a 438 uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
Michael J. Spencer 2:1df0b61d3b5a 439 IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
Michael J. Spencer 2:1df0b61d3b5a 440
Michael J. Spencer 2:1df0b61d3b5a 441 /* SSP transfer data functions ------------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 442 void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
Michael J. Spencer 2:1df0b61d3b5a 443 uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
Michael J. Spencer 2:1df0b61d3b5a 444 int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
Michael J. Spencer 2:1df0b61d3b5a 445 SSP_TRANSFER_Type xfType);
Michael J. Spencer 2:1df0b61d3b5a 446
Michael J. Spencer 2:1df0b61d3b5a 447 /* SSP IRQ function ------------------------------------------------------------*/
Michael J. Spencer 2:1df0b61d3b5a 448 void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 449 void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
Michael J. Spencer 2:1df0b61d3b5a 450
Michael J. Spencer 2:1df0b61d3b5a 451
Michael J. Spencer 2:1df0b61d3b5a 452 /**
Michael J. Spencer 2:1df0b61d3b5a 453 * @}
Michael J. Spencer 2:1df0b61d3b5a 454 */
Michael J. Spencer 2:1df0b61d3b5a 455
Michael J. Spencer 2:1df0b61d3b5a 456 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 457 }
Michael J. Spencer 2:1df0b61d3b5a 458 #endif
Michael J. Spencer 2:1df0b61d3b5a 459
Michael J. Spencer 2:1df0b61d3b5a 460 #endif /* LPC17XX_SSP_H_ */
Michael J. Spencer 2:1df0b61d3b5a 461
Michael J. Spencer 2:1df0b61d3b5a 462 /**
Michael J. Spencer 2:1df0b61d3b5a 463 * @}
Michael J. Spencer 2:1df0b61d3b5a 464 */
Michael J. Spencer 2:1df0b61d3b5a 465
Michael J. Spencer 2:1df0b61d3b5a 466 /* --------------------------------- End Of File ------------------------------ */