Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_rtc.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_rtc.h 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_rtc.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for RTC firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup RTC RTC (Real Time Clock)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_RTC_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_RTC_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46
Michael J. Spencer 2:1df0b61d3b5a 47 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 48 /** @defgroup RTC_Private_Macros RTC Private Macros
Michael J. Spencer 2:1df0b61d3b5a 49 * @{
Michael J. Spencer 2:1df0b61d3b5a 50 */
Michael J. Spencer 2:1df0b61d3b5a 51
Michael J. Spencer 2:1df0b61d3b5a 52 /* ----------------------- BIT DEFINITIONS ----------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 53 /* Miscellaneous register group --------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 54 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 55 * ILR register definitions
Michael J. Spencer 2:1df0b61d3b5a 56 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 57 /** ILR register mask */
Michael J. Spencer 2:1df0b61d3b5a 58 #define RTC_ILR_BITMASK ((0x00000003))
Michael J. Spencer 2:1df0b61d3b5a 59 /** Bit inform the source interrupt is counter increment*/
Michael J. Spencer 2:1df0b61d3b5a 60 #define RTC_IRL_RTCCIF ((1<<0))
Michael J. Spencer 2:1df0b61d3b5a 61 /** Bit inform the source interrupt is alarm match*/
Michael J. Spencer 2:1df0b61d3b5a 62 #define RTC_IRL_RTCALF ((1<<1))
Michael J. Spencer 2:1df0b61d3b5a 63
Michael J. Spencer 2:1df0b61d3b5a 64 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 65 * CCR register definitions
Michael J. Spencer 2:1df0b61d3b5a 66 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 67 /** CCR register mask */
Michael J. Spencer 2:1df0b61d3b5a 68 #define RTC_CCR_BITMASK ((0x00000013))
Michael J. Spencer 2:1df0b61d3b5a 69 /** Clock enable */
Michael J. Spencer 2:1df0b61d3b5a 70 #define RTC_CCR_CLKEN ((1<<0))
Michael J. Spencer 2:1df0b61d3b5a 71 /** Clock reset */
Michael J. Spencer 2:1df0b61d3b5a 72 #define RTC_CCR_CTCRST ((1<<1))
Michael J. Spencer 2:1df0b61d3b5a 73 /** Calibration counter enable */
Michael J. Spencer 2:1df0b61d3b5a 74 #define RTC_CCR_CCALEN ((1<<4))
Michael J. Spencer 2:1df0b61d3b5a 75
Michael J. Spencer 2:1df0b61d3b5a 76 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 77 * CIIR register definitions
Michael J. Spencer 2:1df0b61d3b5a 78 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 79 /** Counter Increment Interrupt bit for second */
Michael J. Spencer 2:1df0b61d3b5a 80 #define RTC_CIIR_IMSEC ((1<<0))
Michael J. Spencer 2:1df0b61d3b5a 81 /** Counter Increment Interrupt bit for minute */
Michael J. Spencer 2:1df0b61d3b5a 82 #define RTC_CIIR_IMMIN ((1<<1))
Michael J. Spencer 2:1df0b61d3b5a 83 /** Counter Increment Interrupt bit for hour */
Michael J. Spencer 2:1df0b61d3b5a 84 #define RTC_CIIR_IMHOUR ((1<<2))
Michael J. Spencer 2:1df0b61d3b5a 85 /** Counter Increment Interrupt bit for day of month */
Michael J. Spencer 2:1df0b61d3b5a 86 #define RTC_CIIR_IMDOM ((1<<3))
Michael J. Spencer 2:1df0b61d3b5a 87 /** Counter Increment Interrupt bit for day of week */
Michael J. Spencer 2:1df0b61d3b5a 88 #define RTC_CIIR_IMDOW ((1<<4))
Michael J. Spencer 2:1df0b61d3b5a 89 /** Counter Increment Interrupt bit for day of year */
Michael J. Spencer 2:1df0b61d3b5a 90 #define RTC_CIIR_IMDOY ((1<<5))
Michael J. Spencer 2:1df0b61d3b5a 91 /** Counter Increment Interrupt bit for month */
Michael J. Spencer 2:1df0b61d3b5a 92 #define RTC_CIIR_IMMON ((1<<6))
Michael J. Spencer 2:1df0b61d3b5a 93 /** Counter Increment Interrupt bit for year */
Michael J. Spencer 2:1df0b61d3b5a 94 #define RTC_CIIR_IMYEAR ((1<<7))
Michael J. Spencer 2:1df0b61d3b5a 95 /** CIIR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 96 #define RTC_CIIR_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 97
Michael J. Spencer 2:1df0b61d3b5a 98 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 99 * AMR register definitions
Michael J. Spencer 2:1df0b61d3b5a 100 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 101 /** Counter Increment Select Mask bit for second */
Michael J. Spencer 2:1df0b61d3b5a 102 #define RTC_AMR_AMRSEC ((1<<0))
Michael J. Spencer 2:1df0b61d3b5a 103 /** Counter Increment Select Mask bit for minute */
Michael J. Spencer 2:1df0b61d3b5a 104 #define RTC_AMR_AMRMIN ((1<<1))
Michael J. Spencer 2:1df0b61d3b5a 105 /** Counter Increment Select Mask bit for hour */
Michael J. Spencer 2:1df0b61d3b5a 106 #define RTC_AMR_AMRHOUR ((1<<2))
Michael J. Spencer 2:1df0b61d3b5a 107 /** Counter Increment Select Mask bit for day of month */
Michael J. Spencer 2:1df0b61d3b5a 108 #define RTC_AMR_AMRDOM ((1<<3))
Michael J. Spencer 2:1df0b61d3b5a 109 /** Counter Increment Select Mask bit for day of week */
Michael J. Spencer 2:1df0b61d3b5a 110 #define RTC_AMR_AMRDOW ((1<<4))
Michael J. Spencer 2:1df0b61d3b5a 111 /** Counter Increment Select Mask bit for day of year */
Michael J. Spencer 2:1df0b61d3b5a 112 #define RTC_AMR_AMRDOY ((1<<5))
Michael J. Spencer 2:1df0b61d3b5a 113 /** Counter Increment Select Mask bit for month */
Michael J. Spencer 2:1df0b61d3b5a 114 #define RTC_AMR_AMRMON ((1<<6))
Michael J. Spencer 2:1df0b61d3b5a 115 /** Counter Increment Select Mask bit for year */
Michael J. Spencer 2:1df0b61d3b5a 116 #define RTC_AMR_AMRYEAR ((1<<7))
Michael J. Spencer 2:1df0b61d3b5a 117 /** AMR bit mask */
Michael J. Spencer 2:1df0b61d3b5a 118 #define RTC_AMR_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 119
Michael J. Spencer 2:1df0b61d3b5a 120 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 121 * RTC_AUX register definitions
Michael J. Spencer 2:1df0b61d3b5a 122 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 123 /** RTC Oscillator Fail detect flag */
Michael J. Spencer 2:1df0b61d3b5a 124 #define RTC_AUX_RTC_OSCF ((1<<4))
Michael J. Spencer 2:1df0b61d3b5a 125
Michael J. Spencer 2:1df0b61d3b5a 126 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 127 * RTC_AUXEN register definitions
Michael J. Spencer 2:1df0b61d3b5a 128 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 129 /** Oscillator Fail Detect interrupt enable*/
Michael J. Spencer 2:1df0b61d3b5a 130 #define RTC_AUXEN_RTC_OSCFEN ((1<<4))
Michael J. Spencer 2:1df0b61d3b5a 131
Michael J. Spencer 2:1df0b61d3b5a 132 /* Consolidated time register group ----------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 133 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 134 * Consolidated Time Register 0 definitions
Michael J. Spencer 2:1df0b61d3b5a 135 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 136 #define RTC_CTIME0_SECONDS_MASK ((0x3F))
Michael J. Spencer 2:1df0b61d3b5a 137 #define RTC_CTIME0_MINUTES_MASK ((0x3F00))
Michael J. Spencer 2:1df0b61d3b5a 138 #define RTC_CTIME0_HOURS_MASK ((0x1F0000))
Michael J. Spencer 2:1df0b61d3b5a 139 #define RTC_CTIME0_DOW_MASK ((0x7000000))
Michael J. Spencer 2:1df0b61d3b5a 140
Michael J. Spencer 2:1df0b61d3b5a 141 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 142 * Consolidated Time Register 1 definitions
Michael J. Spencer 2:1df0b61d3b5a 143 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 144 #define RTC_CTIME1_DOM_MASK ((0x1F))
Michael J. Spencer 2:1df0b61d3b5a 145 #define RTC_CTIME1_MONTH_MASK ((0xF00))
Michael J. Spencer 2:1df0b61d3b5a 146 #define RTC_CTIME1_YEAR_MASK ((0xFFF0000))
Michael J. Spencer 2:1df0b61d3b5a 147
Michael J. Spencer 2:1df0b61d3b5a 148 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 149 * Consolidated Time Register 2 definitions
Michael J. Spencer 2:1df0b61d3b5a 150 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 151 #define RTC_CTIME2_DOY_MASK ((0xFFF))
Michael J. Spencer 2:1df0b61d3b5a 152
Michael J. Spencer 2:1df0b61d3b5a 153 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 154 * Time Counter Group and Alarm register group
Michael J. Spencer 2:1df0b61d3b5a 155 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 156 /** SEC register mask */
Michael J. Spencer 2:1df0b61d3b5a 157 #define RTC_SEC_MASK (0x0000003F)
Michael J. Spencer 2:1df0b61d3b5a 158 /** MIN register mask */
Michael J. Spencer 2:1df0b61d3b5a 159 #define RTC_MIN_MASK (0x0000003F)
Michael J. Spencer 2:1df0b61d3b5a 160 /** HOUR register mask */
Michael J. Spencer 2:1df0b61d3b5a 161 #define RTC_HOUR_MASK (0x0000001F)
Michael J. Spencer 2:1df0b61d3b5a 162 /** DOM register mask */
Michael J. Spencer 2:1df0b61d3b5a 163 #define RTC_DOM_MASK (0x0000001F)
Michael J. Spencer 2:1df0b61d3b5a 164 /** DOW register mask */
Michael J. Spencer 2:1df0b61d3b5a 165 #define RTC_DOW_MASK (0x00000007)
Michael J. Spencer 2:1df0b61d3b5a 166 /** DOY register mask */
Michael J. Spencer 2:1df0b61d3b5a 167 #define RTC_DOY_MASK (0x000001FF)
Michael J. Spencer 2:1df0b61d3b5a 168 /** MONTH register mask */
Michael J. Spencer 2:1df0b61d3b5a 169 #define RTC_MONTH_MASK (0x0000000F)
Michael J. Spencer 2:1df0b61d3b5a 170 /** YEAR register mask */
Michael J. Spencer 2:1df0b61d3b5a 171 #define RTC_YEAR_MASK (0x00000FFF)
Michael J. Spencer 2:1df0b61d3b5a 172
Michael J. Spencer 2:1df0b61d3b5a 173 #define RTC_SECOND_MAX 59 /*!< Maximum value of second */
Michael J. Spencer 2:1df0b61d3b5a 174 #define RTC_MINUTE_MAX 59 /*!< Maximum value of minute*/
Michael J. Spencer 2:1df0b61d3b5a 175 #define RTC_HOUR_MAX 23 /*!< Maximum value of hour*/
Michael J. Spencer 2:1df0b61d3b5a 176 #define RTC_MONTH_MIN 1 /*!< Minimum value of month*/
Michael J. Spencer 2:1df0b61d3b5a 177 #define RTC_MONTH_MAX 12 /*!< Maximum value of month*/
Michael J. Spencer 2:1df0b61d3b5a 178 #define RTC_DAYOFMONTH_MIN 1 /*!< Minimum value of day of month*/
Michael J. Spencer 2:1df0b61d3b5a 179 #define RTC_DAYOFMONTH_MAX 31 /*!< Maximum value of day of month*/
Michael J. Spencer 2:1df0b61d3b5a 180 #define RTC_DAYOFWEEK_MAX 6 /*!< Maximum value of day of week*/
Michael J. Spencer 2:1df0b61d3b5a 181 #define RTC_DAYOFYEAR_MIN 1 /*!< Minimum value of day of year*/
Michael J. Spencer 2:1df0b61d3b5a 182 #define RTC_DAYOFYEAR_MAX 366 /*!< Maximum value of day of year*/
Michael J. Spencer 2:1df0b61d3b5a 183 #define RTC_YEAR_MAX 4095 /*!< Maximum value of year*/
Michael J. Spencer 2:1df0b61d3b5a 184
Michael J. Spencer 2:1df0b61d3b5a 185 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 186 * Calibration register
Michael J. Spencer 2:1df0b61d3b5a 187 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 188 /* Calibration register */
Michael J. Spencer 2:1df0b61d3b5a 189 /** Calibration value */
Michael J. Spencer 2:1df0b61d3b5a 190 #define RTC_CALIBRATION_CALVAL_MASK ((0x1FFFF))
Michael J. Spencer 2:1df0b61d3b5a 191 /** Calibration direction */
Michael J. Spencer 2:1df0b61d3b5a 192 #define RTC_CALIBRATION_LIBDIR ((1<<17))
Michael J. Spencer 2:1df0b61d3b5a 193 /** Calibration max value */
Michael J. Spencer 2:1df0b61d3b5a 194 #define RTC_CALIBRATION_MAX ((0x20000))
Michael J. Spencer 2:1df0b61d3b5a 195 /** Calibration definitions */
Michael J. Spencer 2:1df0b61d3b5a 196 #define RTC_CALIB_DIR_FORWARD ((uint8_t)(0))
Michael J. Spencer 2:1df0b61d3b5a 197 #define RTC_CALIB_DIR_BACKWARD ((uint8_t)(1))
Michael J. Spencer 2:1df0b61d3b5a 198
Michael J. Spencer 2:1df0b61d3b5a 199
Michael J. Spencer 2:1df0b61d3b5a 200 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 201 /** Macro to determine if it is valid RTC peripheral */
Michael J. Spencer 2:1df0b61d3b5a 202 #define PARAM_RTCx(x) (((uint32_t *)x)==((uint32_t *)LPC_RTC))
Michael J. Spencer 2:1df0b61d3b5a 203
Michael J. Spencer 2:1df0b61d3b5a 204 /* Macro check RTC interrupt type */
Michael J. Spencer 2:1df0b61d3b5a 205 #define PARAM_RTC_INT(n) ((n==RTC_INT_COUNTER_INCREASE) || (n==RTC_INT_ALARM))
Michael J. Spencer 2:1df0b61d3b5a 206
Michael J. Spencer 2:1df0b61d3b5a 207 /* Macro check RTC time type */
Michael J. Spencer 2:1df0b61d3b5a 208 #define PARAM_RTC_TIMETYPE(n) ((n==RTC_TIMETYPE_SECOND) || (n==RTC_TIMETYPE_MINUTE) \
Michael J. Spencer 2:1df0b61d3b5a 209 || (n==RTC_TIMETYPE_HOUR) || (n==RTC_TIMETYPE_DAYOFWEEK) \
Michael J. Spencer 2:1df0b61d3b5a 210 || (n==RTC_TIMETYPE_DAYOFMONTH) || (n==RTC_TIMETYPE_DAYOFYEAR) \
Michael J. Spencer 2:1df0b61d3b5a 211 || (n==RTC_TIMETYPE_MONTH) || (n==RTC_TIMETYPE_YEAR))
Michael J. Spencer 2:1df0b61d3b5a 212
Michael J. Spencer 2:1df0b61d3b5a 213 /* Macro check RTC calibration type */
Michael J. Spencer 2:1df0b61d3b5a 214 #define PARAM_RTC_CALIB_DIR(n) ((n==RTC_CALIB_DIR_FORWARD) || (n==RTC_CALIB_DIR_BACKWARD))
Michael J. Spencer 2:1df0b61d3b5a 215
Michael J. Spencer 2:1df0b61d3b5a 216 /* Macro check RTC GPREG type */
Michael J. Spencer 2:1df0b61d3b5a 217 #define PARAM_RTC_GPREG_CH(n) ((n>=0) && (n<=4))
Michael J. Spencer 2:1df0b61d3b5a 218
Michael J. Spencer 2:1df0b61d3b5a 219 /**
Michael J. Spencer 2:1df0b61d3b5a 220 * @}
Michael J. Spencer 2:1df0b61d3b5a 221 */
Michael J. Spencer 2:1df0b61d3b5a 222
Michael J. Spencer 2:1df0b61d3b5a 223
Michael J. Spencer 2:1df0b61d3b5a 224 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 225 /** @defgroup RTC_Public_Types RTC Public Types
Michael J. Spencer 2:1df0b61d3b5a 226 * @{
Michael J. Spencer 2:1df0b61d3b5a 227 */
Michael J. Spencer 2:1df0b61d3b5a 228
Michael J. Spencer 2:1df0b61d3b5a 229 /** @brief Time structure definitions for easy manipulate the data */
Michael J. Spencer 2:1df0b61d3b5a 230 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 231 uint32_t SEC; /*!< Seconds Register */
Michael J. Spencer 2:1df0b61d3b5a 232 uint32_t MIN; /*!< Minutes Register */
Michael J. Spencer 2:1df0b61d3b5a 233 uint32_t HOUR; /*!< Hours Register */
Michael J. Spencer 2:1df0b61d3b5a 234 uint32_t DOM; /*!< Day of Month Register */
Michael J. Spencer 2:1df0b61d3b5a 235 uint32_t DOW; /*!< Day of Week Register */
Michael J. Spencer 2:1df0b61d3b5a 236 uint32_t DOY; /*!< Day of Year Register */
Michael J. Spencer 2:1df0b61d3b5a 237 uint32_t MONTH; /*!< Months Register */
Michael J. Spencer 2:1df0b61d3b5a 238 uint32_t YEAR; /*!< Years Register */
Michael J. Spencer 2:1df0b61d3b5a 239 } RTC_TIME_Type;
Michael J. Spencer 2:1df0b61d3b5a 240
Michael J. Spencer 2:1df0b61d3b5a 241 /** @brief RTC interrupt source */
Michael J. Spencer 2:1df0b61d3b5a 242 typedef enum {
Michael J. Spencer 2:1df0b61d3b5a 243 RTC_INT_COUNTER_INCREASE = RTC_IRL_RTCCIF, /*!< Counter Increment Interrupt */
Michael J. Spencer 2:1df0b61d3b5a 244 RTC_INT_ALARM = RTC_IRL_RTCALF /*!< The alarm interrupt */
Michael J. Spencer 2:1df0b61d3b5a 245 } RTC_INT_OPT;
Michael J. Spencer 2:1df0b61d3b5a 246
Michael J. Spencer 2:1df0b61d3b5a 247
Michael J. Spencer 2:1df0b61d3b5a 248 /** @brief RTC time type option */
Michael J. Spencer 2:1df0b61d3b5a 249 typedef enum {
Michael J. Spencer 2:1df0b61d3b5a 250 RTC_TIMETYPE_SECOND = 0, /*!< Second */
Michael J. Spencer 2:1df0b61d3b5a 251 RTC_TIMETYPE_MINUTE = 1, /*!< Month */
Michael J. Spencer 2:1df0b61d3b5a 252 RTC_TIMETYPE_HOUR = 2, /*!< Hour */
Michael J. Spencer 2:1df0b61d3b5a 253 RTC_TIMETYPE_DAYOFWEEK = 3, /*!< Day of week */
Michael J. Spencer 2:1df0b61d3b5a 254 RTC_TIMETYPE_DAYOFMONTH = 4, /*!< Day of month */
Michael J. Spencer 2:1df0b61d3b5a 255 RTC_TIMETYPE_DAYOFYEAR = 5, /*!< Day of year */
Michael J. Spencer 2:1df0b61d3b5a 256 RTC_TIMETYPE_MONTH = 6, /*!< Month */
Michael J. Spencer 2:1df0b61d3b5a 257 RTC_TIMETYPE_YEAR = 7 /*!< Year */
Michael J. Spencer 2:1df0b61d3b5a 258 } RTC_TIMETYPE_Num;
Michael J. Spencer 2:1df0b61d3b5a 259
Michael J. Spencer 2:1df0b61d3b5a 260 /**
Michael J. Spencer 2:1df0b61d3b5a 261 * @}
Michael J. Spencer 2:1df0b61d3b5a 262 */
Michael J. Spencer 2:1df0b61d3b5a 263
Michael J. Spencer 2:1df0b61d3b5a 264
Michael J. Spencer 2:1df0b61d3b5a 265
Michael J. Spencer 2:1df0b61d3b5a 266 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 267 /** @defgroup RTC_Public_Functions RTC Public Functions
Michael J. Spencer 2:1df0b61d3b5a 268 * @{
Michael J. Spencer 2:1df0b61d3b5a 269 */
Michael J. Spencer 2:1df0b61d3b5a 270
Michael J. Spencer 2:1df0b61d3b5a 271 void RTC_Init (LPC_RTC_TypeDef *RTCx);
Michael J. Spencer 2:1df0b61d3b5a 272 void RTC_DeInit(LPC_RTC_TypeDef *RTCx);
Michael J. Spencer 2:1df0b61d3b5a 273 void RTC_ResetClockTickCounter(LPC_RTC_TypeDef *RTCx);
Michael J. Spencer 2:1df0b61d3b5a 274 void RTC_Cmd (LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 275 void RTC_CntIncrIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t CntIncrIntType, \
Michael J. Spencer 2:1df0b61d3b5a 276 FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 277 void RTC_AlarmIntConfig (LPC_RTC_TypeDef *RTCx, uint32_t AlarmTimeType, \
Michael J. Spencer 2:1df0b61d3b5a 278 FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 279 void RTC_SetTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t TimeValue);
Michael J. Spencer 2:1df0b61d3b5a 280 uint32_t RTC_GetTime(LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
Michael J. Spencer 2:1df0b61d3b5a 281 void RTC_SetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
Michael J. Spencer 2:1df0b61d3b5a 282 void RTC_GetFullTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
Michael J. Spencer 2:1df0b61d3b5a 283 void RTC_SetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype, uint32_t ALValue);
Michael J. Spencer 2:1df0b61d3b5a 284 uint32_t RTC_GetAlarmTime (LPC_RTC_TypeDef *RTCx, uint32_t Timetype);
Michael J. Spencer 2:1df0b61d3b5a 285 void RTC_SetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
Michael J. Spencer 2:1df0b61d3b5a 286 void RTC_GetFullAlarmTime (LPC_RTC_TypeDef *RTCx, RTC_TIME_Type *pFullTime);
Michael J. Spencer 2:1df0b61d3b5a 287 IntStatus RTC_GetIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
Michael J. Spencer 2:1df0b61d3b5a 288 void RTC_ClearIntPending (LPC_RTC_TypeDef *RTCx, uint32_t IntType);
Michael J. Spencer 2:1df0b61d3b5a 289 void RTC_CalibCounterCmd(LPC_RTC_TypeDef *RTCx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 290 void RTC_CalibConfig(LPC_RTC_TypeDef *RTCx, uint32_t CalibValue, uint8_t CalibDir);
Michael J. Spencer 2:1df0b61d3b5a 291 void RTC_WriteGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel, uint32_t Value);
Michael J. Spencer 2:1df0b61d3b5a 292 uint32_t RTC_ReadGPREG (LPC_RTC_TypeDef *RTCx, uint8_t Channel);
Michael J. Spencer 2:1df0b61d3b5a 293
Michael J. Spencer 2:1df0b61d3b5a 294 /**
Michael J. Spencer 2:1df0b61d3b5a 295 * @}
Michael J. Spencer 2:1df0b61d3b5a 296 */
Michael J. Spencer 2:1df0b61d3b5a 297
Michael J. Spencer 2:1df0b61d3b5a 298 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 299 }
Michael J. Spencer 2:1df0b61d3b5a 300 #endif
Michael J. Spencer 2:1df0b61d3b5a 301
Michael J. Spencer 2:1df0b61d3b5a 302 #endif /* LPC17XX_RTC_H_ */
Michael J. Spencer 2:1df0b61d3b5a 303
Michael J. Spencer 2:1df0b61d3b5a 304 /**
Michael J. Spencer 2:1df0b61d3b5a 305 * @}
Michael J. Spencer 2:1df0b61d3b5a 306 */
Michael J. Spencer 2:1df0b61d3b5a 307
Michael J. Spencer 2:1df0b61d3b5a 308 /* --------------------------------- End Of File ------------------------------ */