Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_rit.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_rit.h 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_rit.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for RIT firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup RIT RIT (Repetitive Interrupt Timer)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_RIT_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_RIT_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46
Michael J. Spencer 2:1df0b61d3b5a 47 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 48 /** @defgroup RIT_Private_Macros RIT Private Macros
Michael J. Spencer 2:1df0b61d3b5a 49 * @{
Michael J. Spencer 2:1df0b61d3b5a 50 */
Michael J. Spencer 2:1df0b61d3b5a 51
Michael J. Spencer 2:1df0b61d3b5a 52 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 53 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 54 * Macro defines for RIT control register
Michael J. Spencer 2:1df0b61d3b5a 55 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 56 /** Set interrupt flag when the counter value equals the masked compare value */
Michael J. Spencer 2:1df0b61d3b5a 57 #define RIT_CTRL_INTEN ((uint32_t) (1))
Michael J. Spencer 2:1df0b61d3b5a 58 /** Set timer enable clear to 0 when the counter value equals the masked compare value */
Michael J. Spencer 2:1df0b61d3b5a 59 #define RIT_CTRL_ENCLR ((uint32_t) _BIT(1))
Michael J. Spencer 2:1df0b61d3b5a 60 /** Set timer enable on debug */
Michael J. Spencer 2:1df0b61d3b5a 61 #define RIT_CTRL_ENBR ((uint32_t) _BIT(2))
Michael J. Spencer 2:1df0b61d3b5a 62 /** Set timer enable */
Michael J. Spencer 2:1df0b61d3b5a 63 #define RIT_CTRL_TEN ((uint32_t) _BIT(3))
Michael J. Spencer 2:1df0b61d3b5a 64
Michael J. Spencer 2:1df0b61d3b5a 65 /** Macro to determine if it is valid RIT peripheral */
Michael J. Spencer 2:1df0b61d3b5a 66 #define PARAM_RITx(n) (((uint32_t *)n)==((uint32_t *)LPC_RIT))
Michael J. Spencer 2:1df0b61d3b5a 67 /**
Michael J. Spencer 2:1df0b61d3b5a 68 * @}
Michael J. Spencer 2:1df0b61d3b5a 69 */
Michael J. Spencer 2:1df0b61d3b5a 70
Michael J. Spencer 2:1df0b61d3b5a 71
Michael J. Spencer 2:1df0b61d3b5a 72
Michael J. Spencer 2:1df0b61d3b5a 73 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 74 /** @defgroup RIT_Public_Functions RIT Public Functions
Michael J. Spencer 2:1df0b61d3b5a 75 * @{
Michael J. Spencer 2:1df0b61d3b5a 76 */
Michael J. Spencer 2:1df0b61d3b5a 77 /* RIT Init/DeInit functions */
Michael J. Spencer 2:1df0b61d3b5a 78 void RIT_Init(LPC_RIT_TypeDef *RITx);
Michael J. Spencer 2:1df0b61d3b5a 79 void RIT_DeInit(LPC_RIT_TypeDef *RITx);
Michael J. Spencer 2:1df0b61d3b5a 80
Michael J. Spencer 2:1df0b61d3b5a 81 /* RIT config timer functions */
Michael J. Spencer 2:1df0b61d3b5a 82 void RIT_TimerConfig(LPC_RIT_TypeDef *RITx, uint32_t time_interval);
Michael J. Spencer 2:1df0b61d3b5a 83
Michael J. Spencer 2:1df0b61d3b5a 84 /* Enable/Disable RIT functions */
Michael J. Spencer 2:1df0b61d3b5a 85 void RIT_TimerClearCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 86 void RIT_Cmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 87 void RIT_TimerDebugCmd(LPC_RIT_TypeDef *RITx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 88
Michael J. Spencer 2:1df0b61d3b5a 89 /* RIT Interrupt functions */
Michael J. Spencer 2:1df0b61d3b5a 90 IntStatus RIT_GetIntStatus(LPC_RIT_TypeDef *RITx);
Michael J. Spencer 2:1df0b61d3b5a 91
Michael J. Spencer 2:1df0b61d3b5a 92 /**
Michael J. Spencer 2:1df0b61d3b5a 93 * @}
Michael J. Spencer 2:1df0b61d3b5a 94 */
Michael J. Spencer 2:1df0b61d3b5a 95
Michael J. Spencer 2:1df0b61d3b5a 96 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 97 }
Michael J. Spencer 2:1df0b61d3b5a 98 #endif
Michael J. Spencer 2:1df0b61d3b5a 99
Michael J. Spencer 2:1df0b61d3b5a 100 #endif /* LPC17XX_RIT_H_ */
Michael J. Spencer 2:1df0b61d3b5a 101
Michael J. Spencer 2:1df0b61d3b5a 102 /**
Michael J. Spencer 2:1df0b61d3b5a 103 * @}
Michael J. Spencer 2:1df0b61d3b5a 104 */
Michael J. Spencer 2:1df0b61d3b5a 105
Michael J. Spencer 2:1df0b61d3b5a 106 /* --------------------------------- End Of File ------------------------------ */