Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_qei.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_qei.h 2010-05-21 |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_qei.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for QEI firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 21. May. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup QEI QEI (Quadrature Encoder Interface) |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_QEI_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_QEI_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | /* Public Macros -------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | /** @defgroup QEI_Public_Macros QEI Public Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | /* QEI Reset types */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | /* QEI Direction Invert Type Option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | /* QEI Signal Mode Option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | /* QEI Capture Mode Option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | /* QEI Invert Index Signal Option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | /* QEI timer reload option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | /* QEI Flag Status type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | /* QEI Compare Position channel option */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | /* QEI interrupt flag type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | current position interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | current position interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | current position interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | index count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | /* Private Macros ------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | /** @defgroup QEI_Private_Macros QEI Private Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | /* Quadrature Encoder Interface Control Register Definition --------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | * Macro defines for QEI Control register |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | * Macro defines for QEI Configuration register |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | * Macro defines for QEI Status register |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | * Macro defines for QEI Interrupt Status register |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | both the POS0_Int bit is set and the REV_Int is set */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | both the POS1_Int bit is set and the REV_Int is set */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | both the POS2_Int bit is set and the REV_Int is set */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | * Macro defines for QEI Interrupt Set register |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | * Macro defines for QEI Interrupt Clear register |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | * Macro defines for QEI Interrupt Enable register |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | * Macro defines for QEI Interrupt Enable Set register |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | * Macro defines for QEI Interrupt Enable Clear register |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | current position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | index count */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | /* Macro check QEI peripheral */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | #define PARAM_QEIx(n) ((n==LPC_QEI)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | /* Macro check QEI reset type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | #define PARAM_QEI_RESET(n) ((n==QEI_CON_RESP) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | || (n==QEI_RESET_POSOnIDX) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | || (n==QEI_RESET_VEL) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | || (n==QEI_RESET_IDX)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | /* Macro check QEI Direction invert mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | #define PARAM_QEI_DIRINV(n) ((n==QEI_DIRINV_NONE) || (n==QEI_DIRINV_CMPL)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | /* Macro check QEI signal mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | #define PARAM_QEI_SIGNALMODE(n) ((n==QEI_SIGNALMODE_QUAD) || (n==QEI_SIGNALMODE_CLKDIR)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | /* Macro check QEI Capture mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | #define PARAM_QEI_CAPMODE(n) ((n==QEI_CAPMODE_2X) || (n==QEI_CAPMODE_4X)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | /* Macro check QEI Invert index mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | #define PARAM_QEI_INVINX(n) ((n==QEI_INVINX_NONE) || (n==QEI_INVINX_EN)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | /* Macro check QEI Direction invert mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | #define PARAM_QEI_TIMERRELOAD(n) ((n==QEI_TIMERRELOAD_TICKVAL) || (n==QEI_TIMERRELOAD_USVAL)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | /* Macro check QEI status type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | #define PARAM_QEI_STATUS(n) ((n==QEI_STATUS_DIR)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | /* Macro check QEI combine position type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | #define PARAM_QEI_COMPPOS_CH(n) ((n==QEI_COMPPOS_CH_0) || (n==QEI_COMPPOS_CH_1) || (n==QEI_COMPPOS_CH_2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | /* Macro check QEI interrupt flag type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | #define PARAM_QEI_INTFLAG(n) ((n==QEI_INTFLAG_INX_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | || (n==QEI_INTFLAG_TIM_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | || (n==QEI_INTFLAG_VELC_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | || (n==QEI_INTFLAG_DIR_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | || (n==QEI_INTFLAG_ERR_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | || (n==QEI_INTFLAG_ENCLK_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | || (n==QEI_INTFLAG_POS0_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | || (n==QEI_INTFLAG_POS1_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | || (n==QEI_INTFLAG_POS2_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | || (n==QEI_INTFLAG_REV_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | || (n==QEI_INTFLAG_POS0REV_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | || (n==QEI_INTFLAG_POS1REV_Int) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | || (n==QEI_INTFLAG_POS2REV_Int)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | /* Public Types --------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | /** @defgroup QEI_Public_Types QEI Public Types |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | * @brief QEI Configuration structure type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | uint32_t DirectionInvert :1; /**< Direction invert option: |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | - QEI_DIRINV_NONE: QEI Direction is normal |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | - QEI_DIRINV_CMPL: QEI Direction is complemented |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | uint32_t SignalMode :1; /**< Signal mode Option: |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | - QEI_SIGNALMODE_QUAD: Signal is in Quadrature phase mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | - QEI_SIGNALMODE_CLKDIR: Signal is in Clock/Direction mode |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | uint32_t CaptureMode :1; /**< Capture Mode Option: |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | - QEI_CAPMODE_2X: Only Phase-A edges are counted (2X) |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | - QEI_CAPMODE_4X: BOTH Phase-A and Phase-B edges are counted (4X) |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | uint32_t InvertIndex :1; /**< Invert Index Option: |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | - QEI_INVINX_NONE: the sense of the index input is normal |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | - QEI_INVINX_EN: inverts the sense of the index input |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | } QEI_CFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | * @brief Timer Reload Configuration structure type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | uint8_t ReloadOption; /**< Velocity Timer Reload Option, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | - QEI_TIMERRELOAD_TICKVAL: Reload value in absolute value |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | - QEI_TIMERRELOAD_USVAL: Reload value in microsecond value |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | uint8_t Reserved[3]; |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | uint32_t ReloadValue; /**< Velocity Timer Reload Value, 32-bit long, should be matched |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | with Velocity Timer Reload Option |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | } QEI_RELOADCFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | /** @defgroup QEI_Public_Functions QEI Public Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | void QEI_Reset(LPC_QEI_TypeDef *QEIx, uint32_t ulResetType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | void QEI_Init(LPC_QEI_TypeDef *QEIx, QEI_CFG_Type *QEI_ConfigStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | void QEI_ConfigStructInit(QEI_CFG_Type *QIE_InitStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | void QEI_DeInit(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | FlagStatus QEI_GetStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulFlagType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | uint32_t QEI_GetPosition(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | void QEI_SetMaxPosition(LPC_QEI_TypeDef *QEIx, uint32_t ulMaxPos); |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | void QEI_SetPositionComp(LPC_QEI_TypeDef *QEIx, uint8_t bPosCompCh, uint32_t ulPosComp); |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | uint32_t QEI_GetIndex(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | void QEI_SetIndexComp(LPC_QEI_TypeDef *QEIx, uint32_t ulIndexComp); |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | void QEI_SetTimerReload(LPC_QEI_TypeDef *QEIx, QEI_RELOADCFG_Type *QEIReloadStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | uint32_t QEI_GetTimer(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | uint32_t QEI_GetVelocity(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | uint32_t QEI_GetVelocityCap(LPC_QEI_TypeDef *QEIx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | void QEI_SetVelocityComp(LPC_QEI_TypeDef *QEIx, uint32_t ulVelComp); |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | void QEI_SetDigiFilter(LPC_QEI_TypeDef *QEIx, uint32_t ulSamplingPulse); |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | FlagStatus QEI_GetIntStatus(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | void QEI_IntCmd(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | void QEI_IntSet(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | void QEI_IntClear(LPC_QEI_TypeDef *QEIx, uint32_t ulIntType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 401 | uint32_t QEI_CalculateRPM(LPC_QEI_TypeDef *QEIx, uint32_t ulVelCapValue, uint32_t ulPPR); |
| Michael J. Spencer |
2:1df0b61d3b5a | 402 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 403 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 404 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 405 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 406 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 407 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 408 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 409 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 410 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 411 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 412 | #endif /* LPC17XX_QEI_H_ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 413 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 414 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 415 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 416 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 417 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 418 | /* --------------------------------- End Of File ------------------------------ */ |