Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_i2c.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_i2c.h 2010-05-21 |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_i2c.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for I2C firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 21. May. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup I2C I2C (Inter-IC Control bus) |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_I2C_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_I2C_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | extern "C" |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | /* Private Macros ------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | /** @defgroup I2C_Private_Macros I2C Private Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | /*******************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | * I2C Control Set register description |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | #define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | #define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | #define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | #define I2C_I2CONSET_STA ((0x20)) /*!< START flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | #define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | /*******************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | * I2C Control Clear register description |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | /** Assert acknowledge Clear bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define I2C_I2CONCLR_AAC ((1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | /** I2C interrupt Clear bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | #define I2C_I2CONCLR_SIC ((1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | /** START flag Clear bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | #define I2C_I2CONCLR_STAC ((1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | /** I2C interface Disable bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | #define I2C_I2CONCLR_I2ENC ((1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | * I2C Status Code definition (I2C Status register) |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | /* Return Code in I2C status register */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define I2C_STAT_CODE_BITMASK ((0xF8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | /* I2C return status code definitions ----------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | /** No relevant information */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | #define I2C_I2STAT_NO_INF ((0xF8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | /* Master transmit mode -------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | /** A start condition has been transmitted */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | #define I2C_I2STAT_M_TX_START ((0x08)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | /** A repeat start condition has been transmitted */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | #define I2C_I2STAT_M_TX_RESTART ((0x10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | /** SLA+W has been transmitted, ACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | /** SLA+W has been transmitted, NACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | /** Data has been transmitted, ACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | #define I2C_I2STAT_M_TX_DAT_ACK ((0x28)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | /** Data has been transmitted, NACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | #define I2C_I2STAT_M_TX_DAT_NACK ((0x30)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | /** Arbitration lost in SLA+R/W or Data bytes */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | #define I2C_I2STAT_M_TX_ARB_LOST ((0x38)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | /* Master receive mode -------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | /** A start condition has been transmitted */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | #define I2C_I2STAT_M_RX_START ((0x08)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | /** A repeat start condition has been transmitted */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | #define I2C_I2STAT_M_RX_RESTART ((0x10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | /** Arbitration lost */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | #define I2C_I2STAT_M_RX_ARB_LOST ((0x38)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | /** SLA+R has been transmitted, ACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | /** SLA+R has been transmitted, NACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | /** Data has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | #define I2C_I2STAT_M_RX_DAT_ACK ((0x50)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | /** Data has been received, NACK has been return */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | #define I2C_I2STAT_M_RX_DAT_NACK ((0x58)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | /* Slave receive mode -------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | /** Own slave address has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | /** Arbitration lost in SLA+R/W as master */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | /** Own SLA+W has been received, ACK returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | //#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | /** General call address has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | /** Arbitration lost in SLA+R/W (GENERAL CALL) as master */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | /** General call address has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | //#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | /** Previously addressed with own SLV address; |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | * Data has been received, ACK has been return */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | /** Previously addressed with own SLA; |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | * Data has been received and NOT ACK has been return */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | /** Previously addressed with General Call; |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | * Data has been received and ACK has been return */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | /** Previously addressed with General Call; |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | * Data has been received and NOT ACK has been return */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | /** A STOP condition or repeated START condition has |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | * been received while still addressed as SLV/REC |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | * (Slave Receive) or SLV/TRX (Slave Transmit) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | /** Slave transmit mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | /** Own SLA+R has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | /** Arbitration lost in SLA+R/W as master */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | /** Own SLA+R has been received, ACK has been returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | //#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | /** Data has been transmitted, ACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | /** Data has been transmitted, NACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | /** Last data byte in I2DAT has been transmitted (AA = 0); |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | ACK has been received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | /** Time out in case of using I2C slave mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | #define I2C_SLAVE_TIME_OUT 0x10000UL |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | * I2C Data register definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | /** Mask for I2DAT register*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | #define I2C_I2DAT_BITMASK ((0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | /** Idle data value will be send out in slave mode in case of the actual |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | * expecting data requested from the master is greater than its sending data |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | * length that can be supported */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | #define I2C_I2DAT_IDLE_CHAR (0xFF) |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | * I2C Monitor mode control register description |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | #define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | #define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | #define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | #define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | * I2C Data buffer register description |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | /** I2C Data buffer register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | #define I2DATA_BUFFER_BITMASK ((0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | * I2C Slave Address registers definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | /** General Call enable bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | #define I2C_I2ADR_GC ((1<<0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | /** I2C Slave Address registers bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | #define I2C_I2ADR_BITMASK ((0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | * I2C Mask Register definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | /** I2C Mask Register mask field */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | #define I2C_I2MASK_MASK(n) ((n&0xFE)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | * I2C SCL HIGH duty cycle Register definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | /** I2C SCL HIGH duty cycle Register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | #define I2C_I2SCLH_BITMASK ((0xFFFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | /********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | * I2C SCL LOW duty cycle Register definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | *********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | /** I2C SCL LOW duty cycle Register bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | #define I2C_I2SCLL_BITMASK ((0xFFFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | /* I2C status values */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | #define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | #define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | #define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | * I2C monitor control configuration defines |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | /* Macros check I2C slave address */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | #define PARAM_I2C_SLAVEADDR_CH(n) ((n>=0) && (n<=3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | /** Macro to determine if it is valid SSP port number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | #define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | || (((uint32_t *)n)==((uint32_t *)LPC_I2C2))) |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | /* Macros check I2C monitor configuration type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | /* Public Types --------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | /** @defgroup I2C_Public_Types I2C Public Types |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | * @brief I2C Own slave address setting structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control, |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | should be in range from 0..3 |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | when I2C control being in Slave mode, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | - ENABLE: Enable General Call function. |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | - DISABLE: Disable General Call function. |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1) |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | which is set to '1' will cause an automatic compare on |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | the corresponding bit of the received address when it |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | is compared to the SlaveAddr_7bit value associated with this |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | mask register. In other words, bits in SlaveAddr_7bit value |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | which are masked are not taken into account in determining |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | an address match |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | } I2C_OWNSLAVEADDR_CFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | * @brief Master transfer setup data structure definitions |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | uint32_t sl_addr7bit; /**< Slave address in 7bit mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | is not used */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | uint32_t tx_length; /**< Transmit data length - 0 if data transmit |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | is not used*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | uint32_t tx_count; /**< Current Transmit data counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | is not used */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | uint32_t rx_length; /**< Receive data length - 0 if data receive is |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | not used */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | uint32_t rx_count; /**< Current Receive data counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | uint32_t retransmissions_max; /**< Max Re-Transmission value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | uint32_t retransmissions_count; /**< Current Re-Transmission counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | uint32_t status; /**< Current status of I2C activity */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | void (*callback)(void); /**< Pointer to Call back function when transmission complete |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | used in interrupt transfer mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | } I2C_M_SETUP_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | * @brief Slave transfer setup data structure definitions |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | typedef struct |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | uint8_t* tx_data; |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | uint32_t tx_length; |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | uint32_t tx_count; |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | uint8_t* rx_data; |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | uint32_t rx_length; |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | uint32_t rx_count; |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | uint32_t status; |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | void (*callback)(void); |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | } I2C_S_SETUP_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | * @brief Transfer option type definitions |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | } I2C_TRANSFER_OPT_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | /** @defgroup I2C_Public_Functions I2C Public Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | /* I2C Init/DeInit functions ---------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate); |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | void I2C_DeInit(LPC_I2C_TypeDef* I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | //void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock); |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | /* I2C transfer data functions -------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt); |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct); |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | /* I2C Monitor functions ---------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size); |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | /* I2C Interrupt handler functions ------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | #endif /* LPC17XX_I2C_H_ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | /* --------------------------------- End Of File ------------------------------ */ |