Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_gpdma.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_gpdma.h 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_gpdma.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for GPDMA firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_GPDMA_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_GPDMA_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46 /* Public Macros -------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 47 /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
Michael J. Spencer 2:1df0b61d3b5a 48 * @{
Michael J. Spencer 2:1df0b61d3b5a 49 */
Michael J. Spencer 2:1df0b61d3b5a 50
Michael J. Spencer 2:1df0b61d3b5a 51 /** DMA Connection number definitions */
Michael J. Spencer 2:1df0b61d3b5a 52 #define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
Michael J. Spencer 2:1df0b61d3b5a 53 #define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
Michael J. Spencer 2:1df0b61d3b5a 54 #define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
Michael J. Spencer 2:1df0b61d3b5a 55 #define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
Michael J. Spencer 2:1df0b61d3b5a 56 #define GPDMA_CONN_ADC ((4UL)) /**< ADC */
Michael J. Spencer 2:1df0b61d3b5a 57 #define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
Michael J. Spencer 2:1df0b61d3b5a 58 #define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
Michael J. Spencer 2:1df0b61d3b5a 59 #define GPDMA_CONN_DAC ((7UL)) /**< DAC */
Michael J. Spencer 2:1df0b61d3b5a 60 #define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
Michael J. Spencer 2:1df0b61d3b5a 61 #define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
Michael J. Spencer 2:1df0b61d3b5a 62 #define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
Michael J. Spencer 2:1df0b61d3b5a 63 #define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
Michael J. Spencer 2:1df0b61d3b5a 64 #define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
Michael J. Spencer 2:1df0b61d3b5a 65 #define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
Michael J. Spencer 2:1df0b61d3b5a 66 #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
Michael J. Spencer 2:1df0b61d3b5a 67 #define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
Michael J. Spencer 2:1df0b61d3b5a 68 #define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
Michael J. Spencer 2:1df0b61d3b5a 69 #define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
Michael J. Spencer 2:1df0b61d3b5a 70 #define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
Michael J. Spencer 2:1df0b61d3b5a 71 #define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
Michael J. Spencer 2:1df0b61d3b5a 72 #define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
Michael J. Spencer 2:1df0b61d3b5a 73 #define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
Michael J. Spencer 2:1df0b61d3b5a 74 #define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
Michael J. Spencer 2:1df0b61d3b5a 75 #define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
Michael J. Spencer 2:1df0b61d3b5a 76
Michael J. Spencer 2:1df0b61d3b5a 77 /** GPDMA Transfer type definitions */
Michael J. Spencer 2:1df0b61d3b5a 78 #define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
Michael J. Spencer 2:1df0b61d3b5a 79 #define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
Michael J. Spencer 2:1df0b61d3b5a 80 #define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
Michael J. Spencer 2:1df0b61d3b5a 81 #define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
Michael J. Spencer 2:1df0b61d3b5a 82
Michael J. Spencer 2:1df0b61d3b5a 83 /** Burst size in Source and Destination definitions */
Michael J. Spencer 2:1df0b61d3b5a 84 #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
Michael J. Spencer 2:1df0b61d3b5a 85 #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
Michael J. Spencer 2:1df0b61d3b5a 86 #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
Michael J. Spencer 2:1df0b61d3b5a 87 #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
Michael J. Spencer 2:1df0b61d3b5a 88 #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
Michael J. Spencer 2:1df0b61d3b5a 89 #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
Michael J. Spencer 2:1df0b61d3b5a 90 #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
Michael J. Spencer 2:1df0b61d3b5a 91 #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
Michael J. Spencer 2:1df0b61d3b5a 92
Michael J. Spencer 2:1df0b61d3b5a 93 /** Width in Source transfer width and Destination transfer width definitions */
Michael J. Spencer 2:1df0b61d3b5a 94 #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
Michael J. Spencer 2:1df0b61d3b5a 95 #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
Michael J. Spencer 2:1df0b61d3b5a 96 #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
Michael J. Spencer 2:1df0b61d3b5a 97
Michael J. Spencer 2:1df0b61d3b5a 98 /** DMA Request Select Mode definitions */
Michael J. Spencer 2:1df0b61d3b5a 99 #define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
Michael J. Spencer 2:1df0b61d3b5a 100 #define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
Michael J. Spencer 2:1df0b61d3b5a 101
Michael J. Spencer 2:1df0b61d3b5a 102 /**
Michael J. Spencer 2:1df0b61d3b5a 103 * @}
Michael J. Spencer 2:1df0b61d3b5a 104 */
Michael J. Spencer 2:1df0b61d3b5a 105
Michael J. Spencer 2:1df0b61d3b5a 106
Michael J. Spencer 2:1df0b61d3b5a 107 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 108 /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
Michael J. Spencer 2:1df0b61d3b5a 109 * @{
Michael J. Spencer 2:1df0b61d3b5a 110 */
Michael J. Spencer 2:1df0b61d3b5a 111
Michael J. Spencer 2:1df0b61d3b5a 112 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 113 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 114 * Macro defines for DMA Interrupt Status register
Michael J. Spencer 2:1df0b61d3b5a 115 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 116 #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 117 #define GPDMA_DMACIntStat_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 118
Michael J. Spencer 2:1df0b61d3b5a 119 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 120 * Macro defines for DMA Interrupt Terminal Count Request Status register
Michael J. Spencer 2:1df0b61d3b5a 121 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 122 #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 123 #define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 124
Michael J. Spencer 2:1df0b61d3b5a 125 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 126 * Macro defines for DMA Interrupt Terminal Count Request Clear register
Michael J. Spencer 2:1df0b61d3b5a 127 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 128 #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 129 #define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 130
Michael J. Spencer 2:1df0b61d3b5a 131 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 132 * Macro defines for DMA Interrupt Error Status register
Michael J. Spencer 2:1df0b61d3b5a 133 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 134 #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 135 #define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 136
Michael J. Spencer 2:1df0b61d3b5a 137 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 138 * Macro defines for DMA Interrupt Error Clear register
Michael J. Spencer 2:1df0b61d3b5a 139 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 140 #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 141 #define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 142
Michael J. Spencer 2:1df0b61d3b5a 143 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 144 * Macro defines for DMA Raw Interrupt Terminal Count Status register
Michael J. Spencer 2:1df0b61d3b5a 145 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 146 #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 147 #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 148
Michael J. Spencer 2:1df0b61d3b5a 149 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 150 * Macro defines for DMA Raw Error Interrupt Status register
Michael J. Spencer 2:1df0b61d3b5a 151 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 152 #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 153 #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 154
Michael J. Spencer 2:1df0b61d3b5a 155 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 156 * Macro defines for DMA Enabled Channel register
Michael J. Spencer 2:1df0b61d3b5a 157 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 158 #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 159 #define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 160
Michael J. Spencer 2:1df0b61d3b5a 161 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 162 * Macro defines for DMA Software Burst Request register
Michael J. Spencer 2:1df0b61d3b5a 163 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 164 #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 165 #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 166
Michael J. Spencer 2:1df0b61d3b5a 167 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 168 * Macro defines for DMA Software Single Request register
Michael J. Spencer 2:1df0b61d3b5a 169 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 170 #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 171 #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 172
Michael J. Spencer 2:1df0b61d3b5a 173 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 174 * Macro defines for DMA Software Last Burst Request register
Michael J. Spencer 2:1df0b61d3b5a 175 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 176 #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 177 #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 178
Michael J. Spencer 2:1df0b61d3b5a 179 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 180 * Macro defines for DMA Software Last Single Request register
Michael J. Spencer 2:1df0b61d3b5a 181 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 182 #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 183 #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 184
Michael J. Spencer 2:1df0b61d3b5a 185 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 186 * Macro defines for DMA Configuration register
Michael J. Spencer 2:1df0b61d3b5a 187 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 188 #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
Michael J. Spencer 2:1df0b61d3b5a 189 #define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
Michael J. Spencer 2:1df0b61d3b5a 190 #define GPDMA_DMACConfig_BITMASK ((0x03))
Michael J. Spencer 2:1df0b61d3b5a 191
Michael J. Spencer 2:1df0b61d3b5a 192 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 193 * Macro defines for DMA Synchronization register
Michael J. Spencer 2:1df0b61d3b5a 194 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 195 #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 196 #define GPDMA_DMACSync_BITMASK ((0xFFFF))
Michael J. Spencer 2:1df0b61d3b5a 197
Michael J. Spencer 2:1df0b61d3b5a 198 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 199 * Macro defines for DMA Request Select register
Michael J. Spencer 2:1df0b61d3b5a 200 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 201 #define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 202 #define GPDMA_DMAReqSel_BITMASK ((0xFF))
Michael J. Spencer 2:1df0b61d3b5a 203
Michael J. Spencer 2:1df0b61d3b5a 204 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 205 * Macro defines for DMA Channel Linked List Item registers
Michael J. Spencer 2:1df0b61d3b5a 206 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 207 /** DMA Channel Linked List Item registers bit mask*/
Michael J. Spencer 2:1df0b61d3b5a 208 #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
Michael J. Spencer 2:1df0b61d3b5a 209
Michael J. Spencer 2:1df0b61d3b5a 210 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 211 * Macro defines for DMA channel control registers
Michael J. Spencer 2:1df0b61d3b5a 212 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 213 #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
Michael J. Spencer 2:1df0b61d3b5a 214 #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
Michael J. Spencer 2:1df0b61d3b5a 215 #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
Michael J. Spencer 2:1df0b61d3b5a 216 #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
Michael J. Spencer 2:1df0b61d3b5a 217 #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
Michael J. Spencer 2:1df0b61d3b5a 218 #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
Michael J. Spencer 2:1df0b61d3b5a 219 #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
Michael J. Spencer 2:1df0b61d3b5a 220 #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
Michael J. Spencer 2:1df0b61d3b5a 221 #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
Michael J. Spencer 2:1df0b61d3b5a 222 #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
Michael J. Spencer 2:1df0b61d3b5a 223 #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
Michael J. Spencer 2:1df0b61d3b5a 224 /** DMA channel control registers bit mask */
Michael J. Spencer 2:1df0b61d3b5a 225 #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
Michael J. Spencer 2:1df0b61d3b5a 226
Michael J. Spencer 2:1df0b61d3b5a 227 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 228 * Macro defines for DMA Channel Configuration registers
Michael J. Spencer 2:1df0b61d3b5a 229 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 230 #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
Michael J. Spencer 2:1df0b61d3b5a 231 #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
Michael J. Spencer 2:1df0b61d3b5a 232 #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
Michael J. Spencer 2:1df0b61d3b5a 233 #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
Michael J. Spencer 2:1df0b61d3b5a 234 #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
Michael J. Spencer 2:1df0b61d3b5a 235 #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
Michael J. Spencer 2:1df0b61d3b5a 236 #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
Michael J. Spencer 2:1df0b61d3b5a 237 #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
Michael J. Spencer 2:1df0b61d3b5a 238 #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
Michael J. Spencer 2:1df0b61d3b5a 239 /** DMA Channel Configuration registers bit mask */
Michael J. Spencer 2:1df0b61d3b5a 240 #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
Michael J. Spencer 2:1df0b61d3b5a 241
Michael J. Spencer 2:1df0b61d3b5a 242 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 243 /* Macros check GPDMA channel */
Michael J. Spencer 2:1df0b61d3b5a 244 #define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
Michael J. Spencer 2:1df0b61d3b5a 245
Michael J. Spencer 2:1df0b61d3b5a 246 /* Macros check GPDMA connection type */
Michael J. Spencer 2:1df0b61d3b5a 247 #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 248 || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 249 || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
Michael J. Spencer 2:1df0b61d3b5a 250 || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
Michael J. Spencer 2:1df0b61d3b5a 251 || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 252 || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 253 || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 254 || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
Michael J. Spencer 2:1df0b61d3b5a 255 || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
Michael J. Spencer 2:1df0b61d3b5a 256 || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
Michael J. Spencer 2:1df0b61d3b5a 257 || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
Michael J. Spencer 2:1df0b61d3b5a 258 || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
Michael J. Spencer 2:1df0b61d3b5a 259
Michael J. Spencer 2:1df0b61d3b5a 260 /* Macros check GPDMA burst size type */
Michael J. Spencer 2:1df0b61d3b5a 261 #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
Michael J. Spencer 2:1df0b61d3b5a 262 || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
Michael J. Spencer 2:1df0b61d3b5a 263 || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
Michael J. Spencer 2:1df0b61d3b5a 264 || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
Michael J. Spencer 2:1df0b61d3b5a 265
Michael J. Spencer 2:1df0b61d3b5a 266 /* Macros check GPDMA width type */
Michael J. Spencer 2:1df0b61d3b5a 267 #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
Michael J. Spencer 2:1df0b61d3b5a 268 || (n==GPDMA_WIDTH_WORD))
Michael J. Spencer 2:1df0b61d3b5a 269
Michael J. Spencer 2:1df0b61d3b5a 270 /* Macros check GPDMA status type */
Michael J. Spencer 2:1df0b61d3b5a 271 #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
Michael J. Spencer 2:1df0b61d3b5a 272 || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
Michael J. Spencer 2:1df0b61d3b5a 273 || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
Michael J. Spencer 2:1df0b61d3b5a 274
Michael J. Spencer 2:1df0b61d3b5a 275 /* Macros check GPDMA transfer type */
Michael J. Spencer 2:1df0b61d3b5a 276 #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
Michael J. Spencer 2:1df0b61d3b5a 277 ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
Michael J. Spencer 2:1df0b61d3b5a 278
Michael J. Spencer 2:1df0b61d3b5a 279 /* Macros check GPDMA state clear type */
Michael J. Spencer 2:1df0b61d3b5a 280 #define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
Michael J. Spencer 2:1df0b61d3b5a 281
Michael J. Spencer 2:1df0b61d3b5a 282 /* Macros check GPDMA request select type */
Michael J. Spencer 2:1df0b61d3b5a 283 #define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
Michael J. Spencer 2:1df0b61d3b5a 284 /**
Michael J. Spencer 2:1df0b61d3b5a 285 * @}
Michael J. Spencer 2:1df0b61d3b5a 286 */
Michael J. Spencer 2:1df0b61d3b5a 287
Michael J. Spencer 2:1df0b61d3b5a 288
Michael J. Spencer 2:1df0b61d3b5a 289 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 290 /** @defgroup GPDMA_Public_Types GPDMA Public Types
Michael J. Spencer 2:1df0b61d3b5a 291 * @{
Michael J. Spencer 2:1df0b61d3b5a 292 */
Michael J. Spencer 2:1df0b61d3b5a 293
Michael J. Spencer 2:1df0b61d3b5a 294 /**
Michael J. Spencer 2:1df0b61d3b5a 295 * @brief GPDMA Status enumeration
Michael J. Spencer 2:1df0b61d3b5a 296 */
Michael J. Spencer 2:1df0b61d3b5a 297 typedef enum {
Michael J. Spencer 2:1df0b61d3b5a 298 GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
Michael J. Spencer 2:1df0b61d3b5a 299 GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
Michael J. Spencer 2:1df0b61d3b5a 300 GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
Michael J. Spencer 2:1df0b61d3b5a 301 GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
Michael J. Spencer 2:1df0b61d3b5a 302 GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
Michael J. Spencer 2:1df0b61d3b5a 303 GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
Michael J. Spencer 2:1df0b61d3b5a 304 } GPDMA_Status_Type;
Michael J. Spencer 2:1df0b61d3b5a 305
Michael J. Spencer 2:1df0b61d3b5a 306 /**
Michael J. Spencer 2:1df0b61d3b5a 307 * @brief GPDMA Interrupt clear status enumeration
Michael J. Spencer 2:1df0b61d3b5a 308 */
Michael J. Spencer 2:1df0b61d3b5a 309 typedef enum{
Michael J. Spencer 2:1df0b61d3b5a 310 GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
Michael J. Spencer 2:1df0b61d3b5a 311 GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
Michael J. Spencer 2:1df0b61d3b5a 312 }GPDMA_StateClear_Type;
Michael J. Spencer 2:1df0b61d3b5a 313
Michael J. Spencer 2:1df0b61d3b5a 314 /**
Michael J. Spencer 2:1df0b61d3b5a 315 * @brief GPDMA Channel configuration structure type definition
Michael J. Spencer 2:1df0b61d3b5a 316 */
Michael J. Spencer 2:1df0b61d3b5a 317 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 318 uint32_t ChannelNum; /**< DMA channel number, should be in
Michael J. Spencer 2:1df0b61d3b5a 319 range from 0 to 7.
Michael J. Spencer 2:1df0b61d3b5a 320 Note: DMA channel 0 has the highest priority
Michael J. Spencer 2:1df0b61d3b5a 321 and DMA channel 7 the lowest priority.
Michael J. Spencer 2:1df0b61d3b5a 322 */
Michael J. Spencer 2:1df0b61d3b5a 323 uint32_t TransferSize; /**< Length/Size of transfer */
Michael J. Spencer 2:1df0b61d3b5a 324 uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
Michael J. Spencer 2:1df0b61d3b5a 325 uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
Michael J. Spencer 2:1df0b61d3b5a 326 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
Michael J. Spencer 2:1df0b61d3b5a 327 uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
Michael J. Spencer 2:1df0b61d3b5a 328 GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
Michael J. Spencer 2:1df0b61d3b5a 329 uint32_t TransferType; /**< Transfer Type, should be one of the following:
Michael J. Spencer 2:1df0b61d3b5a 330 - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
Michael J. Spencer 2:1df0b61d3b5a 331 - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
Michael J. Spencer 2:1df0b61d3b5a 332 - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
Michael J. Spencer 2:1df0b61d3b5a 333 - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
Michael J. Spencer 2:1df0b61d3b5a 334 */
Michael J. Spencer 2:1df0b61d3b5a 335 uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
Michael J. Spencer 2:1df0b61d3b5a 336 GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
Michael J. Spencer 2:1df0b61d3b5a 337 following:
Michael J. Spencer 2:1df0b61d3b5a 338 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
Michael J. Spencer 2:1df0b61d3b5a 339 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
Michael J. Spencer 2:1df0b61d3b5a 340 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
Michael J. Spencer 2:1df0b61d3b5a 341 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
Michael J. Spencer 2:1df0b61d3b5a 342 - GPDMA_CONN_ADC: ADC
Michael J. Spencer 2:1df0b61d3b5a 343 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
Michael J. Spencer 2:1df0b61d3b5a 344 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
Michael J. Spencer 2:1df0b61d3b5a 345 - GPDMA_CONN_DAC: DAC
Michael J. Spencer 2:1df0b61d3b5a 346 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
Michael J. Spencer 2:1df0b61d3b5a 347 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
Michael J. Spencer 2:1df0b61d3b5a 348 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
Michael J. Spencer 2:1df0b61d3b5a 349 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
Michael J. Spencer 2:1df0b61d3b5a 350 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
Michael J. Spencer 2:1df0b61d3b5a 351 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
Michael J. Spencer 2:1df0b61d3b5a 352 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
Michael J. Spencer 2:1df0b61d3b5a 353 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
Michael J. Spencer 2:1df0b61d3b5a 354 */
Michael J. Spencer 2:1df0b61d3b5a 355 uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
Michael J. Spencer 2:1df0b61d3b5a 356 GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
Michael J. Spencer 2:1df0b61d3b5a 357 following:
Michael J. Spencer 2:1df0b61d3b5a 358 - GPDMA_CONN_SSP0_Tx: SSP0, Tx
Michael J. Spencer 2:1df0b61d3b5a 359 - GPDMA_CONN_SSP0_Rx: SSP0, Rx
Michael J. Spencer 2:1df0b61d3b5a 360 - GPDMA_CONN_SSP1_Tx: SSP1, Tx
Michael J. Spencer 2:1df0b61d3b5a 361 - GPDMA_CONN_SSP1_Rx: SSP1, Rx
Michael J. Spencer 2:1df0b61d3b5a 362 - GPDMA_CONN_ADC: ADC
Michael J. Spencer 2:1df0b61d3b5a 363 - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
Michael J. Spencer 2:1df0b61d3b5a 364 - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
Michael J. Spencer 2:1df0b61d3b5a 365 - GPDMA_CONN_DAC: DAC
Michael J. Spencer 2:1df0b61d3b5a 366 - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
Michael J. Spencer 2:1df0b61d3b5a 367 - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
Michael J. Spencer 2:1df0b61d3b5a 368 - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
Michael J. Spencer 2:1df0b61d3b5a 369 - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
Michael J. Spencer 2:1df0b61d3b5a 370 - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
Michael J. Spencer 2:1df0b61d3b5a 371 - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
Michael J. Spencer 2:1df0b61d3b5a 372 - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
Michael J. Spencer 2:1df0b61d3b5a 373 - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
Michael J. Spencer 2:1df0b61d3b5a 374 */
Michael J. Spencer 2:1df0b61d3b5a 375 uint32_t DMALLI; /**< Linker List Item structure data address
Michael J. Spencer 2:1df0b61d3b5a 376 if there's no Linker List, set as '0'
Michael J. Spencer 2:1df0b61d3b5a 377 */
Michael J. Spencer 2:1df0b61d3b5a 378 } GPDMA_Channel_CFG_Type;
Michael J. Spencer 2:1df0b61d3b5a 379
Michael J. Spencer 2:1df0b61d3b5a 380 /**
Michael J. Spencer 2:1df0b61d3b5a 381 * @brief GPDMA Linker List Item structure type definition
Michael J. Spencer 2:1df0b61d3b5a 382 */
Michael J. Spencer 2:1df0b61d3b5a 383 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 384 uint32_t SrcAddr; /**< Source Address */
Michael J. Spencer 2:1df0b61d3b5a 385 uint32_t DstAddr; /**< Destination address */
Michael J. Spencer 2:1df0b61d3b5a 386 uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
Michael J. Spencer 2:1df0b61d3b5a 387 uint32_t Control; /**< GPDMA Control of this LLI */
Michael J. Spencer 2:1df0b61d3b5a 388 } GPDMA_LLI_Type;
Michael J. Spencer 2:1df0b61d3b5a 389
Michael J. Spencer 2:1df0b61d3b5a 390
Michael J. Spencer 2:1df0b61d3b5a 391 /**
Michael J. Spencer 2:1df0b61d3b5a 392 * @}
Michael J. Spencer 2:1df0b61d3b5a 393 */
Michael J. Spencer 2:1df0b61d3b5a 394
Michael J. Spencer 2:1df0b61d3b5a 395 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 396 /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
Michael J. Spencer 2:1df0b61d3b5a 397 * @{
Michael J. Spencer 2:1df0b61d3b5a 398 */
Michael J. Spencer 2:1df0b61d3b5a 399
Michael J. Spencer 2:1df0b61d3b5a 400 void GPDMA_Init(void);
Michael J. Spencer 2:1df0b61d3b5a 401 //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
Michael J. Spencer 2:1df0b61d3b5a 402 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
Michael J. Spencer 2:1df0b61d3b5a 403 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
Michael J. Spencer 2:1df0b61d3b5a 404 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
Michael J. Spencer 2:1df0b61d3b5a 405 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 406 //void GPDMA_IntHandler(void);
Michael J. Spencer 2:1df0b61d3b5a 407
Michael J. Spencer 2:1df0b61d3b5a 408 /**
Michael J. Spencer 2:1df0b61d3b5a 409 * @}
Michael J. Spencer 2:1df0b61d3b5a 410 */
Michael J. Spencer 2:1df0b61d3b5a 411
Michael J. Spencer 2:1df0b61d3b5a 412
Michael J. Spencer 2:1df0b61d3b5a 413 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 414 }
Michael J. Spencer 2:1df0b61d3b5a 415 #endif
Michael J. Spencer 2:1df0b61d3b5a 416
Michael J. Spencer 2:1df0b61d3b5a 417 #endif /* LPC17XX_GPDMA_H_ */
Michael J. Spencer 2:1df0b61d3b5a 418
Michael J. Spencer 2:1df0b61d3b5a 419 /**
Michael J. Spencer 2:1df0b61d3b5a 420 * @}
Michael J. Spencer 2:1df0b61d3b5a 421 */
Michael J. Spencer 2:1df0b61d3b5a 422
Michael J. Spencer 2:1df0b61d3b5a 423 /* --------------------------------- End Of File ------------------------------ */