Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_emac.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_emac.h 2010-05-21
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_emac.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains all macro definitions and function prototypes
Michael J. Spencer 2:1df0b61d3b5a 6 * support for Ethernet MAC firmware library on LPC17xx
Michael J. Spencer 2:1df0b61d3b5a 7 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 8 * @date 21. May. 2010
Michael J. Spencer 2:1df0b61d3b5a 9 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 10 *
Michael J. Spencer 2:1df0b61d3b5a 11 * Copyright(C) 2010, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 12 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 13 *
Michael J. Spencer 2:1df0b61d3b5a 14 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 15 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 16 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 17 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 18 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 19 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 20 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 21 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 22 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 23 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 24 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 25 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 26
Michael J. Spencer 2:1df0b61d3b5a 27 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
Michael J. Spencer 2:1df0b61d3b5a 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 30 * @{
Michael J. Spencer 2:1df0b61d3b5a 31 */
Michael J. Spencer 2:1df0b61d3b5a 32
Michael J. Spencer 2:1df0b61d3b5a 33 #ifndef LPC17XX_EMAC_H_
Michael J. Spencer 2:1df0b61d3b5a 34 #define LPC17XX_EMAC_H_
Michael J. Spencer 2:1df0b61d3b5a 35
Michael J. Spencer 2:1df0b61d3b5a 36 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 37 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 38 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 39
Michael J. Spencer 2:1df0b61d3b5a 40
Michael J. Spencer 2:1df0b61d3b5a 41 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 42 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 43 {
Michael J. Spencer 2:1df0b61d3b5a 44 #endif
Michael J. Spencer 2:1df0b61d3b5a 45
Michael J. Spencer 2:1df0b61d3b5a 46 #define MCB_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 47 //#define IAR_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 48
Michael J. Spencer 2:1df0b61d3b5a 49 /* Public Macros -------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 50 /** @defgroup EMAC_Public_Macros EMAC Public Macros
Michael J. Spencer 2:1df0b61d3b5a 51 * @{
Michael J. Spencer 2:1df0b61d3b5a 52 */
Michael J. Spencer 2:1df0b61d3b5a 53
Michael J. Spencer 2:1df0b61d3b5a 54
Michael J. Spencer 2:1df0b61d3b5a 55 /* EMAC PHY status type definitions */
Michael J. Spencer 2:1df0b61d3b5a 56 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
Michael J. Spencer 2:1df0b61d3b5a 57 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
Michael J. Spencer 2:1df0b61d3b5a 58 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
Michael J. Spencer 2:1df0b61d3b5a 59
Michael J. Spencer 2:1df0b61d3b5a 60 /* EMAC PHY device Speed definitions */
Michael J. Spencer 2:1df0b61d3b5a 61 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
Michael J. Spencer 2:1df0b61d3b5a 62 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
Michael J. Spencer 2:1df0b61d3b5a 63 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
Michael J. Spencer 2:1df0b61d3b5a 64 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
Michael J. Spencer 2:1df0b61d3b5a 65 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
Michael J. Spencer 2:1df0b61d3b5a 66
Michael J. Spencer 2:1df0b61d3b5a 67 /**
Michael J. Spencer 2:1df0b61d3b5a 68 * @}
Michael J. Spencer 2:1df0b61d3b5a 69 */
Michael J. Spencer 2:1df0b61d3b5a 70 /* Private Macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 71 /** @defgroup EMAC_Private_Macros EMAC Private Macros
Michael J. Spencer 2:1df0b61d3b5a 72 * @{
Michael J. Spencer 2:1df0b61d3b5a 73 */
Michael J. Spencer 2:1df0b61d3b5a 74
Michael J. Spencer 2:1df0b61d3b5a 75
Michael J. Spencer 2:1df0b61d3b5a 76 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
Michael J. Spencer 2:1df0b61d3b5a 77 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
Michael J. Spencer 2:1df0b61d3b5a 78 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
Michael J. Spencer 2:1df0b61d3b5a 79 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
Michael J. Spencer 2:1df0b61d3b5a 80 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
Michael J. Spencer 2:1df0b61d3b5a 81
Michael J. Spencer 2:1df0b61d3b5a 82 /* --------------------- BIT DEFINITIONS -------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 83 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 84 * Macro defines for MAC Configuration Register 1
Michael J. Spencer 2:1df0b61d3b5a 85 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 86 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
Michael J. Spencer 2:1df0b61d3b5a 87 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
Michael J. Spencer 2:1df0b61d3b5a 88 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
Michael J. Spencer 2:1df0b61d3b5a 89 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
Michael J. Spencer 2:1df0b61d3b5a 90 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
Michael J. Spencer 2:1df0b61d3b5a 91 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
Michael J. Spencer 2:1df0b61d3b5a 92 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
Michael J. Spencer 2:1df0b61d3b5a 93 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
Michael J. Spencer 2:1df0b61d3b5a 94 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
Michael J. Spencer 2:1df0b61d3b5a 95 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
Michael J. Spencer 2:1df0b61d3b5a 96 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
Michael J. Spencer 2:1df0b61d3b5a 97
Michael J. Spencer 2:1df0b61d3b5a 98 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 99 * Macro defines for MAC Configuration Register 2
Michael J. Spencer 2:1df0b61d3b5a 100 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 101 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
Michael J. Spencer 2:1df0b61d3b5a 102 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
Michael J. Spencer 2:1df0b61d3b5a 103 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
Michael J. Spencer 2:1df0b61d3b5a 104 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
Michael J. Spencer 2:1df0b61d3b5a 105 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
Michael J. Spencer 2:1df0b61d3b5a 106 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
Michael J. Spencer 2:1df0b61d3b5a 107 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
Michael J. Spencer 2:1df0b61d3b5a 108 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
Michael J. Spencer 2:1df0b61d3b5a 109 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
Michael J. Spencer 2:1df0b61d3b5a 110 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
Michael J. Spencer 2:1df0b61d3b5a 111 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
Michael J. Spencer 2:1df0b61d3b5a 112 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
Michael J. Spencer 2:1df0b61d3b5a 113 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
Michael J. Spencer 2:1df0b61d3b5a 114
Michael J. Spencer 2:1df0b61d3b5a 115 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 116 * Macro defines for Back-to-Back Inter-Packet-Gap Register
Michael J. Spencer 2:1df0b61d3b5a 117 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 118 /** Programmable field representing the nibble time offset of the minimum possible period
Michael J. Spencer 2:1df0b61d3b5a 119 * between the end of any transmitted packet to the beginning of the next */
Michael J. Spencer 2:1df0b61d3b5a 120 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
Michael J. Spencer 2:1df0b61d3b5a 121 /** Recommended value for Full Duplex of Programmable field representing the nibble time
Michael J. Spencer 2:1df0b61d3b5a 122 * offset of the minimum possible period between the end of any transmitted packet to the
Michael J. Spencer 2:1df0b61d3b5a 123 * beginning of the next */
Michael J. Spencer 2:1df0b61d3b5a 124 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
Michael J. Spencer 2:1df0b61d3b5a 125 /** Recommended value for Half Duplex of Programmable field representing the nibble time
Michael J. Spencer 2:1df0b61d3b5a 126 * offset of the minimum possible period between the end of any transmitted packet to the
Michael J. Spencer 2:1df0b61d3b5a 127 * beginning of the next */
Michael J. Spencer 2:1df0b61d3b5a 128 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
Michael J. Spencer 2:1df0b61d3b5a 129
Michael J. Spencer 2:1df0b61d3b5a 130 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 131 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
Michael J. Spencer 2:1df0b61d3b5a 132 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 133 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
Michael J. Spencer 2:1df0b61d3b5a 134 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
Michael J. Spencer 2:1df0b61d3b5a 135 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
Michael J. Spencer 2:1df0b61d3b5a 136 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
Michael J. Spencer 2:1df0b61d3b5a 137 /** Programmable field representing the optional carrierSense window referenced in
Michael J. Spencer 2:1df0b61d3b5a 138 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
Michael J. Spencer 2:1df0b61d3b5a 139 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
Michael J. Spencer 2:1df0b61d3b5a 140 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
Michael J. Spencer 2:1df0b61d3b5a 141 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
Michael J. Spencer 2:1df0b61d3b5a 142
Michael J. Spencer 2:1df0b61d3b5a 143 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 144 * Macro defines for Collision Window/Retry Register
Michael J. Spencer 2:1df0b61d3b5a 145 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 146 /** Programmable field specifying the number of retransmission attempts following a collision before
Michael J. Spencer 2:1df0b61d3b5a 147 * aborting the packet due to excessive collisions */
Michael J. Spencer 2:1df0b61d3b5a 148 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
Michael J. Spencer 2:1df0b61d3b5a 149 /** Programmable field representing the slot time or collision window during which collisions occur
Michael J. Spencer 2:1df0b61d3b5a 150 * in properly configured networks */
Michael J. Spencer 2:1df0b61d3b5a 151 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
Michael J. Spencer 2:1df0b61d3b5a 152 /** Default value for Collision Window / Retry register */
Michael J. Spencer 2:1df0b61d3b5a 153 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
Michael J. Spencer 2:1df0b61d3b5a 154
Michael J. Spencer 2:1df0b61d3b5a 155 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 156 * Macro defines for Maximum Frame Register
Michael J. Spencer 2:1df0b61d3b5a 157 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 158 /** Represents a maximum receive frame of 1536 octets */
Michael J. Spencer 2:1df0b61d3b5a 159 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
Michael J. Spencer 2:1df0b61d3b5a 160
Michael J. Spencer 2:1df0b61d3b5a 161 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 162 * Macro defines for PHY Support Register
Michael J. Spencer 2:1df0b61d3b5a 163 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 164 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
Michael J. Spencer 2:1df0b61d3b5a 165 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
Michael J. Spencer 2:1df0b61d3b5a 166
Michael J. Spencer 2:1df0b61d3b5a 167 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 168 * Macro defines for Test Register
Michael J. Spencer 2:1df0b61d3b5a 169 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 170 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
Michael J. Spencer 2:1df0b61d3b5a 171 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
Michael J. Spencer 2:1df0b61d3b5a 172 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
Michael J. Spencer 2:1df0b61d3b5a 173
Michael J. Spencer 2:1df0b61d3b5a 174 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 175 * Macro defines for MII Management Configuration Register
Michael J. Spencer 2:1df0b61d3b5a 176 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 177 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
Michael J. Spencer 2:1df0b61d3b5a 178 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
Michael J. Spencer 2:1df0b61d3b5a 179 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
Michael J. Spencer 2:1df0b61d3b5a 180 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
Michael J. Spencer 2:1df0b61d3b5a 181 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
Michael J. Spencer 2:1df0b61d3b5a 182
Michael J. Spencer 2:1df0b61d3b5a 183 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 184 * Macro defines for MII Management Command Register
Michael J. Spencer 2:1df0b61d3b5a 185 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 186 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
Michael J. Spencer 2:1df0b61d3b5a 187 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
Michael J. Spencer 2:1df0b61d3b5a 188
Michael J. Spencer 2:1df0b61d3b5a 189 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
Michael J. Spencer 2:1df0b61d3b5a 190 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
Michael J. Spencer 2:1df0b61d3b5a 191
Michael J. Spencer 2:1df0b61d3b5a 192 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 193 * Macro defines for MII Management Address Register
Michael J. Spencer 2:1df0b61d3b5a 194 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 195 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
Michael J. Spencer 2:1df0b61d3b5a 196 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
Michael J. Spencer 2:1df0b61d3b5a 197
Michael J. Spencer 2:1df0b61d3b5a 198 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 199 * Macro defines for MII Management Write Data Register
Michael J. Spencer 2:1df0b61d3b5a 200 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 201 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
Michael J. Spencer 2:1df0b61d3b5a 202
Michael J. Spencer 2:1df0b61d3b5a 203 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 204 * Macro defines for MII Management Read Data Register
Michael J. Spencer 2:1df0b61d3b5a 205 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 206 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
Michael J. Spencer 2:1df0b61d3b5a 207
Michael J. Spencer 2:1df0b61d3b5a 208 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 209 * Macro defines for MII Management Indicators Register
Michael J. Spencer 2:1df0b61d3b5a 210 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 211 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
Michael J. Spencer 2:1df0b61d3b5a 212 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
Michael J. Spencer 2:1df0b61d3b5a 213 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
Michael J. Spencer 2:1df0b61d3b5a 214 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
Michael J. Spencer 2:1df0b61d3b5a 215
Michael J. Spencer 2:1df0b61d3b5a 216 /* Station Address 0 Register */
Michael J. Spencer 2:1df0b61d3b5a 217 /* Station Address 1 Register */
Michael J. Spencer 2:1df0b61d3b5a 218 /* Station Address 2 Register */
Michael J. Spencer 2:1df0b61d3b5a 219
Michael J. Spencer 2:1df0b61d3b5a 220
Michael J. Spencer 2:1df0b61d3b5a 221 /* Control register definitions --------------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 222 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 223 * Macro defines for Command Register
Michael J. Spencer 2:1df0b61d3b5a 224 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 225 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
Michael J. Spencer 2:1df0b61d3b5a 226 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
Michael J. Spencer 2:1df0b61d3b5a 227 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
Michael J. Spencer 2:1df0b61d3b5a 228 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
Michael J. Spencer 2:1df0b61d3b5a 229 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
Michael J. Spencer 2:1df0b61d3b5a 230 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
Michael J. Spencer 2:1df0b61d3b5a 231 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
Michael J. Spencer 2:1df0b61d3b5a 232 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
Michael J. Spencer 2:1df0b61d3b5a 233 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
Michael J. Spencer 2:1df0b61d3b5a 234 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
Michael J. Spencer 2:1df0b61d3b5a 235
Michael J. Spencer 2:1df0b61d3b5a 236 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 237 * Macro defines for Status Register
Michael J. Spencer 2:1df0b61d3b5a 238 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 239 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
Michael J. Spencer 2:1df0b61d3b5a 240 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
Michael J. Spencer 2:1df0b61d3b5a 241
Michael J. Spencer 2:1df0b61d3b5a 242 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 243 * Macro defines for Transmit Status Vector 0 Register
Michael J. Spencer 2:1df0b61d3b5a 244 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 245 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
Michael J. Spencer 2:1df0b61d3b5a 246 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
Michael J. Spencer 2:1df0b61d3b5a 247 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
Michael J. Spencer 2:1df0b61d3b5a 248 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
Michael J. Spencer 2:1df0b61d3b5a 249 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
Michael J. Spencer 2:1df0b61d3b5a 250 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
Michael J. Spencer 2:1df0b61d3b5a 251 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
Michael J. Spencer 2:1df0b61d3b5a 252 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
Michael J. Spencer 2:1df0b61d3b5a 253 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
Michael J. Spencer 2:1df0b61d3b5a 254 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
Michael J. Spencer 2:1df0b61d3b5a 255 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
Michael J. Spencer 2:1df0b61d3b5a 256 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
Michael J. Spencer 2:1df0b61d3b5a 257 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
Michael J. Spencer 2:1df0b61d3b5a 258 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
Michael J. Spencer 2:1df0b61d3b5a 259 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
Michael J. Spencer 2:1df0b61d3b5a 260 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
Michael J. Spencer 2:1df0b61d3b5a 261 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
Michael J. Spencer 2:1df0b61d3b5a 262
Michael J. Spencer 2:1df0b61d3b5a 263 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 264 * Macro defines for Transmit Status Vector 1 Register
Michael J. Spencer 2:1df0b61d3b5a 265 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 266 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
Michael J. Spencer 2:1df0b61d3b5a 267 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
Michael J. Spencer 2:1df0b61d3b5a 268
Michael J. Spencer 2:1df0b61d3b5a 269 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 270 * Macro defines for Receive Status Vector Register
Michael J. Spencer 2:1df0b61d3b5a 271 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 272 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
Michael J. Spencer 2:1df0b61d3b5a 273 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
Michael J. Spencer 2:1df0b61d3b5a 274 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
Michael J. Spencer 2:1df0b61d3b5a 275 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
Michael J. Spencer 2:1df0b61d3b5a 276 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
Michael J. Spencer 2:1df0b61d3b5a 277 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
Michael J. Spencer 2:1df0b61d3b5a 278 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
Michael J. Spencer 2:1df0b61d3b5a 279 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
Michael J. Spencer 2:1df0b61d3b5a 280 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
Michael J. Spencer 2:1df0b61d3b5a 281 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
Michael J. Spencer 2:1df0b61d3b5a 282 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
Michael J. Spencer 2:1df0b61d3b5a 283 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
Michael J. Spencer 2:1df0b61d3b5a 284 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
Michael J. Spencer 2:1df0b61d3b5a 285 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
Michael J. Spencer 2:1df0b61d3b5a 286 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
Michael J. Spencer 2:1df0b61d3b5a 287 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
Michael J. Spencer 2:1df0b61d3b5a 288
Michael J. Spencer 2:1df0b61d3b5a 289 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 290 * Macro defines for Flow Control Counter Register
Michael J. Spencer 2:1df0b61d3b5a 291 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 292 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
Michael J. Spencer 2:1df0b61d3b5a 293 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
Michael J. Spencer 2:1df0b61d3b5a 294
Michael J. Spencer 2:1df0b61d3b5a 295 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 296 * Macro defines for Flow Control Status Register
Michael J. Spencer 2:1df0b61d3b5a 297 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 298 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
Michael J. Spencer 2:1df0b61d3b5a 299
Michael J. Spencer 2:1df0b61d3b5a 300
Michael J. Spencer 2:1df0b61d3b5a 301 /* Receive filter register definitions -------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 302 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 303 * Macro defines for Receive Filter Control Register
Michael J. Spencer 2:1df0b61d3b5a 304 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 305 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
Michael J. Spencer 2:1df0b61d3b5a 306 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
Michael J. Spencer 2:1df0b61d3b5a 307 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
Michael J. Spencer 2:1df0b61d3b5a 308 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
Michael J. Spencer 2:1df0b61d3b5a 309 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
Michael J. Spencer 2:1df0b61d3b5a 310 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
Michael J. Spencer 2:1df0b61d3b5a 311 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
Michael J. Spencer 2:1df0b61d3b5a 312 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
Michael J. Spencer 2:1df0b61d3b5a 313
Michael J. Spencer 2:1df0b61d3b5a 314 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 315 * Macro defines for Receive Filter WoL Status/Clear Registers
Michael J. Spencer 2:1df0b61d3b5a 316 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 317 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
Michael J. Spencer 2:1df0b61d3b5a 318 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
Michael J. Spencer 2:1df0b61d3b5a 319 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
Michael J. Spencer 2:1df0b61d3b5a 320 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
Michael J. Spencer 2:1df0b61d3b5a 321 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
Michael J. Spencer 2:1df0b61d3b5a 322 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
Michael J. Spencer 2:1df0b61d3b5a 323 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
Michael J. Spencer 2:1df0b61d3b5a 324 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
Michael J. Spencer 2:1df0b61d3b5a 325 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
Michael J. Spencer 2:1df0b61d3b5a 326
Michael J. Spencer 2:1df0b61d3b5a 327
Michael J. Spencer 2:1df0b61d3b5a 328 /* Module control register definitions ---------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 329 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 330 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
Michael J. Spencer 2:1df0b61d3b5a 331 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 332 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
Michael J. Spencer 2:1df0b61d3b5a 333 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
Michael J. Spencer 2:1df0b61d3b5a 334 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
Michael J. Spencer 2:1df0b61d3b5a 335 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
Michael J. Spencer 2:1df0b61d3b5a 336 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
Michael J. Spencer 2:1df0b61d3b5a 337 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
Michael J. Spencer 2:1df0b61d3b5a 338 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
Michael J. Spencer 2:1df0b61d3b5a 339 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
Michael J. Spencer 2:1df0b61d3b5a 340 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
Michael J. Spencer 2:1df0b61d3b5a 341 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
Michael J. Spencer 2:1df0b61d3b5a 342
Michael J. Spencer 2:1df0b61d3b5a 343 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 344 * Macro defines for Power Down Register
Michael J. Spencer 2:1df0b61d3b5a 345 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 346 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
Michael J. Spencer 2:1df0b61d3b5a 347
Michael J. Spencer 2:1df0b61d3b5a 348 /* Descriptor and status formats ---------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 349 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 350 * Macro defines for RX Descriptor Control Word
Michael J. Spencer 2:1df0b61d3b5a 351 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 352 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
Michael J. Spencer 2:1df0b61d3b5a 353 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
Michael J. Spencer 2:1df0b61d3b5a 354
Michael J. Spencer 2:1df0b61d3b5a 355 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 356 * Macro defines for RX Status Hash CRC Word
Michael J. Spencer 2:1df0b61d3b5a 357 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 358 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
Michael J. Spencer 2:1df0b61d3b5a 359 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
Michael J. Spencer 2:1df0b61d3b5a 360
Michael J. Spencer 2:1df0b61d3b5a 361 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 362 * Macro defines for RX Status Information Word
Michael J. Spencer 2:1df0b61d3b5a 363 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 364 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
Michael J. Spencer 2:1df0b61d3b5a 365 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
Michael J. Spencer 2:1df0b61d3b5a 366 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
Michael J. Spencer 2:1df0b61d3b5a 367 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
Michael J. Spencer 2:1df0b61d3b5a 368 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
Michael J. Spencer 2:1df0b61d3b5a 369 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
Michael J. Spencer 2:1df0b61d3b5a 370 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
Michael J. Spencer 2:1df0b61d3b5a 371 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
Michael J. Spencer 2:1df0b61d3b5a 372 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
Michael J. Spencer 2:1df0b61d3b5a 373 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
Michael J. Spencer 2:1df0b61d3b5a 374 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
Michael J. Spencer 2:1df0b61d3b5a 375 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
Michael J. Spencer 2:1df0b61d3b5a 376 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
Michael J. Spencer 2:1df0b61d3b5a 377 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
Michael J. Spencer 2:1df0b61d3b5a 378 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Michael J. Spencer 2:1df0b61d3b5a 379 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
Michael J. Spencer 2:1df0b61d3b5a 380 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
Michael J. Spencer 2:1df0b61d3b5a 381
Michael J. Spencer 2:1df0b61d3b5a 382 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 383 * Macro defines for TX Descriptor Control Word
Michael J. Spencer 2:1df0b61d3b5a 384 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 385 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
Michael J. Spencer 2:1df0b61d3b5a 386 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
Michael J. Spencer 2:1df0b61d3b5a 387 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
Michael J. Spencer 2:1df0b61d3b5a 388 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
Michael J. Spencer 2:1df0b61d3b5a 389 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
Michael J. Spencer 2:1df0b61d3b5a 390 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
Michael J. Spencer 2:1df0b61d3b5a 391 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
Michael J. Spencer 2:1df0b61d3b5a 392
Michael J. Spencer 2:1df0b61d3b5a 393 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 394 * Macro defines for TX Status Information Word
Michael J. Spencer 2:1df0b61d3b5a 395 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 396 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
Michael J. Spencer 2:1df0b61d3b5a 397 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
Michael J. Spencer 2:1df0b61d3b5a 398 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
Michael J. Spencer 2:1df0b61d3b5a 399 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
Michael J. Spencer 2:1df0b61d3b5a 400 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
Michael J. Spencer 2:1df0b61d3b5a 401 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
Michael J. Spencer 2:1df0b61d3b5a 402 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
Michael J. Spencer 2:1df0b61d3b5a 403 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
Michael J. Spencer 2:1df0b61d3b5a 404
Michael J. Spencer 2:1df0b61d3b5a 405 #ifdef MCB_LPC_1768
Michael J. Spencer 2:1df0b61d3b5a 406 /* DP83848C PHY definition ------------------------------------------------------------ */
Michael J. Spencer 2:1df0b61d3b5a 407
Michael J. Spencer 2:1df0b61d3b5a 408 /** PHY device reset time out definition */
Michael J. Spencer 2:1df0b61d3b5a 409 #define EMAC_PHY_RESP_TOUT 0x100000UL
Michael J. Spencer 2:1df0b61d3b5a 410
Michael J. Spencer 2:1df0b61d3b5a 411 /* ENET Device Revision ID */
Michael J. Spencer 2:1df0b61d3b5a 412 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Michael J. Spencer 2:1df0b61d3b5a 413
Michael J. Spencer 2:1df0b61d3b5a 414 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 415 * Macro defines for DP83848C PHY Registers
Michael J. Spencer 2:1df0b61d3b5a 416 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 417 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Michael J. Spencer 2:1df0b61d3b5a 418 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Michael J. Spencer 2:1df0b61d3b5a 419 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Michael J. Spencer 2:1df0b61d3b5a 420 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Michael J. Spencer 2:1df0b61d3b5a 421 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Michael J. Spencer 2:1df0b61d3b5a 422 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Michael J. Spencer 2:1df0b61d3b5a 423 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Michael J. Spencer 2:1df0b61d3b5a 424 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Michael J. Spencer 2:1df0b61d3b5a 425 #define EMAC_PHY_REG_LPNPA 0x08
Michael J. Spencer 2:1df0b61d3b5a 426
Michael J. Spencer 2:1df0b61d3b5a 427 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 428 * Macro defines for PHY Extended Registers
Michael J. Spencer 2:1df0b61d3b5a 429 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 430 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
Michael J. Spencer 2:1df0b61d3b5a 431 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
Michael J. Spencer 2:1df0b61d3b5a 432 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
Michael J. Spencer 2:1df0b61d3b5a 433 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
Michael J. Spencer 2:1df0b61d3b5a 434 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
Michael J. Spencer 2:1df0b61d3b5a 435 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
Michael J. Spencer 2:1df0b61d3b5a 436 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
Michael J. Spencer 2:1df0b61d3b5a 437 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
Michael J. Spencer 2:1df0b61d3b5a 438 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
Michael J. Spencer 2:1df0b61d3b5a 439 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
Michael J. Spencer 2:1df0b61d3b5a 440 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
Michael J. Spencer 2:1df0b61d3b5a 441 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
Michael J. Spencer 2:1df0b61d3b5a 442
Michael J. Spencer 2:1df0b61d3b5a 443 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 444 * Macro defines for PHY Basic Mode Control Register
Michael J. Spencer 2:1df0b61d3b5a 445 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 446 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Michael J. Spencer 2:1df0b61d3b5a 447 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Michael J. Spencer 2:1df0b61d3b5a 448 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Michael J. Spencer 2:1df0b61d3b5a 449 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Michael J. Spencer 2:1df0b61d3b5a 450 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Michael J. Spencer 2:1df0b61d3b5a 451 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Michael J. Spencer 2:1df0b61d3b5a 452 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Michael J. Spencer 2:1df0b61d3b5a 453 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Michael J. Spencer 2:1df0b61d3b5a 454
Michael J. Spencer 2:1df0b61d3b5a 455 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 456 * Macro defines for PHY Basic Mode Status Status Register
Michael J. Spencer 2:1df0b61d3b5a 457 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 458 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Michael J. Spencer 2:1df0b61d3b5a 459 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Michael J. Spencer 2:1df0b61d3b5a 460 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Michael J. Spencer 2:1df0b61d3b5a 461 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Michael J. Spencer 2:1df0b61d3b5a 462 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Michael J. Spencer 2:1df0b61d3b5a 463 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Michael J. Spencer 2:1df0b61d3b5a 464 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Michael J. Spencer 2:1df0b61d3b5a 465 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Michael J. Spencer 2:1df0b61d3b5a 466 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Michael J. Spencer 2:1df0b61d3b5a 467 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
Michael J. Spencer 2:1df0b61d3b5a 468
Michael J. Spencer 2:1df0b61d3b5a 469 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 470 * Macro defines for PHY Status Register
Michael J. Spencer 2:1df0b61d3b5a 471 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 472 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
Michael J. Spencer 2:1df0b61d3b5a 473 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
Michael J. Spencer 2:1df0b61d3b5a 474 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
Michael J. Spencer 2:1df0b61d3b5a 475 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
Michael J. Spencer 2:1df0b61d3b5a 476 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
Michael J. Spencer 2:1df0b61d3b5a 477 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
Michael J. Spencer 2:1df0b61d3b5a 478 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
Michael J. Spencer 2:1df0b61d3b5a 479
Michael J. Spencer 2:1df0b61d3b5a 480 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Michael J. Spencer 2:1df0b61d3b5a 481 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Michael J. Spencer 2:1df0b61d3b5a 482 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Michael J. Spencer 2:1df0b61d3b5a 483 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Michael J. Spencer 2:1df0b61d3b5a 484 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Michael J. Spencer 2:1df0b61d3b5a 485
Michael J. Spencer 2:1df0b61d3b5a 486 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
Michael J. Spencer 2:1df0b61d3b5a 487 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
Michael J. Spencer 2:1df0b61d3b5a 488
Michael J. Spencer 2:1df0b61d3b5a 489 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Michael J. Spencer 2:1df0b61d3b5a 490 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Michael J. Spencer 2:1df0b61d3b5a 491 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Michael J. Spencer 2:1df0b61d3b5a 492
Michael J. Spencer 2:1df0b61d3b5a 493 #elif defined(IAR_LPC_1768)
Michael J. Spencer 2:1df0b61d3b5a 494 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
Michael J. Spencer 2:1df0b61d3b5a 495 /** PHY device reset time out definition */
Michael J. Spencer 2:1df0b61d3b5a 496 #define EMAC_PHY_RESP_TOUT 0x100000UL
Michael J. Spencer 2:1df0b61d3b5a 497
Michael J. Spencer 2:1df0b61d3b5a 498 /* ENET Device Revision ID */
Michael J. Spencer 2:1df0b61d3b5a 499 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
Michael J. Spencer 2:1df0b61d3b5a 500
Michael J. Spencer 2:1df0b61d3b5a 501 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 502 * Macro defines for KSZ8721BL PHY Registers
Michael J. Spencer 2:1df0b61d3b5a 503 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 504 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
Michael J. Spencer 2:1df0b61d3b5a 505 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
Michael J. Spencer 2:1df0b61d3b5a 506 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
Michael J. Spencer 2:1df0b61d3b5a 507 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
Michael J. Spencer 2:1df0b61d3b5a 508 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
Michael J. Spencer 2:1df0b61d3b5a 509 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
Michael J. Spencer 2:1df0b61d3b5a 510 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
Michael J. Spencer 2:1df0b61d3b5a 511 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
Michael J. Spencer 2:1df0b61d3b5a 512 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
Michael J. Spencer 2:1df0b61d3b5a 513 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
Michael J. Spencer 2:1df0b61d3b5a 514 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
Michael J. Spencer 2:1df0b61d3b5a 515 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
Michael J. Spencer 2:1df0b61d3b5a 516
Michael J. Spencer 2:1df0b61d3b5a 517 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 518 * Macro defines for PHY Basic Mode Control Register
Michael J. Spencer 2:1df0b61d3b5a 519 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 520 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
Michael J. Spencer 2:1df0b61d3b5a 521 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
Michael J. Spencer 2:1df0b61d3b5a 522 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
Michael J. Spencer 2:1df0b61d3b5a 523 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
Michael J. Spencer 2:1df0b61d3b5a 524 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
Michael J. Spencer 2:1df0b61d3b5a 525 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
Michael J. Spencer 2:1df0b61d3b5a 526 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
Michael J. Spencer 2:1df0b61d3b5a 527 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
Michael J. Spencer 2:1df0b61d3b5a 528 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
Michael J. Spencer 2:1df0b61d3b5a 529 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
Michael J. Spencer 2:1df0b61d3b5a 530
Michael J. Spencer 2:1df0b61d3b5a 531 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 532 * Macro defines for PHY Basic Mode Status Register
Michael J. Spencer 2:1df0b61d3b5a 533 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 534 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
Michael J. Spencer 2:1df0b61d3b5a 535 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
Michael J. Spencer 2:1df0b61d3b5a 536 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
Michael J. Spencer 2:1df0b61d3b5a 537 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
Michael J. Spencer 2:1df0b61d3b5a 538 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
Michael J. Spencer 2:1df0b61d3b5a 539 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
Michael J. Spencer 2:1df0b61d3b5a 540 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
Michael J. Spencer 2:1df0b61d3b5a 541 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
Michael J. Spencer 2:1df0b61d3b5a 542 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
Michael J. Spencer 2:1df0b61d3b5a 543 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
Michael J. Spencer 2:1df0b61d3b5a 544 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
Michael J. Spencer 2:1df0b61d3b5a 545 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
Michael J. Spencer 2:1df0b61d3b5a 546
Michael J. Spencer 2:1df0b61d3b5a 547 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 548 * Macro defines for PHY Identifier
Michael J. Spencer 2:1df0b61d3b5a 549 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 550 /* PHY Identifier 1 bitmap definitions */
Michael J. Spencer 2:1df0b61d3b5a 551 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
Michael J. Spencer 2:1df0b61d3b5a 552
Michael J. Spencer 2:1df0b61d3b5a 553 /* PHY Identifier 2 bitmap definitions */
Michael J. Spencer 2:1df0b61d3b5a 554 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
Michael J. Spencer 2:1df0b61d3b5a 555
Michael J. Spencer 2:1df0b61d3b5a 556 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 557 * Macro defines for Auto-Negotiation Advertisement
Michael J. Spencer 2:1df0b61d3b5a 558 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 559 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
Michael J. Spencer 2:1df0b61d3b5a 560 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
Michael J. Spencer 2:1df0b61d3b5a 561 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
Michael J. Spencer 2:1df0b61d3b5a 562 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
Michael J. Spencer 2:1df0b61d3b5a 563 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
Michael J. Spencer 2:1df0b61d3b5a 564 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
Michael J. Spencer 2:1df0b61d3b5a 565 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
Michael J. Spencer 2:1df0b61d3b5a 566 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
Michael J. Spencer 2:1df0b61d3b5a 567 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
Michael J. Spencer 2:1df0b61d3b5a 568
Michael J. Spencer 2:1df0b61d3b5a 569 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
Michael J. Spencer 2:1df0b61d3b5a 570 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
Michael J. Spencer 2:1df0b61d3b5a 571 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
Michael J. Spencer 2:1df0b61d3b5a 572 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
Michael J. Spencer 2:1df0b61d3b5a 573 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
Michael J. Spencer 2:1df0b61d3b5a 574
Michael J. Spencer 2:1df0b61d3b5a 575 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
Michael J. Spencer 2:1df0b61d3b5a 576 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
Michael J. Spencer 2:1df0b61d3b5a 577
Michael J. Spencer 2:1df0b61d3b5a 578 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
Michael J. Spencer 2:1df0b61d3b5a 579 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
Michael J. Spencer 2:1df0b61d3b5a 580 #endif
Michael J. Spencer 2:1df0b61d3b5a 581
Michael J. Spencer 2:1df0b61d3b5a 582 /**
Michael J. Spencer 2:1df0b61d3b5a 583 * @}
Michael J. Spencer 2:1df0b61d3b5a 584 */
Michael J. Spencer 2:1df0b61d3b5a 585
Michael J. Spencer 2:1df0b61d3b5a 586
Michael J. Spencer 2:1df0b61d3b5a 587 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 588 /** @defgroup EMAC_Public_Types EMAC Public Types
Michael J. Spencer 2:1df0b61d3b5a 589 * @{
Michael J. Spencer 2:1df0b61d3b5a 590 */
Michael J. Spencer 2:1df0b61d3b5a 591
Michael J. Spencer 2:1df0b61d3b5a 592 /* Descriptor and status formats ---------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 593
Michael J. Spencer 2:1df0b61d3b5a 594 /**
Michael J. Spencer 2:1df0b61d3b5a 595 * @brief RX Descriptor structure type definition
Michael J. Spencer 2:1df0b61d3b5a 596 */
Michael J. Spencer 2:1df0b61d3b5a 597 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 598 uint32_t Packet; /**< Receive Packet Descriptor */
Michael J. Spencer 2:1df0b61d3b5a 599 uint32_t Ctrl; /**< Receive Control Descriptor */
Michael J. Spencer 2:1df0b61d3b5a 600 } RX_Desc;
Michael J. Spencer 2:1df0b61d3b5a 601
Michael J. Spencer 2:1df0b61d3b5a 602 /**
Michael J. Spencer 2:1df0b61d3b5a 603 * @brief RX Status structure type definition
Michael J. Spencer 2:1df0b61d3b5a 604 */
Michael J. Spencer 2:1df0b61d3b5a 605 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 606 uint32_t Info; /**< Receive Information Status */
Michael J. Spencer 2:1df0b61d3b5a 607 uint32_t HashCRC; /**< Receive Hash CRC Status */
Michael J. Spencer 2:1df0b61d3b5a 608 } RX_Stat;
Michael J. Spencer 2:1df0b61d3b5a 609
Michael J. Spencer 2:1df0b61d3b5a 610 /**
Michael J. Spencer 2:1df0b61d3b5a 611 * @brief TX Descriptor structure type definition
Michael J. Spencer 2:1df0b61d3b5a 612 */
Michael J. Spencer 2:1df0b61d3b5a 613 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 614 uint32_t Packet; /**< Transmit Packet Descriptor */
Michael J. Spencer 2:1df0b61d3b5a 615 uint32_t Ctrl; /**< Transmit Control Descriptor */
Michael J. Spencer 2:1df0b61d3b5a 616 } TX_Desc;
Michael J. Spencer 2:1df0b61d3b5a 617
Michael J. Spencer 2:1df0b61d3b5a 618 /**
Michael J. Spencer 2:1df0b61d3b5a 619 * @brief TX Status structure type definition
Michael J. Spencer 2:1df0b61d3b5a 620 */
Michael J. Spencer 2:1df0b61d3b5a 621 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 622 uint32_t Info; /**< Transmit Information Status */
Michael J. Spencer 2:1df0b61d3b5a 623 } TX_Stat;
Michael J. Spencer 2:1df0b61d3b5a 624
Michael J. Spencer 2:1df0b61d3b5a 625
Michael J. Spencer 2:1df0b61d3b5a 626 /**
Michael J. Spencer 2:1df0b61d3b5a 627 * @brief TX Data Buffer structure definition
Michael J. Spencer 2:1df0b61d3b5a 628 */
Michael J. Spencer 2:1df0b61d3b5a 629 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 630 uint32_t ulDataLen; /**< Data length */
Michael J. Spencer 2:1df0b61d3b5a 631 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
Michael J. Spencer 2:1df0b61d3b5a 632 } EMAC_PACKETBUF_Type;
Michael J. Spencer 2:1df0b61d3b5a 633
Michael J. Spencer 2:1df0b61d3b5a 634 /**
Michael J. Spencer 2:1df0b61d3b5a 635 * @brief EMAC configuration structure definition
Michael J. Spencer 2:1df0b61d3b5a 636 */
Michael J. Spencer 2:1df0b61d3b5a 637 typedef struct {
Michael J. Spencer 2:1df0b61d3b5a 638 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
Michael J. Spencer 2:1df0b61d3b5a 639 - EMAC_MODE_AUTO
Michael J. Spencer 2:1df0b61d3b5a 640 - EMAC_MODE_10M_FULL
Michael J. Spencer 2:1df0b61d3b5a 641 - EMAC_MODE_10M_HALF
Michael J. Spencer 2:1df0b61d3b5a 642 - EMAC_MODE_100M_FULL
Michael J. Spencer 2:1df0b61d3b5a 643 - EMAC_MODE_100M_HALF
Michael J. Spencer 2:1df0b61d3b5a 644 */
Michael J. Spencer 2:1df0b61d3b5a 645 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
Michael J. Spencer 2:1df0b61d3b5a 646 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
Michael J. Spencer 2:1df0b61d3b5a 647 */
Michael J. Spencer 2:1df0b61d3b5a 648 } EMAC_CFG_Type;
Michael J. Spencer 2:1df0b61d3b5a 649
Michael J. Spencer 2:1df0b61d3b5a 650
Michael J. Spencer 2:1df0b61d3b5a 651 /**
Michael J. Spencer 2:1df0b61d3b5a 652 * @}
Michael J. Spencer 2:1df0b61d3b5a 653 */
Michael J. Spencer 2:1df0b61d3b5a 654
Michael J. Spencer 2:1df0b61d3b5a 655
Michael J. Spencer 2:1df0b61d3b5a 656 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 657 /** @defgroup EMAC_Public_Functions EMAC Public Functions
Michael J. Spencer 2:1df0b61d3b5a 658 * @{
Michael J. Spencer 2:1df0b61d3b5a 659 */
Michael J. Spencer 2:1df0b61d3b5a 660 /* Init/DeInit EMAC peripheral */
Michael J. Spencer 2:1df0b61d3b5a 661 Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
Michael J. Spencer 2:1df0b61d3b5a 662 void EMAC_DeInit(void);
Michael J. Spencer 2:1df0b61d3b5a 663
Michael J. Spencer 2:1df0b61d3b5a 664 /* PHY functions --------------*/
Michael J. Spencer 2:1df0b61d3b5a 665 int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
Michael J. Spencer 2:1df0b61d3b5a 666 int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
Michael J. Spencer 2:1df0b61d3b5a 667 int32_t EMAC_UpdatePHYStatus(void);
Michael J. Spencer 2:1df0b61d3b5a 668
Michael J. Spencer 2:1df0b61d3b5a 669 /* Filter functions ----------*/
Michael J. Spencer 2:1df0b61d3b5a 670 void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 671 void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 672
Michael J. Spencer 2:1df0b61d3b5a 673 /* EMAC Packet Buffer functions */
Michael J. Spencer 2:1df0b61d3b5a 674 void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
Michael J. Spencer 2:1df0b61d3b5a 675 void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
Michael J. Spencer 2:1df0b61d3b5a 676
Michael J. Spencer 2:1df0b61d3b5a 677 /* EMAC Interrupt functions -------*/
Michael J. Spencer 2:1df0b61d3b5a 678 void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 679 IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
Michael J. Spencer 2:1df0b61d3b5a 680
Michael J. Spencer 2:1df0b61d3b5a 681 /* EMAC Index functions -----------*/
Michael J. Spencer 2:1df0b61d3b5a 682 Bool EMAC_CheckReceiveIndex(void);
Michael J. Spencer 2:1df0b61d3b5a 683 Bool EMAC_CheckTransmitIndex(void);
Michael J. Spencer 2:1df0b61d3b5a 684 void EMAC_UpdateRxConsumeIndex(void);
Michael J. Spencer 2:1df0b61d3b5a 685 void EMAC_UpdateTxProduceIndex(void);
Michael J. Spencer 2:1df0b61d3b5a 686
Michael J. Spencer 2:1df0b61d3b5a 687 FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
Michael J. Spencer 2:1df0b61d3b5a 688 uint32_t EMAC_GetReceiveDataSize(void);
Michael J. Spencer 2:1df0b61d3b5a 689 FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
Michael J. Spencer 2:1df0b61d3b5a 690
Michael J. Spencer 2:1df0b61d3b5a 691 /**
Michael J. Spencer 2:1df0b61d3b5a 692 * @}
Michael J. Spencer 2:1df0b61d3b5a 693 */
Michael J. Spencer 2:1df0b61d3b5a 694
Michael J. Spencer 2:1df0b61d3b5a 695 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 696 }
Michael J. Spencer 2:1df0b61d3b5a 697 #endif
Michael J. Spencer 2:1df0b61d3b5a 698
Michael J. Spencer 2:1df0b61d3b5a 699 #endif /* LPC17XX_EMAC_H_ */
Michael J. Spencer 2:1df0b61d3b5a 700
Michael J. Spencer 2:1df0b61d3b5a 701 /**
Michael J. Spencer 2:1df0b61d3b5a 702 * @}
Michael J. Spencer 2:1df0b61d3b5a 703 */
Michael J. Spencer 2:1df0b61d3b5a 704
Michael J. Spencer 2:1df0b61d3b5a 705 /* --------------------------------- End Of File ------------------------------ */