Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_clkpwr.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_clkpwr.h 2010-05-21 |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_clkpwr.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for Clock and Power Control firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 2.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 21. May. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup CLKPWR CLKPWR (Clock Power) |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_CLKPWR_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_CLKPWR_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | extern "C" |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | /* Public Macros -------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | * Peripheral Clock Selection Definitions |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | /** Peripheral clock divider bit position for WDT */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | /** Peripheral clock divider bit position for TIMER0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | /** Peripheral clock divider bit position for TIMER1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | /** Peripheral clock divider bit position for UART0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | /** Peripheral clock divider bit position for UART1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | /** Peripheral clock divider bit position for PWM1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | /** Peripheral clock divider bit position for I2C0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | /** Peripheral clock divider bit position for SPI */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | /** Peripheral clock divider bit position for SSP1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | /** Peripheral clock divider bit position for DAC */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | /** Peripheral clock divider bit position for ADC */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | /** Peripheral clock divider bit position for CAN1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | /** Peripheral clock divider bit position for CAN2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | /** Peripheral clock divider bit position for ACF */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | /** Peripheral clock divider bit position for QEI */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | /** Peripheral clock divider bit position for PCB */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | /** Peripheral clock divider bit position for I2C1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | /** Peripheral clock divider bit position for SSP0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | /** Peripheral clock divider bit position for TIMER2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | /** Peripheral clock divider bit position for TIMER3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | /** Peripheral clock divider bit position for UART2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | /** Peripheral clock divider bit position for UART3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | /** Peripheral clock divider bit position for I2C2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | /** Peripheral clock divider bit position for I2S */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | /** Peripheral clock divider bit position for RIT */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | /** Peripheral clock divider bit position for SYSCON */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | /** Peripheral clock divider bit position for MC */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | #define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | /** Macro for Peripheral Clock Selection register bit values |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | * Note: When CCLK_DIV_8, Peripheral's clock is selected to |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | * when '11'selects PCLK_xyz = CCLK/6 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | /* Peripheral clock divider is set to 4 from CCLK */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | /** Peripheral clock divider is the same with CCLK */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | /** Peripheral clock divider is set to 2 from CCLK */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | /******************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | * Power Control for Peripherals Definitions |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | /** Timer/Counter 0 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | /* Timer/Counter 1 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | /** UART0 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | /** UART1 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | /** PWM1 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | /** The I2C0 interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | /** The SPI interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | /** The RTC power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | /** The SSP1 interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | /** A/D converter 0 (ADC0) power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | /** CAN Controller 1 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | /** CAN Controller 2 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | /** GPIO power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | /** Repetitive Interrupt Timer power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | /** Motor Control PWM */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | /** Quadrature Encoder Interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | /** The I2C1 interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | /** The SSP0 interface power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | /** Timer 2 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | /** Timer 3 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | /** UART 2 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | /** UART 3 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | /** I2C interface 2 power/clock control bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | /** I2S interface power/clock control bit*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | /** GP DMA function power/clock control bit*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | /** Ethernet block power/clock control bit*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | /** USB interface power/clock control bit*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | /* Private Macros ------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | * Macro defines for Clock Source Select Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | /** Internal RC oscillator */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | /** Main oscillator */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | /** RTC oscillator */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | /** Clock source selection bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | * Macro defines for Clock Output Configuration Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | /* Clock Output Configuration register definition */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | /** Selects the CPU clock as the CLKOUT source */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | /** Selects the main oscillator as the CLKOUT source */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | /** Selects the Internal RC oscillator as the CLKOUT source */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | /** Selects the USB clock as the CLKOUT source */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | /** Selects the RTC oscillator as the CLKOUT source */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | /** Integer value to divide the output clock by, minus one */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | /** CLKOUT enable control */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | /** CLKOUT activity indication */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | /** Clock source selection bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | * Macro defines for PPL0 Control Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | /** PLL 0 control enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | /** PLL 0 control connect */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | /** PLL 0 control bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | * Macro defines for PPL0 Configuration Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | /** PLL 0 Configuration MSEL field */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | /** PLL 0 Configuration NSEL field */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | /** PLL 0 Configuration bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | * Macro defines for PPL0 Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | /** PLL 0 MSEL value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | /** PLL NSEL get value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | /** PLL status enable bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | /** PLL status Connect bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | /** PLL status lock */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | * Macro defines for PPL0 Feed Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | /** PLL0 Feed bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | * Macro defines for PLL1 Control Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | /** USB PLL control enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | /** USB PLL control connect */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | /** USB PLL control bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | * Macro defines for PLL1 Configuration Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | /** USB PLL MSEL set value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | /** USB PLL PSEL set value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | /** USB PLL configuration bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | * Macro defines for PLL1 Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | /** USB PLL MSEL get value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | /** USB PLL PSEL get value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | /** USB PLL status enable bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | /** USB PLL status Connect bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | /** USB PLL status lock */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | * Macro defines for PLL1 Feed Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | /** PLL1 Feed bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | * Macro defines for CPU Clock Configuration Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | /** CPU Clock configuration bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | * Macro defines for USB Clock Configuration Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | /** USB Clock Configuration bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | * Macro defines for IRC Trim Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | /** IRC Trim bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | * Macro defines for Peripheral Clock Selection Register 0 and 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | /** Peripheral Clock Selection 0 mask bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | /** Peripheral Clock Selection 1 mask bit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | /** Macro to set peripheral clock of each type |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | * p: position of two bits that hold divider of peripheral clock |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | * n: value of divider of peripheral clock to be set */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | /** Macro to mask peripheral clock of each type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | /** Macro to get peripheral clock of each type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | * Macro defines for Power Mode Control Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | /** Power mode control bit 0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | /** Power mode control bit 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | /** Brown-Out Reduced Power Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | /** Brown-Out Global Disable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | /** Brown Out Reset Disable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | #define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | /** Sleep Mode entry flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | /** Deep Sleep entry flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | /** Power-down entry flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | /** Deep Power-down entry flag */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | * Macro defines for Power Control for Peripheral Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | /** Power Control for Peripherals bit mask */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | uint32_t CLKPWR_GetPCLK (uint32_t ClkType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | void CLKPWR_Sleep(void); |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | void CLKPWR_DeepSleep(void); |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | void CLKPWR_PowerDown(void); |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | void CLKPWR_DeepPowerDown(void); |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | #endif /* LPC17XX_CLKPWR_H_ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | /* --------------------------------- End Of File ------------------------------ */ |