Michael Spencer
Fork of Smoothie to port to mbed non-LPC targets.
Fork of
Smoothie
by 
Stéphane Cachat
libs/LPC17xx/LPC17xxLib/inc/lpc17xx_can.h@2:1df0b61d3b5a, 2014-02-28 (annotated)
- Committer:
- Michael J. Spencer
- Date:
- Fri Feb 28 18:52:52 2014 -0800
- Revision:
- 2:1df0b61d3b5a
Update to latest Smoothie.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Michael J. Spencer |
2:1df0b61d3b5a | 1 | /********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 2 | * $Id$ lpc17xx_can.h 2010-06-18 |
| Michael J. Spencer |
2:1df0b61d3b5a | 3 | *//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 4 | * @file lpc17xx_can.h |
| Michael J. Spencer |
2:1df0b61d3b5a | 5 | * @brief Contains all macro definitions and function prototypes |
| Michael J. Spencer |
2:1df0b61d3b5a | 6 | * support for CAN firmware library on LPC17xx |
| Michael J. Spencer |
2:1df0b61d3b5a | 7 | * @version 3.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 8 | * @date 18. June. 2010 |
| Michael J. Spencer |
2:1df0b61d3b5a | 9 | * @author NXP MCU SW Application Team |
| Michael J. Spencer |
2:1df0b61d3b5a | 10 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 11 | * Copyright(C) 2010, NXP Semiconductor |
| Michael J. Spencer |
2:1df0b61d3b5a | 12 | * All rights reserved. |
| Michael J. Spencer |
2:1df0b61d3b5a | 13 | * |
| Michael J. Spencer |
2:1df0b61d3b5a | 14 | *********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 15 | * Software that is described herein is for illustrative purposes only |
| Michael J. Spencer |
2:1df0b61d3b5a | 16 | * which provides customers with programming information regarding the |
| Michael J. Spencer |
2:1df0b61d3b5a | 17 | * products. This software is supplied "AS IS" without any warranties. |
| Michael J. Spencer |
2:1df0b61d3b5a | 18 | * NXP Semiconductors assumes no responsibility or liability for the |
| Michael J. Spencer |
2:1df0b61d3b5a | 19 | * use of the software, conveys no license or title under any patent, |
| Michael J. Spencer |
2:1df0b61d3b5a | 20 | * copyright, or mask work right to the product. NXP Semiconductors |
| Michael J. Spencer |
2:1df0b61d3b5a | 21 | * reserves the right to make changes in the software without |
| Michael J. Spencer |
2:1df0b61d3b5a | 22 | * notification. NXP Semiconductors also make no representation or |
| Michael J. Spencer |
2:1df0b61d3b5a | 23 | * warranty that such application will be suitable for the specified |
| Michael J. Spencer |
2:1df0b61d3b5a | 24 | * use without further testing or modification. |
| Michael J. Spencer |
2:1df0b61d3b5a | 25 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 26 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 27 | /* Peripheral group ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 28 | /** @defgroup CAN CAN (Control Area Network) |
| Michael J. Spencer |
2:1df0b61d3b5a | 29 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| Michael J. Spencer |
2:1df0b61d3b5a | 30 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 31 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 32 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 33 | #ifndef LPC17XX_CAN_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 34 | #define LPC17XX_CAN_H_ |
| Michael J. Spencer |
2:1df0b61d3b5a | 35 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 36 | /* Includes ------------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 37 | #include "LPC17xx.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 38 | #include "lpc_types.h" |
| Michael J. Spencer |
2:1df0b61d3b5a | 39 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 40 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 41 | extern "C" |
| Michael J. Spencer |
2:1df0b61d3b5a | 42 | { |
| Michael J. Spencer |
2:1df0b61d3b5a | 43 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 44 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 45 | /* Public Types --------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 46 | /** @defgroup CAN_Public_Macros CAN Public Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 47 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 48 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 49 | #define MSG_ENABLE ((uint8_t)(0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 50 | #define MSG_DISABLE ((uint8_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 51 | #define CAN1_CTRL ((uint8_t)(0)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 52 | #define CAN2_CTRL ((uint8_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 53 | #define PARAM_FULLCAN_IC(n) ((n==FULLCAN_IC0)||(n==FULLCAN_IC1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 54 | #define ID_11 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 55 | #define MAX_HW_FULLCAN_OBJ 64 |
| Michael J. Spencer |
2:1df0b61d3b5a | 56 | #define MAX_SW_FULLCAN_OBJ 32 |
| Michael J. Spencer |
2:1df0b61d3b5a | 57 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 58 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 59 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 60 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 61 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 62 | /* Private Macros ------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 63 | /** @defgroup CAN_Private_Macros CAN Private Macros |
| Michael J. Spencer |
2:1df0b61d3b5a | 64 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 65 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 66 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 67 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 68 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 69 | * Macro defines for CAN Mode Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 70 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 71 | /** CAN Reset mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 72 | #define CAN_MOD_RM ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 73 | /** CAN Listen Only Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 74 | #define CAN_MOD_LOM ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 75 | /** CAN Self Test mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 76 | #define CAN_MOD_STM ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 77 | /** CAN Transmit Priority mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 78 | #define CAN_MOD_TPM ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 79 | /** CAN Sleep mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 80 | #define CAN_MOD_SM ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 81 | /** CAN Receive Polarity mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 82 | #define CAN_MOD_RPM ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 83 | /** CAN Test mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 84 | #define CAN_MOD_TM ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 85 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 86 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 87 | * Macro defines for CAN Command Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 88 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 89 | /** CAN Transmission Request */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 90 | #define CAN_CMR_TR ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 91 | /** CAN Abort Transmission */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 92 | #define CAN_CMR_AT ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 93 | /** CAN Release Receive Buffer */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 94 | #define CAN_CMR_RRB ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 95 | /** CAN Clear Data Overrun */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 96 | #define CAN_CMR_CDO ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 97 | /** CAN Self Reception Request */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 98 | #define CAN_CMR_SRR ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 99 | /** CAN Select Tx Buffer 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 100 | #define CAN_CMR_STB1 ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 101 | /** CAN Select Tx Buffer 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 102 | #define CAN_CMR_STB2 ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 103 | /** CAN Select Tx Buffer 3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 104 | #define CAN_CMR_STB3 ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 105 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 106 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 107 | * Macro defines for CAN Global Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 108 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 109 | /** CAN Receive Buffer Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 110 | #define CAN_GSR_RBS ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 111 | /** CAN Data Overrun Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 112 | #define CAN_GSR_DOS ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 113 | /** CAN Transmit Buffer Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 114 | #define CAN_GSR_TBS ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 115 | /** CAN Transmit Complete Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 116 | #define CAN_GSR_TCS ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 117 | /** CAN Receive Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 118 | #define CAN_GSR_RS ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 119 | /** CAN Transmit Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 120 | #define CAN_GSR_TS ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 121 | /** CAN Error Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 122 | #define CAN_GSR_ES ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 123 | /** CAN Bus Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 124 | #define CAN_GSR_BS ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 125 | /** CAN Current value of the Rx Error Counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 126 | #define CAN_GSR_RXERR(n) ((uint32_t)((n&0xFF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 127 | /** CAN Current value of the Tx Error Counter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 128 | #define CAN_GSR_TXERR(n) ((uint32_t)(n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 129 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 130 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 131 | * Macro defines for CAN Interrupt and Capture Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 132 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 133 | /** CAN Receive Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 134 | #define CAN_ICR_RI ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 135 | /** CAN Transmit Interrupt 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 136 | #define CAN_ICR_TI1 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 137 | /** CAN Error Warning Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 138 | #define CAN_ICR_EI ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 139 | /** CAN Data Overrun Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 140 | #define CAN_ICR_DOI ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 141 | /** CAN Wake-Up Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 142 | #define CAN_ICR_WUI ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 143 | /** CAN Error Passive Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 144 | #define CAN_ICR_EPI ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 145 | /** CAN Arbitration Lost Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 146 | #define CAN_ICR_ALI ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 147 | /** CAN Bus Error Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 148 | #define CAN_ICR_BEI ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 149 | /** CAN ID Ready Interrupt */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 150 | #define CAN_ICR_IDI ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 151 | /** CAN Transmit Interrupt 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 152 | #define CAN_ICR_TI2 ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 153 | /** CAN Transmit Interrupt 3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 154 | #define CAN_ICR_TI3 ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 155 | /** CAN Error Code Capture */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 156 | #define CAN_ICR_ERRBIT(n) ((uint32_t)((n&0x1F)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 157 | /** CAN Error Direction */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 158 | #define CAN_ICR_ERRDIR ((uint32_t)(1<<21)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 159 | /** CAN Error Capture */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 160 | #define CAN_ICR_ERRC(n) ((uint32_t)((n&0x3)<<22)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 161 | /** CAN Arbitration Lost Capture */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 162 | #define CAN_ICR_ALCBIT(n) ((uint32_t)((n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 163 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 164 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 165 | * Macro defines for CAN Interrupt Enable Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 166 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 167 | /** CAN Receive Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 168 | #define CAN_IER_RIE ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 169 | /** CAN Transmit Interrupt Enable for buffer 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 170 | #define CAN_IER_TIE1 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 171 | /** CAN Error Warning Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 172 | #define CAN_IER_EIE ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 173 | /** CAN Data Overrun Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 174 | #define CAN_IER_DOIE ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 175 | /** CAN Wake-Up Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 176 | #define CAN_IER_WUIE ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 177 | /** CAN Error Passive Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 178 | #define CAN_IER_EPIE ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 179 | /** CAN Arbitration Lost Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 180 | #define CAN_IER_ALIE ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 181 | /** CAN Bus Error Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 182 | #define CAN_IER_BEIE ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 183 | /** CAN ID Ready Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 184 | #define CAN_IER_IDIE ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 185 | /** CAN Transmit Enable Interrupt for Buffer 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 186 | #define CAN_IER_TIE2 ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 187 | /** CAN Transmit Enable Interrupt for Buffer 3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 188 | #define CAN_IER_TIE3 ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 189 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 190 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 191 | * Macro defines for CAN Bus Timing Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 192 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 193 | /** CAN Baudrate Prescaler */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 194 | #define CAN_BTR_BRP(n) ((uint32_t)(n&0x3FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 195 | /** CAN Synchronization Jump Width */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 196 | #define CAN_BTR_SJM(n) ((uint32_t)((n&0x3)<<14)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 197 | /** CAN Time Segment 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 198 | #define CAN_BTR_TESG1(n) ((uint32_t)(n&0xF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 199 | /** CAN Time Segment 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 200 | #define CAN_BTR_TESG2(n) ((uint32_t)(n&0xF)<<20)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 201 | /** CAN Sampling */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 202 | #define CAN_BTR_SAM(n) ((uint32_t)(1<<23)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 203 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 204 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 205 | * Macro defines for CAN Error Warning Limit Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 206 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 207 | /** CAN Error Warning Limit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 208 | #define CAN_EWL_EWL(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 209 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 210 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 211 | * Macro defines for CAN Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 212 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 213 | /** CAN Receive Buffer Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 214 | #define CAN_SR_RBS ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 215 | /** CAN Data Overrun Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 216 | #define CAN_SR_DOS ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 217 | /** CAN Transmit Buffer Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 218 | #define CAN_SR_TBS1 ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 219 | /** CAN Transmission Complete Status of Buffer 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 220 | #define CAN_SR_TCS1 ((uint32_t)(1<<3)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 221 | /** CAN Receive Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 222 | #define CAN_SR_RS ((uint32_t)(1<<4)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 223 | /** CAN Transmit Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 224 | #define CAN_SR_TS1 ((uint32_t)(1<<5)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 225 | /** CAN Error Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 226 | #define CAN_SR_ES ((uint32_t)(1<<6)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 227 | /** CAN Bus Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 228 | #define CAN_SR_BS ((uint32_t)(1<<7)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 229 | /** CAN Transmit Buffer Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 230 | #define CAN_SR_TBS2 ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 231 | /** CAN Transmission Complete Status of Buffer 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 232 | #define CAN_SR_TCS2 ((uint32_t)(1<<11)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 233 | /** CAN Transmit Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 234 | #define CAN_SR_TS2 ((uint32_t)(1<<13)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 235 | /** CAN Transmit Buffer Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 236 | #define CAN_SR_TBS3 ((uint32_t)(1<<18)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 237 | /** CAN Transmission Complete Status of Buffer 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 238 | #define CAN_SR_TCS3 ((uint32_t)(1<<19)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 239 | /** CAN Transmit Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 240 | #define CAN_SR_TS3 ((uint32_t)(1<<21)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 241 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 242 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 243 | * Macro defines for CAN Receive Frame Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 244 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 245 | /** CAN ID Index */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 246 | #define CAN_RFS_ID_INDEX(n) ((uint32_t)(n&0x3FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 247 | /** CAN Bypass */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 248 | #define CAN_RFS_BP ((uint32_t)(1<<10)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 249 | /** CAN Data Length Code */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 250 | #define CAN_RFS_DLC(n) ((uint32_t)((n&0xF)<<16) |
| Michael J. Spencer |
2:1df0b61d3b5a | 251 | /** CAN Remote Transmission Request */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 252 | #define CAN_RFS_RTR ((uint32_t)(1<<30)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 253 | /** CAN control 11 bit or 29 bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 254 | #define CAN_RFS_FF ((uint32_t)(1<<31)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 255 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 256 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 257 | * Macro defines for CAN Receive Identifier Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 258 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 259 | /** CAN 11 bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 260 | #define CAN_RID_ID_11(n) ((uint32_t)(n&0x7FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 261 | /** CAN 29 bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 262 | #define CAN_RID_ID_29(n) ((uint32_t)(n&0x1FFFFFFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 263 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 264 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 265 | * Macro defines for CAN Receive Data A Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 266 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 267 | /** CAN Receive Data 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 268 | #define CAN_RDA_DATA1(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 269 | /** CAN Receive Data 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 270 | #define CAN_RDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 271 | /** CAN Receive Data 3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 272 | #define CAN_RDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 273 | /** CAN Receive Data 4 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 274 | #define CAN_RDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 275 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 276 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 277 | * Macro defines for CAN Receive Data B Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 278 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 279 | /** CAN Receive Data 5 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 280 | #define CAN_RDB_DATA5(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 281 | /** CAN Receive Data 6 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 282 | #define CAN_RDB_DATA6(n) ((uint32_t)((n&0xFF)<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 283 | /** CAN Receive Data 7 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 284 | #define CAN_RDB_DATA7(n) ((uint32_t)((n&0xFF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 285 | /** CAN Receive Data 8 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 286 | #define CAN_RDB_DATA8(n) ((uint32_t)((n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 287 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 288 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 289 | * Macro defines for CAN Transmit Frame Information Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 290 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 291 | /** CAN Priority */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 292 | #define CAN_TFI_PRIO(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 293 | /** CAN Data Length Code */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 294 | #define CAN_TFI_DLC(n) ((uint32_t)((n&0xF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 295 | /** CAN Remote Frame Transmission */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 296 | #define CAN_TFI_RTR ((uint32_t)(1<<30)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 297 | /** CAN control 11-bit or 29-bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 298 | #define CAN_TFI_FF ((uint32_t)(1<<31)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 299 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 300 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 301 | * Macro defines for CAN Transmit Identifier Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 302 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 303 | /** CAN 11-bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 304 | #define CAN_TID_ID11(n) ((uint32_t)(n&0x7FF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 305 | /** CAN 11-bit Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 306 | #define CAN_TID_ID29(n) ((uint32_t)(n&0x1FFFFFFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 307 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 308 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 309 | * Macro defines for CAN Transmit Data A Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 310 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 311 | /** CAN Transmit Data 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 312 | #define CAN_TDA_DATA1(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 313 | /** CAN Transmit Data 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 314 | #define CAN_TDA_DATA2(n) ((uint32_t)((n&0xFF)<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 315 | /** CAN Transmit Data 3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 316 | #define CAN_TDA_DATA3(n) ((uint32_t)((n&0xFF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 317 | /** CAN Transmit Data 4 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 318 | #define CAN_TDA_DATA4(n) ((uint32_t)((n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 319 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 320 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 321 | * Macro defines for CAN Transmit Data B Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 322 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 323 | /** CAN Transmit Data 5 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 324 | #define CAN_TDA_DATA5(n) ((uint32_t)(n&0xFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 325 | /** CAN Transmit Data 6 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 326 | #define CAN_TDA_DATA6(n) ((uint32_t)((n&0xFF)<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 327 | /** CAN Transmit Data 7 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 328 | #define CAN_TDA_DATA7(n) ((uint32_t)((n&0xFF)<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 329 | /** CAN Transmit Data 8 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 330 | #define CAN_TDA_DATA8(n) ((uint32_t)((n&0xFF)<<24)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 331 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 332 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 333 | * Macro defines for CAN Sleep Clear Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 334 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 335 | /** CAN1 Sleep mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 336 | #define CAN1SLEEPCLR ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 337 | /** CAN2 Sleep Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 338 | #define CAN2SLEEPCLR ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 339 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 340 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 341 | * Macro defines for CAN Wake up Flags Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 342 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 343 | /** CAN1 Sleep mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 344 | #define CAN_WAKEFLAGES_CAN1WAKE ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 345 | /** CAN2 Sleep Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 346 | #define CAN_WAKEFLAGES_CAN2WAKE ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 347 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 348 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 349 | * Macro defines for Central transmit Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 350 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 351 | /** CAN Transmit 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 352 | #define CAN_TSR_TS1 ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 353 | /** CAN Transmit 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 354 | #define CAN_TSR_TS2 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 355 | /** CAN Transmit Buffer Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 356 | #define CAN_TSR_TBS1 ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 357 | /** CAN Transmit Buffer Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 358 | #define CAN_TSR_TBS2 ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 359 | /** CAN Transmission Complete Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 360 | #define CAN_TSR_TCS1 ((uint32_t)(1<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 361 | /** CAN Transmission Complete Status 2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 362 | #define CAN_TSR_TCS2 ((uint32_t)(1<<17)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 363 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 364 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 365 | * Macro defines for Central Receive Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 366 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 367 | /** CAN Receive Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 368 | #define CAN_RSR_RS1 ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 369 | /** CAN Receive Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 370 | #define CAN_RSR_RS2 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 371 | /** CAN Receive Buffer Status 1*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 372 | #define CAN_RSR_RB1 ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 373 | /** CAN Receive Buffer Status 2*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 374 | #define CAN_RSR_RB2 ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 375 | /** CAN Data Overrun Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 376 | #define CAN_RSR_DOS1 ((uint32_t)(1<<16)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 377 | /** CAN Data Overrun Status 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 378 | #define CAN_RSR_DOS2 ((uint32_t)(1<<17)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 379 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 380 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 381 | * Macro defines for Central Miscellaneous Status Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 382 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 383 | /** Same CAN Error Status in CAN1GSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 384 | #define CAN_MSR_E1 ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 385 | /** Same CAN Error Status in CAN2GSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 386 | #define CAN_MSR_E2 ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 387 | /** Same CAN Bus Status in CAN1GSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 388 | #define CAN_MSR_BS1 ((uint32_t)(1<<8)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 389 | /** Same CAN Bus Status in CAN2GSR */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 390 | #define CAN_MSR_BS2 ((uint32_t)(1<<9)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 391 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 392 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 393 | * Macro defines for Acceptance Filter Mode Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 394 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 395 | /** CAN Acceptance Filter Off mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 396 | #define CAN_AFMR_AccOff ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 397 | /** CAN Acceptance File Bypass mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 398 | #define CAN_AFMR_AccBP ((uint32_t)(1<<1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 399 | /** FullCAN Mode Enhancements */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 400 | #define CAN_AFMR_eFCAN ((uint32_t)(1<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 401 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 402 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 403 | * Macro defines for Standard Frame Individual Start Address Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 404 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 405 | /** The start address of the table of individual Standard Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 406 | #define CAN_STT_sa(n) ((uint32_t)((n&1FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 407 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 408 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 409 | * Macro defines for Standard Frame Group Start Address Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 410 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 411 | /** The start address of the table of grouped Standard Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 412 | #define CAN_SFF_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 413 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 414 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 415 | * Macro defines for Extended Frame Start Address Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 416 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 417 | /** The start address of the table of individual Extended Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 418 | #define CAN_EFF_sa(n) ((uint32_t)((n&1FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 419 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 420 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 421 | * Macro defines for Extended Frame Group Start Address Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 422 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 423 | /** The start address of the table of grouped Extended Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 424 | #define CAN_Eff_GRP_sa(n) ((uint32_t)((n&3FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 425 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 426 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 427 | * Macro defines for End Of AF Table Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 428 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 429 | /** The End of Table of AF LookUp Table */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 430 | #define CAN_EndofTable(n) ((uint32_t)((n&3FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 431 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 432 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 433 | * Macro defines for LUT Error Address Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 434 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 435 | /** CAN Look-Up Table Error Address */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 436 | #define CAN_LUTerrAd(n) ((uint32_t)((n&1FF)<<2)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 437 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 438 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 439 | * Macro defines for LUT Error Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 440 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 441 | /** CAN Look-Up Table Error */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 442 | #define CAN_LUTerr ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 443 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 444 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 445 | * Macro defines for Global FullCANInterrupt Enable Register |
| Michael J. Spencer |
2:1df0b61d3b5a | 446 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 447 | /** Global FullCANInterrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 448 | #define CAN_FCANIE ((uint32_t)(1)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 449 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 450 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 451 | * Macro defines for FullCAN Interrupt and Capture Register 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 452 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 453 | /** FullCAN Interrupt and Capture (0-31)*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 454 | #define CAN_FCANIC0_IntPnd(n) ((uint32_t)(1<<n)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 455 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 456 | /*********************************************************************//** |
| Michael J. Spencer |
2:1df0b61d3b5a | 457 | * Macro defines for FullCAN Interrupt and Capture Register 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 458 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 459 | /** FullCAN Interrupt and Capture (0-31)*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 460 | #define CAN_FCANIC1_IntPnd(n) ((uint32_t)(1<<(n-32))) |
| Michael J. Spencer |
2:1df0b61d3b5a | 461 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 462 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 463 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 464 | /** Macro to determine if it is valid CAN peripheral or not */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 465 | #define PARAM_CANx(x) ((((uint32_t*)x)==((uint32_t *)LPC_CAN1)) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 466 | ||(((uint32_t*)x)==((uint32_t *)LPC_CAN2))) |
| Michael J. Spencer |
2:1df0b61d3b5a | 467 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 468 | /* Macro to determine if it is valid CANAF or not*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 469 | #define PARAM_CANAFx(x) (((uint32_t*)x)== ((uint32_t*)LPC_CANAF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 470 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 471 | /* Macro to determine if it is valid CANAF RAM or not*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 472 | #define PARAM_CANAFRAMx(x) (((uint32_t*)x)== (uint32_t*)LPC_CANAF_RAM) |
| Michael J. Spencer |
2:1df0b61d3b5a | 473 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 474 | /* Macro to determine if it is valid CANCR or not*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 475 | #define PARAM_CANCRx(x) (((uint32_t*)x)==((uint32_t*)LPC_CANCR)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 476 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 477 | /** Macro to check Data to send valid */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 478 | #define PARAM_I2S_DATA(data) ((data>=0)&&(data <= 0xFFFFFFFF)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 479 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 480 | /** Macro to check frequency value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 481 | #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 482 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 483 | /** Macro to check Frame Identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 484 | #define PARAM_ID_11(n) ((n>>11)==0) /*-- 11 bit --*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 485 | #define PARAM_ID_29(n) ((n>>29)==0) /*-- 29 bit --*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 486 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 487 | /** Macro to check DLC value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 488 | #define PARAM_DLC(n) ((n>>4)==0) /*-- 4 bit --*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 489 | /** Macro to check ID format type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 490 | #define PARAM_ID_FORMAT(n) ((n==STD_ID_FORMAT)||(n==EXT_ID_FORMAT)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 491 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 492 | /** Macro to check Group identifier */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 493 | #define PARAM_GRP_ID(x, y) ((x<=y)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 494 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 495 | /** Macro to check Frame type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 496 | #define PARAM_FRAME_TYPE(n) ((n==DATA_FRAME)||(n==REMOTE_FRAME)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 497 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 498 | /** Macro to check Control/Central Status type parameter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 499 | #define PARAM_CTRL_STS_TYPE(n) ((n==CANCTRL_GLOBAL_STS)||(n==CANCTRL_INT_CAP) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 500 | ||(n==CANCTRL_ERR_WRN)||(n==CANCTRL_STS)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 501 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 502 | /** Macro to check CR status type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 503 | #define PARAM_CR_STS_TYPE(n) ((n==CANCR_TX_STS)||(n==CANCR_RX_STS) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 504 | ||(n==CANCR_MS)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 505 | /** Macro to check AF Mode type parameter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 506 | #define PARAM_AFMODE_TYPE(n) ((n==CAN_Normal)||(n==CAN_AccOff) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 507 | ||(n==CAN_AccBP)||(n==CAN_eFCAN)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 508 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 509 | /** Macro to check Operation Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 510 | #define PARAM_MODE_TYPE(n) ((n==CAN_OPERATING_MODE)||(n==CAN_RESET_MODE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 511 | ||(n==CAN_LISTENONLY_MODE)||(n==CAN_SELFTEST_MODE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 512 | ||(n==CAN_TXPRIORITY_MODE)||(n==CAN_SLEEP_MODE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 513 | ||(n==CAN_RXPOLARITY_MODE)||(n==CAN_TEST_MODE)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 514 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 515 | /** Macro define for struct AF_Section parameter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 516 | #define PARAM_CTRL(n) ((n==CAN1_CTRL)|(n==CAN2_CTRL)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 517 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 518 | /** Macro define for struct AF_Section parameter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 519 | #define PARAM_MSG_DISABLE(n) ((n==MSG_ENABLE)|(n==MSG_DISABLE)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 520 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 521 | /**Macro to check Interrupt Type parameter */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 522 | #define PARAM_INT_EN_TYPE(n) ((n==CANINT_RIE)||(n==CANINT_TIE1) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 523 | ||(n==CANINT_EIE)||(n==CANINT_DOIE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 524 | ||(n==CANINT_WUIE)||(n==CANINT_EPIE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 525 | ||(n==CANINT_ALIE)||(n==CANINT_BEIE) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 526 | ||(n==CANINT_IDIE)||(n==CANINT_TIE2) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 527 | ||(n==CANINT_TIE3)||(n==CANINT_FCE)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 528 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 529 | /** Macro to check AFLUT Entry type */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 530 | #define PARAM_AFLUT_ENTRY_TYPE(n) ((n==FULLCAN_ENTRY)||(n==EXPLICIT_STANDARD_ENTRY)\ |
| Michael J. Spencer |
2:1df0b61d3b5a | 531 | ||(n==GROUP_STANDARD_ENTRY)||(n==EXPLICIT_EXTEND_ENTRY) \ |
| Michael J. Spencer |
2:1df0b61d3b5a | 532 | ||(n==GROUP_EXTEND_ENTRY)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 533 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 534 | /** Macro to check position */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 535 | #define PARAM_POSITION(n) ((n>=0)&&(n<512)) |
| Michael J. Spencer |
2:1df0b61d3b5a | 536 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 537 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 538 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 539 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 540 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 541 | /* Public Types --------------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 542 | /** @defgroup CAN_Public_Types CAN Public Types |
| Michael J. Spencer |
2:1df0b61d3b5a | 543 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 544 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 545 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 546 | /** CAN configuration structure */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 547 | /*********************************************************************** |
| Michael J. Spencer |
2:1df0b61d3b5a | 548 | * CAN device configuration commands (IOCTL commands and arguments) |
| Michael J. Spencer |
2:1df0b61d3b5a | 549 | **********************************************************************/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 550 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 551 | * @brief CAN ID format definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 552 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 553 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 554 | STD_ID_FORMAT = 0, /**< Use standard ID format (11 bit ID) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 555 | EXT_ID_FORMAT = 1 /**< Use extended ID format (29 bit ID) */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 556 | } CAN_ID_FORMAT_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 557 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 558 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 559 | * @brief AFLUT Entry type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 560 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 561 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 562 | FULLCAN_ENTRY = 0, |
| Michael J. Spencer |
2:1df0b61d3b5a | 563 | EXPLICIT_STANDARD_ENTRY, |
| Michael J. Spencer |
2:1df0b61d3b5a | 564 | GROUP_STANDARD_ENTRY, |
| Michael J. Spencer |
2:1df0b61d3b5a | 565 | EXPLICIT_EXTEND_ENTRY, |
| Michael J. Spencer |
2:1df0b61d3b5a | 566 | GROUP_EXTEND_ENTRY |
| Michael J. Spencer |
2:1df0b61d3b5a | 567 | } AFLUT_ENTRY_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 568 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 569 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 570 | * @brief Symbolic names for type of CAN message |
| Michael J. Spencer |
2:1df0b61d3b5a | 571 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 572 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 573 | DATA_FRAME = 0, /**< Data frame */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 574 | REMOTE_FRAME = 1 /**< Remote frame */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 575 | } CAN_FRAME_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 576 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 577 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 578 | * @brief CAN Control status definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 579 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 580 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 581 | CANCTRL_GLOBAL_STS = 0, /**< CAN Global Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 582 | CANCTRL_INT_CAP, /**< CAN Interrupt and Capture */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 583 | CANCTRL_ERR_WRN, /**< CAN Error Warning Limit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 584 | CANCTRL_STS /**< CAN Control Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 585 | } CAN_CTRL_STS_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 586 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 587 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 588 | * @brief Central CAN status type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 589 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 590 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 591 | CANCR_TX_STS = 0, /**< Central CAN Tx Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 592 | CANCR_RX_STS, /**< Central CAN Rx Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 593 | CANCR_MS /**< Central CAN Miscellaneous Status */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 594 | } CAN_CR_STS_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 595 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 596 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 597 | * @brief FullCAN Interrupt Capture type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 598 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 599 | typedef enum{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 600 | FULLCAN_IC0, /**< FullCAN Interrupt and Capture 0 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 601 | FULLCAN_IC1 /**< FullCAN Interrupt and Capture 1 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 602 | }FullCAN_IC_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 603 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 604 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 605 | * @brief CAN interrupt enable type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 606 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 607 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 608 | CANINT_RIE = 0, /**< CAN Receiver Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 609 | CANINT_TIE1, /**< CAN Transmit Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 610 | CANINT_EIE, /**< CAN Error Warning Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 611 | CANINT_DOIE, /**< CAN Data Overrun Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 612 | CANINT_WUIE, /**< CAN Wake-Up Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 613 | CANINT_EPIE, /**< CAN Error Passive Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 614 | CANINT_ALIE, /**< CAN Arbitration Lost Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 615 | CANINT_BEIE, /**< CAN Bus Error Inter rupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 616 | CANINT_IDIE, /**< CAN ID Ready Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 617 | CANINT_TIE2, /**< CAN Transmit Interrupt Enable for Buffer2 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 618 | CANINT_TIE3, /**< CAN Transmit Interrupt Enable for Buffer3 */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 619 | CANINT_FCE /**< FullCAN Interrupt Enable */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 620 | } CAN_INT_EN_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 621 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 622 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 623 | * @brief Acceptance Filter Mode type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 624 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 625 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 626 | CAN_Normal = 0, /**< Normal Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 627 | CAN_AccOff, /**< Acceptance Filter Off Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 628 | CAN_AccBP, /**< Acceptance Fileter Bypass Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 629 | CAN_eFCAN /**< FullCAN Mode Enhancement */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 630 | } CAN_AFMODE_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 631 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 632 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 633 | * @brief CAN Mode Type definition |
| Michael J. Spencer |
2:1df0b61d3b5a | 634 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 635 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 636 | CAN_OPERATING_MODE = 0, /**< Operating Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 637 | CAN_RESET_MODE, /**< Reset Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 638 | CAN_LISTENONLY_MODE, /**< Listen Only Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 639 | CAN_SELFTEST_MODE, /**< Seft Test Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 640 | CAN_TXPRIORITY_MODE, /**< Transmit Priority Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 641 | CAN_SLEEP_MODE, /**< Sleep Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 642 | CAN_RXPOLARITY_MODE, /**< Receive Polarity Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 643 | CAN_TEST_MODE /**< Test Mode */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 644 | } CAN_MODE_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 645 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 646 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 647 | * @brief Error values that functions can return |
| Michael J. Spencer |
2:1df0b61d3b5a | 648 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 649 | typedef enum { |
| Michael J. Spencer |
2:1df0b61d3b5a | 650 | CAN_OK = 1, /**< No error */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 651 | CAN_OBJECTS_FULL_ERROR, /**< No more rx or tx objects available */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 652 | CAN_FULL_OBJ_NOT_RCV, /**< Full CAN object not received */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 653 | CAN_NO_RECEIVE_DATA, /**< No have receive data available */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 654 | CAN_AF_ENTRY_ERROR, /**< Entry load in AFLUT is unvalid */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 655 | CAN_CONFLICT_ID_ERROR, /**< Conflict ID occur */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 656 | CAN_ENTRY_NOT_EXIT_ERROR /**< Entry remove outo AFLUT is not exit */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 657 | } CAN_ERROR; |
| Michael J. Spencer |
2:1df0b61d3b5a | 658 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 659 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 660 | * @brief Pin Configuration structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 661 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 662 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 663 | uint8_t RD; /**< Serial Inputs, from CAN transceivers, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 664 | ** For CAN1: |
| Michael J. Spencer |
2:1df0b61d3b5a | 665 | - CAN_RD1_P0_0: RD pin is on P0.0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 666 | - CAN_RD1_P0_21 : RD pin is on P0.21 |
| Michael J. Spencer |
2:1df0b61d3b5a | 667 | ** For CAN2: |
| Michael J. Spencer |
2:1df0b61d3b5a | 668 | - CAN_RD2_P0_4: RD pin is on P0.4 |
| Michael J. Spencer |
2:1df0b61d3b5a | 669 | - CAN_RD2_P2_7: RD pin is on P2.7 |
| Michael J. Spencer |
2:1df0b61d3b5a | 670 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 671 | uint8_t TD; /**< Serial Outputs, To CAN transceivers, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 672 | ** For CAN1: |
| Michael J. Spencer |
2:1df0b61d3b5a | 673 | - CAN_TD1_P0_1: TD pin is on P0.1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 674 | - CAN_TD1_P0_22: TD pin is on P0.22 |
| Michael J. Spencer |
2:1df0b61d3b5a | 675 | ** For CAN2: |
| Michael J. Spencer |
2:1df0b61d3b5a | 676 | - CAN_TD2_P0_5: TD pin is on P0.5 |
| Michael J. Spencer |
2:1df0b61d3b5a | 677 | - CAN_TD2_P2_8: TD pin is on P2.8 |
| Michael J. Spencer |
2:1df0b61d3b5a | 678 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 679 | } CAN_PinCFG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 680 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 681 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 682 | * @brief CAN message object structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 683 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 684 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 685 | uint32_t id; /**< 29 bit identifier, it depend on "format" value |
| Michael J. Spencer |
2:1df0b61d3b5a | 686 | - if format = STD_ID_FORMAT, id should be 11 bit identifier |
| Michael J. Spencer |
2:1df0b61d3b5a | 687 | - if format = EXT_ID_FORMAT, id should be 29 bit identifier |
| Michael J. Spencer |
2:1df0b61d3b5a | 688 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 689 | uint8_t dataA[4]; /**< Data field A */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 690 | uint8_t dataB[4]; /**< Data field B */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 691 | uint8_t len; /**< Length of data field in bytes, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 692 | - 0000b-0111b: 0-7 bytes |
| Michael J. Spencer |
2:1df0b61d3b5a | 693 | - 1xxxb: 8 bytes |
| Michael J. Spencer |
2:1df0b61d3b5a | 694 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 695 | uint8_t format; /**< Identifier Format, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 696 | - STD_ID_FORMAT: Standard ID - 11 bit format |
| Michael J. Spencer |
2:1df0b61d3b5a | 697 | - EXT_ID_FORMAT: Extended ID - 29 bit format |
| Michael J. Spencer |
2:1df0b61d3b5a | 698 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 699 | uint8_t type; /**< Remote Frame transmission, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 700 | - DATA_FRAME: the number of data bytes called out by the DLC |
| Michael J. Spencer |
2:1df0b61d3b5a | 701 | field are send from the CANxTDA and CANxTDB registers |
| Michael J. Spencer |
2:1df0b61d3b5a | 702 | - REMOTE_FRAME: Remote Frame is sent |
| Michael J. Spencer |
2:1df0b61d3b5a | 703 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 704 | } CAN_MSG_Type; |
| Michael J. Spencer |
2:1df0b61d3b5a | 705 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 706 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 707 | * @brief FullCAN Entry structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 708 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 709 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 710 | uint8_t controller; /**< CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 711 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 712 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 713 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 714 | uint8_t disable; /**< Disable bit, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 715 | - MSG_ENABLE: disable bit = 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 716 | - MSG_DISABLE: disable bit = 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 717 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 718 | uint16_t id_11; /**< Standard ID, should be 11-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 719 | } FullCAN_Entry; |
| Michael J. Spencer |
2:1df0b61d3b5a | 720 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 721 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 722 | * @brief Standard ID Frame Format Entry structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 723 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 724 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 725 | uint8_t controller; /**< CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 726 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 727 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 728 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 729 | uint8_t disable; /**< Disable bit, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 730 | - MSG_ENABLE: disable bit = 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 731 | - MSG_DISABLE: disable bit = 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 732 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 733 | uint16_t id_11; /**< Standard ID, should be 11-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 734 | } SFF_Entry; |
| Michael J. Spencer |
2:1df0b61d3b5a | 735 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 736 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 737 | * @brief Group of Standard ID Frame Format Entry structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 738 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 739 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 740 | uint8_t controller1; /**< First CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 741 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 742 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 743 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 744 | uint8_t disable1; /**< First Disable bit, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 745 | - MSG_ENABLE: disable bit = 0) |
| Michael J. Spencer |
2:1df0b61d3b5a | 746 | - MSG_DISABLE: disable bit = 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 747 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 748 | uint16_t lowerID; /**< ID lower bound, should be 11-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 749 | uint8_t controller2; /**< Second CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 750 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 751 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 752 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 753 | uint8_t disable2; /**< Second Disable bit, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 754 | - MSG_ENABLE: disable bit = 0 |
| Michael J. Spencer |
2:1df0b61d3b5a | 755 | - MSG_DISABLE: disable bit = 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 756 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 757 | uint16_t upperID; /**< ID upper bound, should be 11-bit value and |
| Michael J. Spencer |
2:1df0b61d3b5a | 758 | equal or greater than lowerID |
| Michael J. Spencer |
2:1df0b61d3b5a | 759 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 760 | } SFF_GPR_Entry; |
| Michael J. Spencer |
2:1df0b61d3b5a | 761 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 762 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 763 | * @brief Extended ID Frame Format Entry structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 764 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 765 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 766 | uint8_t controller; /**< CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 767 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 768 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 769 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 770 | uint32_t ID_29; /**< Extend ID, shoud be 29-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 771 | } EFF_Entry; |
| Michael J. Spencer |
2:1df0b61d3b5a | 772 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 773 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 774 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 775 | * @brief Group of Extended ID Frame Format Entry structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 776 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 777 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 778 | uint8_t controller1; /**< First CAN Controller, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 779 | - CAN1_CTRL: CAN1 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 780 | - CAN2_CTRL: CAN2 Controller |
| Michael J. Spencer |
2:1df0b61d3b5a | 781 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 782 | uint8_t controller2; /**< Second Disable bit, should be: |
| Michael J. Spencer |
2:1df0b61d3b5a | 783 | - MSG_ENABLE: disable bit = 0(default) |
| Michael J. Spencer |
2:1df0b61d3b5a | 784 | - MSG_DISABLE: disable bit = 1 |
| Michael J. Spencer |
2:1df0b61d3b5a | 785 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 786 | uint32_t lowerEID; /**< Extended ID lower bound, should be 29-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 787 | uint32_t upperEID; /**< Extended ID upper bound, should be 29-bit value */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 788 | } EFF_GPR_Entry; |
| Michael J. Spencer |
2:1df0b61d3b5a | 789 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 790 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 791 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 792 | * @brief Acceptance Filter Section Table structure |
| Michael J. Spencer |
2:1df0b61d3b5a | 793 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 794 | typedef struct { |
| Michael J. Spencer |
2:1df0b61d3b5a | 795 | FullCAN_Entry* FullCAN_Sec; /**< The pointer point to FullCAN_Entry */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 796 | uint8_t FC_NumEntry; /**< FullCAN Entry Number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 797 | SFF_Entry* SFF_Sec; /**< The pointer point to SFF_Entry */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 798 | uint8_t SFF_NumEntry; /**< Standard ID Entry Number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 799 | SFF_GPR_Entry* SFF_GPR_Sec; /**< The pointer point to SFF_GPR_Entry */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 800 | uint8_t SFF_GPR_NumEntry; /**< Group Standard ID Entry Number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 801 | EFF_Entry* EFF_Sec; /**< The pointer point to EFF_Entry */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 802 | uint8_t EFF_NumEntry; /**< Extended ID Entry Number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 803 | EFF_GPR_Entry* EFF_GPR_Sec; /**< The pointer point to EFF_GPR_Entry */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 804 | uint8_t EFF_GPR_NumEntry; /**< Group Extended ID Entry Number */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 805 | } AF_SectionDef; |
| Michael J. Spencer |
2:1df0b61d3b5a | 806 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 807 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 808 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 809 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 810 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 811 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 812 | /* Public Functions ----------------------------------------------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 813 | /** @defgroup CAN_Public_Functions CAN Public Functions |
| Michael J. Spencer |
2:1df0b61d3b5a | 814 | * @{ |
| Michael J. Spencer |
2:1df0b61d3b5a | 815 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 816 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 817 | /* Init/DeInit CAN peripheral -----------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 818 | void CAN_Init(LPC_CAN_TypeDef *CANx, uint32_t baudrate); |
| Michael J. Spencer |
2:1df0b61d3b5a | 819 | void CAN_DeInit(LPC_CAN_TypeDef *CANx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 820 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 821 | /* CAN messages functions ---------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 822 | Status CAN_SendMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 823 | Status CAN_ReceiveMsg(LPC_CAN_TypeDef *CANx, CAN_MSG_Type *CAN_Msg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 824 | CAN_ERROR FCAN_ReadObj(LPC_CANAF_TypeDef* CANAFx, CAN_MSG_Type *CAN_Msg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 825 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 826 | /* CAN configure functions ---------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 827 | void CAN_ModeConfig(LPC_CAN_TypeDef* CANx, CAN_MODE_Type mode, |
| Michael J. Spencer |
2:1df0b61d3b5a | 828 | FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 829 | void CAN_SetAFMode(LPC_CANAF_TypeDef* CANAFx, CAN_AFMODE_Type AFmode); |
| Michael J. Spencer |
2:1df0b61d3b5a | 830 | void CAN_SetCommand(LPC_CAN_TypeDef* CANx, uint32_t CMRType); |
| Michael J. Spencer |
2:1df0b61d3b5a | 831 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 832 | /* AFLUT functions ---------------------- */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 833 | CAN_ERROR CAN_SetupAFLUT(LPC_CANAF_TypeDef* CANAFx, AF_SectionDef* AFSection); |
| Michael J. Spencer |
2:1df0b61d3b5a | 834 | CAN_ERROR CAN_LoadFullCANEntry(LPC_CAN_TypeDef* CANx, uint16_t ID); |
| Michael J. Spencer |
2:1df0b61d3b5a | 835 | CAN_ERROR CAN_LoadExplicitEntry(LPC_CAN_TypeDef* CANx, uint32_t ID, |
| Michael J. Spencer |
2:1df0b61d3b5a | 836 | CAN_ID_FORMAT_Type format); |
| Michael J. Spencer |
2:1df0b61d3b5a | 837 | CAN_ERROR CAN_LoadGroupEntry(LPC_CAN_TypeDef* CANx, uint32_t lowerID, |
| Michael J. Spencer |
2:1df0b61d3b5a | 838 | uint32_t upperID, CAN_ID_FORMAT_Type format); |
| Michael J. Spencer |
2:1df0b61d3b5a | 839 | CAN_ERROR CAN_RemoveEntry(AFLUT_ENTRY_Type EntryType, uint16_t position); |
| Michael J. Spencer |
2:1df0b61d3b5a | 840 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 841 | /* CAN interrupt functions -----------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 842 | void CAN_IRQCmd(LPC_CAN_TypeDef* CANx, CAN_INT_EN_Type arg, FunctionalState NewState); |
| Michael J. Spencer |
2:1df0b61d3b5a | 843 | uint32_t CAN_IntGetStatus(LPC_CAN_TypeDef* CANx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 844 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 845 | /* CAN get status functions ----------------*/ |
| Michael J. Spencer |
2:1df0b61d3b5a | 846 | IntStatus CAN_FullCANIntGetStatus (LPC_CANAF_TypeDef* CANAFx); |
| Michael J. Spencer |
2:1df0b61d3b5a | 847 | uint32_t CAN_FullCANPendGetStatus (LPC_CANAF_TypeDef* CANAFx, FullCAN_IC_Type type); |
| Michael J. Spencer |
2:1df0b61d3b5a | 848 | uint32_t CAN_GetCTRLStatus(LPC_CAN_TypeDef* CANx, CAN_CTRL_STS_Type arg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 849 | uint32_t CAN_GetCRStatus(LPC_CANCR_TypeDef* CANCRx, CAN_CR_STS_Type arg); |
| Michael J. Spencer |
2:1df0b61d3b5a | 850 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 851 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 852 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 853 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 854 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 855 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 856 | #ifdef __cplusplus |
| Michael J. Spencer |
2:1df0b61d3b5a | 857 | } |
| Michael J. Spencer |
2:1df0b61d3b5a | 858 | #endif |
| Michael J. Spencer |
2:1df0b61d3b5a | 859 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 860 | #endif /* LPC17XX_CAN_H_ */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 861 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 862 | /** |
| Michael J. Spencer |
2:1df0b61d3b5a | 863 | * @} |
| Michael J. Spencer |
2:1df0b61d3b5a | 864 | */ |
| Michael J. Spencer |
2:1df0b61d3b5a | 865 | |
| Michael J. Spencer |
2:1df0b61d3b5a | 866 | /* --------------------------------- End Of File ------------------------------ */ |