Michael Spencer / Smoothie

Fork of Smoothie to port to mbed non-LPC targets.

Dependencies:   mbed

Fork of Smoothie by Stéphane Cachat

libs/LPC17xx/LPC17xxLib/inc/lpc17xx_adc.h@2:1df0b61d3b5a, 2014-02-28 (annotated)

Committer:
Michael J. Spencer
Date:
Fri Feb 28 18:52:52 2014 -0800
Revision:
2:1df0b61d3b5a
Update to latest Smoothie.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Michael J. Spencer 2:1df0b61d3b5a 1 /**********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 2 * $Id$ lpc17xx_adc.h 2008-07-27
Michael J. Spencer 2:1df0b61d3b5a 3 *//**
Michael J. Spencer 2:1df0b61d3b5a 4 * @file lpc17xx_adc.h
Michael J. Spencer 2:1df0b61d3b5a 5 * @brief Contains the NXP ABL typedefs for C standard types.
Michael J. Spencer 2:1df0b61d3b5a 6 * It is intended to be used in ISO C conforming development
Michael J. Spencer 2:1df0b61d3b5a 7 * environments and checks for this insofar as it is possible
Michael J. Spencer 2:1df0b61d3b5a 8 * to do so.
Michael J. Spencer 2:1df0b61d3b5a 9 * @version 2.0
Michael J. Spencer 2:1df0b61d3b5a 10 * @date 27 Jul. 2008
Michael J. Spencer 2:1df0b61d3b5a 11 * @author NXP MCU SW Application Team
Michael J. Spencer 2:1df0b61d3b5a 12 *
Michael J. Spencer 2:1df0b61d3b5a 13 * Copyright(C) 2008, NXP Semiconductor
Michael J. Spencer 2:1df0b61d3b5a 14 * All rights reserved.
Michael J. Spencer 2:1df0b61d3b5a 15 *
Michael J. Spencer 2:1df0b61d3b5a 16 ***********************************************************************
Michael J. Spencer 2:1df0b61d3b5a 17 * Software that is described herein is for illustrative purposes only
Michael J. Spencer 2:1df0b61d3b5a 18 * which provides customers with programming information regarding the
Michael J. Spencer 2:1df0b61d3b5a 19 * products. This software is supplied "AS IS" without any warranties.
Michael J. Spencer 2:1df0b61d3b5a 20 * NXP Semiconductors assumes no responsibility or liability for the
Michael J. Spencer 2:1df0b61d3b5a 21 * use of the software, conveys no license or title under any patent,
Michael J. Spencer 2:1df0b61d3b5a 22 * copyright, or mask work right to the product. NXP Semiconductors
Michael J. Spencer 2:1df0b61d3b5a 23 * reserves the right to make changes in the software without
Michael J. Spencer 2:1df0b61d3b5a 24 * notification. NXP Semiconductors also make no representation or
Michael J. Spencer 2:1df0b61d3b5a 25 * warranty that such application will be suitable for the specified
Michael J. Spencer 2:1df0b61d3b5a 26 * use without further testing or modification.
Michael J. Spencer 2:1df0b61d3b5a 27 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 28
Michael J. Spencer 2:1df0b61d3b5a 29 /* Peripheral group ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 30 /** @defgroup ADC ADC (Analog-to-Digital Converter)
Michael J. Spencer 2:1df0b61d3b5a 31 * @ingroup LPC1700CMSIS_FwLib_Drivers
Michael J. Spencer 2:1df0b61d3b5a 32 * @{
Michael J. Spencer 2:1df0b61d3b5a 33 */
Michael J. Spencer 2:1df0b61d3b5a 34
Michael J. Spencer 2:1df0b61d3b5a 35 #ifndef LPC17XX_ADC_H_
Michael J. Spencer 2:1df0b61d3b5a 36 #define LPC17XX_ADC_H_
Michael J. Spencer 2:1df0b61d3b5a 37
Michael J. Spencer 2:1df0b61d3b5a 38 /* Includes ------------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 39 #include "LPC17xx.h"
Michael J. Spencer 2:1df0b61d3b5a 40 #include "lpc_types.h"
Michael J. Spencer 2:1df0b61d3b5a 41
Michael J. Spencer 2:1df0b61d3b5a 42
Michael J. Spencer 2:1df0b61d3b5a 43 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 44 extern "C"
Michael J. Spencer 2:1df0b61d3b5a 45 {
Michael J. Spencer 2:1df0b61d3b5a 46 #endif
Michael J. Spencer 2:1df0b61d3b5a 47
Michael J. Spencer 2:1df0b61d3b5a 48 /* Private macros ------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 49 /** @defgroup ADC_Private_Macros ADC Private Macros
Michael J. Spencer 2:1df0b61d3b5a 50 * @{
Michael J. Spencer 2:1df0b61d3b5a 51 */
Michael J. Spencer 2:1df0b61d3b5a 52
Michael J. Spencer 2:1df0b61d3b5a 53 /* -------------------------- BIT DEFINITIONS ----------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 54 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 55 * Macro defines for ADC control register
Michael J. Spencer 2:1df0b61d3b5a 56 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 57 /** Selects which of the AD0.0:7 pins is (are) to be sampled and converted */
Michael J. Spencer 2:1df0b61d3b5a 58 #define ADC_CR_CH_SEL(n) ((1UL << n))
Michael J. Spencer 2:1df0b61d3b5a 59 /** The APB clock (PCLK) is divided by (this value plus one)
Michael J. Spencer 2:1df0b61d3b5a 60 * to produce the clock for the A/D */
Michael J. Spencer 2:1df0b61d3b5a 61 #define ADC_CR_CLKDIV(n) ((n<<8))
Michael J. Spencer 2:1df0b61d3b5a 62 /** Repeated conversions A/D enable bit */
Michael J. Spencer 2:1df0b61d3b5a 63 #define ADC_CR_BURST ((1UL<<16))
Michael J. Spencer 2:1df0b61d3b5a 64 /** ADC convert in power down mode */
Michael J. Spencer 2:1df0b61d3b5a 65 #define ADC_CR_PDN ((1UL<<21))
Michael J. Spencer 2:1df0b61d3b5a 66 /** Start mask bits */
Michael J. Spencer 2:1df0b61d3b5a 67 #define ADC_CR_START_MASK ((7UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 68 /** Select Start Mode */
Michael J. Spencer 2:1df0b61d3b5a 69 #define ADC_CR_START_MODE_SEL(SEL) ((SEL<<24))
Michael J. Spencer 2:1df0b61d3b5a 70 /** Start conversion now */
Michael J. Spencer 2:1df0b61d3b5a 71 #define ADC_CR_START_NOW ((1UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 72 /** Start conversion when the edge selected by bit 27 occurs on P2.10/EINT0 */
Michael J. Spencer 2:1df0b61d3b5a 73 #define ADC_CR_START_EINT0 ((2UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 74 /** Start conversion when the edge selected by bit 27 occurs on P1.27/CAP0.1 */
Michael J. Spencer 2:1df0b61d3b5a 75 #define ADC_CR_START_CAP01 ((3UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 76 /** Start conversion when the edge selected by bit 27 occurs on MAT0.1 */
Michael J. Spencer 2:1df0b61d3b5a 77 #define ADC_CR_START_MAT01 ((4UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 78 /** Start conversion when the edge selected by bit 27 occurs on MAT0.3 */
Michael J. Spencer 2:1df0b61d3b5a 79 #define ADC_CR_START_MAT03 ((5UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 80 /** Start conversion when the edge selected by bit 27 occurs on MAT1.0 */
Michael J. Spencer 2:1df0b61d3b5a 81 #define ADC_CR_START_MAT10 ((6UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 82 /** Start conversion when the edge selected by bit 27 occurs on MAT1.1 */
Michael J. Spencer 2:1df0b61d3b5a 83 #define ADC_CR_START_MAT11 ((7UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 84 /** Start conversion on a falling edge on the selected CAP/MAT signal */
Michael J. Spencer 2:1df0b61d3b5a 85 #define ADC_CR_EDGE ((1UL<<27))
Michael J. Spencer 2:1df0b61d3b5a 86
Michael J. Spencer 2:1df0b61d3b5a 87 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 88 * Macro defines for ADC Global Data register
Michael J. Spencer 2:1df0b61d3b5a 89 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 90 /** When DONE is 1, this field contains result value of ADC conversion */
Michael J. Spencer 2:1df0b61d3b5a 91 #define ADC_GDR_RESULT(n) (((n>>4)&0xFFF))
Michael J. Spencer 2:1df0b61d3b5a 92 /** These bits contain the channel from which the LS bits were converted */
Michael J. Spencer 2:1df0b61d3b5a 93 #define ADC_GDR_CH(n) (((n>>24)&0x7))
Michael J. Spencer 2:1df0b61d3b5a 94 /** This bit is 1 in burst mode if the results of one or
Michael J. Spencer 2:1df0b61d3b5a 95 * more conversions was (were) lost */
Michael J. Spencer 2:1df0b61d3b5a 96 #define ADC_GDR_OVERRUN_FLAG ((1UL<<30))
Michael J. Spencer 2:1df0b61d3b5a 97 /** This bit is set to 1 when an A/D conversion completes */
Michael J. Spencer 2:1df0b61d3b5a 98 #define ADC_GDR_DONE_FLAG ((1UL<<31))
Michael J. Spencer 2:1df0b61d3b5a 99
Michael J. Spencer 2:1df0b61d3b5a 100 /** This bits is used to mask for Channel */
Michael J. Spencer 2:1df0b61d3b5a 101 #define ADC_GDR_CH_MASK ((7UL<<24))
Michael J. Spencer 2:1df0b61d3b5a 102 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 103 * Macro defines for ADC Interrupt register
Michael J. Spencer 2:1df0b61d3b5a 104 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 105 /** These bits allow control over which A/D channels generate
Michael J. Spencer 2:1df0b61d3b5a 106 * interrupts for conversion completion */
Michael J. Spencer 2:1df0b61d3b5a 107 #define ADC_INTEN_CH(n) ((1UL<<n))
Michael J. Spencer 2:1df0b61d3b5a 108 /** When 1, enables the global DONE flag in ADDR to generate an interrupt */
Michael J. Spencer 2:1df0b61d3b5a 109 #define ADC_INTEN_GLOBAL ((1UL<<8))
Michael J. Spencer 2:1df0b61d3b5a 110
Michael J. Spencer 2:1df0b61d3b5a 111 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 112 * Macro defines for ADC Data register
Michael J. Spencer 2:1df0b61d3b5a 113 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 114 /** When DONE is 1, this field contains result value of ADC conversion */
Michael J. Spencer 2:1df0b61d3b5a 115 #define ADC_DR_RESULT(n) (((n>>4)&0xFFF))
Michael J. Spencer 2:1df0b61d3b5a 116 /** These bits mirror the OVERRRUN status flags that appear in the
Michael J. Spencer 2:1df0b61d3b5a 117 * result register for each A/D channel */
Michael J. Spencer 2:1df0b61d3b5a 118 #define ADC_DR_OVERRUN_FLAG ((1UL<<30))
Michael J. Spencer 2:1df0b61d3b5a 119 /** This bit is set to 1 when an A/D conversion completes. It is cleared
Michael J. Spencer 2:1df0b61d3b5a 120 * when this register is read */
Michael J. Spencer 2:1df0b61d3b5a 121 #define ADC_DR_DONE_FLAG ((1UL<<31))
Michael J. Spencer 2:1df0b61d3b5a 122
Michael J. Spencer 2:1df0b61d3b5a 123 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 124 * Macro defines for ADC Status register
Michael J. Spencer 2:1df0b61d3b5a 125 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 126 /** These bits mirror the DONE status flags that appear in the result
Michael J. Spencer 2:1df0b61d3b5a 127 * register for each A/D channel */
Michael J. Spencer 2:1df0b61d3b5a 128 #define ADC_STAT_CH_DONE_FLAG(n) ((n&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 129 /** These bits mirror the OVERRRUN status flags that appear in the
Michael J. Spencer 2:1df0b61d3b5a 130 * result register for each A/D channel */
Michael J. Spencer 2:1df0b61d3b5a 131 #define ADC_STAT_CH_OVERRUN_FLAG(n) (((n>>8)&0xFF))
Michael J. Spencer 2:1df0b61d3b5a 132 /** This bit is the A/D interrupt flag */
Michael J. Spencer 2:1df0b61d3b5a 133 #define ADC_STAT_INT_FLAG ((1UL<<16))
Michael J. Spencer 2:1df0b61d3b5a 134
Michael J. Spencer 2:1df0b61d3b5a 135 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 136 * Macro defines for ADC Trim register
Michael J. Spencer 2:1df0b61d3b5a 137 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 138 /** Offset trim bits for ADC operation */
Michael J. Spencer 2:1df0b61d3b5a 139 #define ADC_ADCOFFS(n) (((n&0xF)<<4))
Michael J. Spencer 2:1df0b61d3b5a 140 /** Written to boot code*/
Michael J. Spencer 2:1df0b61d3b5a 141 #define ADC_TRIM(n) (((n&0xF)<<8))
Michael J. Spencer 2:1df0b61d3b5a 142
Michael J. Spencer 2:1df0b61d3b5a 143 /* ------------------- CHECK PARAM DEFINITIONS ------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 144 /** Check ADC parameter */
Michael J. Spencer 2:1df0b61d3b5a 145 #define PARAM_ADCx(n) (((uint32_t *)n)==((uint32_t *)LPC_ADC))
Michael J. Spencer 2:1df0b61d3b5a 146
Michael J. Spencer 2:1df0b61d3b5a 147 /** Check ADC state parameter */
Michael J. Spencer 2:1df0b61d3b5a 148 #define PARAM_ADC_START_ON_EDGE_OPT(OPT) ((OPT == ADC_START_ON_RISING)||(OPT == ADC_START_ON_FALLING))
Michael J. Spencer 2:1df0b61d3b5a 149
Michael J. Spencer 2:1df0b61d3b5a 150 /** Check ADC state parameter */
Michael J. Spencer 2:1df0b61d3b5a 151 #define PARAM_ADC_DATA_STATUS(OPT) ((OPT== ADC_DATA_BURST)||(OPT== ADC_DATA_DONE))
Michael J. Spencer 2:1df0b61d3b5a 152
Michael J. Spencer 2:1df0b61d3b5a 153 /** Check ADC rate parameter */
Michael J. Spencer 2:1df0b61d3b5a 154 #define PARAM_ADC_RATE(rate) ((rate>0)&&(rate<=200000))
Michael J. Spencer 2:1df0b61d3b5a 155
Michael J. Spencer 2:1df0b61d3b5a 156 /** Check ADC channel selection parameter */
Michael J. Spencer 2:1df0b61d3b5a 157 #define PARAM_ADC_CHANNEL_SELECTION(SEL) ((SEL == ADC_CHANNEL_0)||(ADC_CHANNEL_1)\
Michael J. Spencer 2:1df0b61d3b5a 158 ||(SEL == ADC_CHANNEL_2)|(ADC_CHANNEL_3)\
Michael J. Spencer 2:1df0b61d3b5a 159 ||(SEL == ADC_CHANNEL_4)||(ADC_CHANNEL_5)\
Michael J. Spencer 2:1df0b61d3b5a 160 ||(SEL == ADC_CHANNEL_6)||(ADC_CHANNEL_7))
Michael J. Spencer 2:1df0b61d3b5a 161
Michael J. Spencer 2:1df0b61d3b5a 162 /** Check ADC start option parameter */
Michael J. Spencer 2:1df0b61d3b5a 163 #define PARAM_ADC_START_OPT(OPT) ((OPT == ADC_START_CONTINUOUS)||(OPT == ADC_START_NOW)\
Michael J. Spencer 2:1df0b61d3b5a 164 ||(OPT == ADC_START_ON_EINT0)||(OPT == ADC_START_ON_CAP01)\
Michael J. Spencer 2:1df0b61d3b5a 165 ||(OPT == ADC_START_ON_MAT01)||(OPT == ADC_START_ON_MAT03)\
Michael J. Spencer 2:1df0b61d3b5a 166 ||(OPT == ADC_START_ON_MAT10)||(OPT == ADC_START_ON_MAT11))
Michael J. Spencer 2:1df0b61d3b5a 167
Michael J. Spencer 2:1df0b61d3b5a 168 /** Check ADC interrupt type parameter */
Michael J. Spencer 2:1df0b61d3b5a 169 #define PARAM_ADC_TYPE_INT_OPT(OPT) ((OPT == ADC_ADINTEN0)||(OPT == ADC_ADINTEN1)\
Michael J. Spencer 2:1df0b61d3b5a 170 ||(OPT == ADC_ADINTEN2)||(OPT == ADC_ADINTEN3)\
Michael J. Spencer 2:1df0b61d3b5a 171 ||(OPT == ADC_ADINTEN4)||(OPT == ADC_ADINTEN5)\
Michael J. Spencer 2:1df0b61d3b5a 172 ||(OPT == ADC_ADINTEN6)||(OPT == ADC_ADINTEN7)\
Michael J. Spencer 2:1df0b61d3b5a 173 ||(OPT == ADC_ADGINTEN))
Michael J. Spencer 2:1df0b61d3b5a 174
Michael J. Spencer 2:1df0b61d3b5a 175 /**
Michael J. Spencer 2:1df0b61d3b5a 176 * @}
Michael J. Spencer 2:1df0b61d3b5a 177 */
Michael J. Spencer 2:1df0b61d3b5a 178
Michael J. Spencer 2:1df0b61d3b5a 179
Michael J. Spencer 2:1df0b61d3b5a 180 /* Public Types --------------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 181 /** @defgroup ADC_Public_Types ADC Public Types
Michael J. Spencer 2:1df0b61d3b5a 182 * @{
Michael J. Spencer 2:1df0b61d3b5a 183 */
Michael J. Spencer 2:1df0b61d3b5a 184
Michael J. Spencer 2:1df0b61d3b5a 185 /*********************************************************************//**
Michael J. Spencer 2:1df0b61d3b5a 186 * @brief ADC enumeration
Michael J. Spencer 2:1df0b61d3b5a 187 **********************************************************************/
Michael J. Spencer 2:1df0b61d3b5a 188 /** @brief Channel Selection */
Michael J. Spencer 2:1df0b61d3b5a 189 typedef enum
Michael J. Spencer 2:1df0b61d3b5a 190 {
Michael J. Spencer 2:1df0b61d3b5a 191 ADC_CHANNEL_0 = 0, /*!< Channel 0 */
Michael J. Spencer 2:1df0b61d3b5a 192 ADC_CHANNEL_1, /*!< Channel 1 */
Michael J. Spencer 2:1df0b61d3b5a 193 ADC_CHANNEL_2, /*!< Channel 2 */
Michael J. Spencer 2:1df0b61d3b5a 194 ADC_CHANNEL_3, /*!< Channel 3 */
Michael J. Spencer 2:1df0b61d3b5a 195 ADC_CHANNEL_4, /*!< Channel 4 */
Michael J. Spencer 2:1df0b61d3b5a 196 ADC_CHANNEL_5, /*!< Channel 5 */
Michael J. Spencer 2:1df0b61d3b5a 197 ADC_CHANNEL_6, /*!< Channel 6 */
Michael J. Spencer 2:1df0b61d3b5a 198 ADC_CHANNEL_7 /*!< Channel 7 */
Michael J. Spencer 2:1df0b61d3b5a 199 }ADC_CHANNEL_SELECTION;
Michael J. Spencer 2:1df0b61d3b5a 200
Michael J. Spencer 2:1df0b61d3b5a 201 /** @brief Type of start option */
Michael J. Spencer 2:1df0b61d3b5a 202 typedef enum
Michael J. Spencer 2:1df0b61d3b5a 203 {
Michael J. Spencer 2:1df0b61d3b5a 204 ADC_START_CONTINUOUS =0, /*!< Continuous mode */
Michael J. Spencer 2:1df0b61d3b5a 205 ADC_START_NOW, /*!< Start conversion now */
Michael J. Spencer 2:1df0b61d3b5a 206 ADC_START_ON_EINT0, /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 207 * by bit 27 occurs on P2.10/EINT0 */
Michael J. Spencer 2:1df0b61d3b5a 208 ADC_START_ON_CAP01, /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 209 * by bit 27 occurs on P1.27/CAP0.1 */
Michael J. Spencer 2:1df0b61d3b5a 210 ADC_START_ON_MAT01, /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 211 * by bit 27 occurs on MAT0.1 */
Michael J. Spencer 2:1df0b61d3b5a 212 ADC_START_ON_MAT03, /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 213 * by bit 27 occurs on MAT0.3 */
Michael J. Spencer 2:1df0b61d3b5a 214 ADC_START_ON_MAT10, /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 215 * by bit 27 occurs on MAT1.0 */
Michael J. Spencer 2:1df0b61d3b5a 216 ADC_START_ON_MAT11 /*!< Start conversion when the edge selected
Michael J. Spencer 2:1df0b61d3b5a 217 * by bit 27 occurs on MAT1.1 */
Michael J. Spencer 2:1df0b61d3b5a 218 } ADC_START_OPT;
Michael J. Spencer 2:1df0b61d3b5a 219
Michael J. Spencer 2:1df0b61d3b5a 220
Michael J. Spencer 2:1df0b61d3b5a 221 /** @brief Type of edge when start conversion on the selected CAP/MAT signal */
Michael J. Spencer 2:1df0b61d3b5a 222 typedef enum
Michael J. Spencer 2:1df0b61d3b5a 223 {
Michael J. Spencer 2:1df0b61d3b5a 224 ADC_START_ON_RISING = 0, /*!< Start conversion on a rising edge
Michael J. Spencer 2:1df0b61d3b5a 225 *on the selected CAP/MAT signal */
Michael J. Spencer 2:1df0b61d3b5a 226 ADC_START_ON_FALLING /*!< Start conversion on a falling edge
Michael J. Spencer 2:1df0b61d3b5a 227 *on the selected CAP/MAT signal */
Michael J. Spencer 2:1df0b61d3b5a 228 } ADC_START_ON_EDGE_OPT;
Michael J. Spencer 2:1df0b61d3b5a 229
Michael J. Spencer 2:1df0b61d3b5a 230 /** @brief* ADC type interrupt enum */
Michael J. Spencer 2:1df0b61d3b5a 231 typedef enum
Michael J. Spencer 2:1df0b61d3b5a 232 {
Michael J. Spencer 2:1df0b61d3b5a 233 ADC_ADINTEN0 = 0, /*!< Interrupt channel 0 */
Michael J. Spencer 2:1df0b61d3b5a 234 ADC_ADINTEN1, /*!< Interrupt channel 1 */
Michael J. Spencer 2:1df0b61d3b5a 235 ADC_ADINTEN2, /*!< Interrupt channel 2 */
Michael J. Spencer 2:1df0b61d3b5a 236 ADC_ADINTEN3, /*!< Interrupt channel 3 */
Michael J. Spencer 2:1df0b61d3b5a 237 ADC_ADINTEN4, /*!< Interrupt channel 4 */
Michael J. Spencer 2:1df0b61d3b5a 238 ADC_ADINTEN5, /*!< Interrupt channel 5 */
Michael J. Spencer 2:1df0b61d3b5a 239 ADC_ADINTEN6, /*!< Interrupt channel 6 */
Michael J. Spencer 2:1df0b61d3b5a 240 ADC_ADINTEN7, /*!< Interrupt channel 7 */
Michael J. Spencer 2:1df0b61d3b5a 241 ADC_ADGINTEN /*!< Individual channel/global flag done generate an interrupt */
Michael J. Spencer 2:1df0b61d3b5a 242 }ADC_TYPE_INT_OPT;
Michael J. Spencer 2:1df0b61d3b5a 243
Michael J. Spencer 2:1df0b61d3b5a 244 /** @brief ADC Data status */
Michael J. Spencer 2:1df0b61d3b5a 245 typedef enum
Michael J. Spencer 2:1df0b61d3b5a 246 {
Michael J. Spencer 2:1df0b61d3b5a 247 ADC_DATA_BURST = 0, /*Burst bit*/
Michael J. Spencer 2:1df0b61d3b5a 248 ADC_DATA_DONE /*Done bit*/
Michael J. Spencer 2:1df0b61d3b5a 249 }ADC_DATA_STATUS;
Michael J. Spencer 2:1df0b61d3b5a 250
Michael J. Spencer 2:1df0b61d3b5a 251 /**
Michael J. Spencer 2:1df0b61d3b5a 252 * @}
Michael J. Spencer 2:1df0b61d3b5a 253 */
Michael J. Spencer 2:1df0b61d3b5a 254
Michael J. Spencer 2:1df0b61d3b5a 255
Michael J. Spencer 2:1df0b61d3b5a 256 /* Public Functions ----------------------------------------------------------- */
Michael J. Spencer 2:1df0b61d3b5a 257 /** @defgroup ADC_Public_Functions ADC Public Functions
Michael J. Spencer 2:1df0b61d3b5a 258 * @{
Michael J. Spencer 2:1df0b61d3b5a 259 */
Michael J. Spencer 2:1df0b61d3b5a 260 /* Init/DeInit ADC peripheral ----------------*/
Michael J. Spencer 2:1df0b61d3b5a 261 void ADC_Init(LPC_ADC_TypeDef *ADCx, uint32_t rate);
Michael J. Spencer 2:1df0b61d3b5a 262 void ADC_DeInit(LPC_ADC_TypeDef *ADCx);
Michael J. Spencer 2:1df0b61d3b5a 263
Michael J. Spencer 2:1df0b61d3b5a 264 /* Enable/Disable ADC functions --------------*/
Michael J. Spencer 2:1df0b61d3b5a 265 void ADC_BurstCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 266 void ADC_PowerdownCmd(LPC_ADC_TypeDef *ADCx, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 267 void ADC_StartCmd(LPC_ADC_TypeDef *ADCx, uint8_t start_mode);
Michael J. Spencer 2:1df0b61d3b5a 268 void ADC_ChannelCmd (LPC_ADC_TypeDef *ADCx, uint8_t Channel, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 269
Michael J. Spencer 2:1df0b61d3b5a 270 /* Configure ADC functions -------------------*/
Michael J. Spencer 2:1df0b61d3b5a 271 void ADC_EdgeStartConfig(LPC_ADC_TypeDef *ADCx, uint8_t EdgeOption);
Michael J. Spencer 2:1df0b61d3b5a 272 void ADC_IntConfig (LPC_ADC_TypeDef *ADCx, ADC_TYPE_INT_OPT IntType, FunctionalState NewState);
Michael J. Spencer 2:1df0b61d3b5a 273
Michael J. Spencer 2:1df0b61d3b5a 274 /* Get ADC information functions -------------------*/
Michael J. Spencer 2:1df0b61d3b5a 275 uint16_t ADC_ChannelGetData(LPC_ADC_TypeDef *ADCx, uint8_t channel);
Michael J. Spencer 2:1df0b61d3b5a 276 FlagStatus ADC_ChannelGetStatus(LPC_ADC_TypeDef *ADCx, uint8_t channel, uint32_t StatusType);
Michael J. Spencer 2:1df0b61d3b5a 277 uint32_t ADC_GlobalGetData(LPC_ADC_TypeDef *ADCx);
Michael J. Spencer 2:1df0b61d3b5a 278 FlagStatus ADC_GlobalGetStatus(LPC_ADC_TypeDef *ADCx, uint32_t StatusType);
Michael J. Spencer 2:1df0b61d3b5a 279
Michael J. Spencer 2:1df0b61d3b5a 280 /**
Michael J. Spencer 2:1df0b61d3b5a 281 * @}
Michael J. Spencer 2:1df0b61d3b5a 282 */
Michael J. Spencer 2:1df0b61d3b5a 283
Michael J. Spencer 2:1df0b61d3b5a 284
Michael J. Spencer 2:1df0b61d3b5a 285 #ifdef __cplusplus
Michael J. Spencer 2:1df0b61d3b5a 286 }
Michael J. Spencer 2:1df0b61d3b5a 287 #endif
Michael J. Spencer 2:1df0b61d3b5a 288
Michael J. Spencer 2:1df0b61d3b5a 289
Michael J. Spencer 2:1df0b61d3b5a 290 #endif /* LPC17XX_ADC_H_ */
Michael J. Spencer 2:1df0b61d3b5a 291
Michael J. Spencer 2:1df0b61d3b5a 292 /**
Michael J. Spencer 2:1df0b61d3b5a 293 * @}
Michael J. Spencer 2:1df0b61d3b5a 294 */
Michael J. Spencer 2:1df0b61d3b5a 295
Michael J. Spencer 2:1df0b61d3b5a 296 /* --------------------------------- End Of File ------------------------------ */