Bernhard Filzmaier / mbed-src

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targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/spi_api.c@443:ed48b4122bfb, 2015-01-12 (annotated)

Committer:
mbed_official
Date:
Mon Jan 12 08:15:07 2015 +0000
Revision:
443:ed48b4122bfb
Parent:
441:d2c15dda23c1
Child:
500:04797f1feae2
Synchronized with git revision 7a3d2b4423a702a090d20403e5209c70f572c84e



Full URL: https://github.com/mbedmicro/mbed/commit/7a3d2b4423a702a090d20403e5209c70f572c84e/



NUCLEO_F070RB - Update tests

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 17 #include <math.h>
mbed_official 390:35c2c1cf29cd 18
mbed_official 390:35c2c1cf29cd 19 #include "spi_api.h"
mbed_official 390:35c2c1cf29cd 20 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 21 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 22 #include "mbed_error.h"
mbed_official 441:d2c15dda23c1 23 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 24
mbed_official 390:35c2c1cf29cd 25 static const PinMap PinMap_SPI_SCLK[] = {
mbed_official 390:35c2c1cf29cd 26 {P10_12, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 27 {P11_12, SPI_1, 2},
mbed_official 441:d2c15dda23c1 28 {P8_3 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 29 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 30 };
mbed_official 390:35c2c1cf29cd 31
mbed_official 390:35c2c1cf29cd 32 static const PinMap PinMap_SPI_SSEL[] = {
mbed_official 390:35c2c1cf29cd 33 {P10_13, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 34 {P11_13, SPI_1, 2},
mbed_official 441:d2c15dda23c1 35 {P8_4 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 36 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 37 };
mbed_official 390:35c2c1cf29cd 38
mbed_official 390:35c2c1cf29cd 39 static const PinMap PinMap_SPI_MOSI[] = {
mbed_official 390:35c2c1cf29cd 40 {P10_14, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 41 {P11_14, SPI_1, 2},
mbed_official 441:d2c15dda23c1 42 {P8_5 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 43 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 44 };
mbed_official 390:35c2c1cf29cd 45
mbed_official 390:35c2c1cf29cd 46 static const PinMap PinMap_SPI_MISO[] = {
mbed_official 390:35c2c1cf29cd 47 {P10_15, SPI_0, 4},
mbed_official 390:35c2c1cf29cd 48 {P11_15, SPI_1, 2},
mbed_official 441:d2c15dda23c1 49 {P8_6 , SPI_2, 3},
mbed_official 441:d2c15dda23c1 50 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 51 };
mbed_official 390:35c2c1cf29cd 52
mbed_official 441:d2c15dda23c1 53 static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 54
mbed_official 390:35c2c1cf29cd 55 static inline void spi_disable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 56 static inline void spi_enable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 57 static inline int spi_readable(spi_t *obj);
mbed_official 390:35c2c1cf29cd 58 static inline void spi_write(spi_t *obj, int value);
mbed_official 390:35c2c1cf29cd 59 static inline int spi_read(spi_t *obj);
mbed_official 390:35c2c1cf29cd 60
mbed_official 390:35c2c1cf29cd 61 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
mbed_official 390:35c2c1cf29cd 62 // determine the SPI to use
mbed_official 441:d2c15dda23c1 63 volatile uint8_t dummy;
mbed_official 441:d2c15dda23c1 64 uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
mbed_official 441:d2c15dda23c1 65 uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
mbed_official 441:d2c15dda23c1 66 uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 67 uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
mbed_official 441:d2c15dda23c1 68 uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
mbed_official 441:d2c15dda23c1 69 uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
mbed_official 441:d2c15dda23c1 70 uint32_t spi = pinmap_merge(spi_data, spi_cntl);
mbed_official 441:d2c15dda23c1 71
mbed_official 441:d2c15dda23c1 72 MBED_ASSERT((int)spi != NC);
mbed_official 441:d2c15dda23c1 73
mbed_official 441:d2c15dda23c1 74 obj->spi = (struct st_rspi *)RSPI[spi];
mbed_official 441:d2c15dda23c1 75
mbed_official 390:35c2c1cf29cd 76 // enable power and clocking
mbed_official 441:d2c15dda23c1 77 switch (spi) {
mbed_official 390:35c2c1cf29cd 78 case SPI_0: CPGSTBCR10 &= ~(0x80); break;
mbed_official 390:35c2c1cf29cd 79 case SPI_1: CPGSTBCR10 &= ~(0x40); break;
mbed_official 420:8e6e2662709e 80 case SPI_2: CPGSTBCR10 &= ~(0x20); break;
mbed_official 390:35c2c1cf29cd 81 }
mbed_official 390:35c2c1cf29cd 82 dummy = CPGSTBCR10;
mbed_official 390:35c2c1cf29cd 83
mbed_official 441:d2c15dda23c1 84 obj->spi->SPCR = 0x00; // CTRL to 0
mbed_official 441:d2c15dda23c1 85 obj->spi->SPSCR = 0x00; // no sequential operation
mbed_official 441:d2c15dda23c1 86 obj->spi->SSLP = 0x00; // SSL 'L' active
mbed_official 441:d2c15dda23c1 87 obj->spi->SPDCR = 0x20; // byte access
mbed_official 441:d2c15dda23c1 88 obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
mbed_official 441:d2c15dda23c1 89 obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
mbed_official 441:d2c15dda23c1 90 obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
mbed_official 441:d2c15dda23c1 91 obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
mbed_official 441:d2c15dda23c1 92 obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
mbed_official 441:d2c15dda23c1 93 obj->spi->SPBFCR = 0x30; // and reset buffer
mbed_official 390:35c2c1cf29cd 94
mbed_official 390:35c2c1cf29cd 95 // set default format and frequency
mbed_official 441:d2c15dda23c1 96 if ((int)ssel == NC) {
mbed_official 390:35c2c1cf29cd 97 spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
mbed_official 390:35c2c1cf29cd 98 } else {
mbed_official 390:35c2c1cf29cd 99 spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
mbed_official 390:35c2c1cf29cd 100 }
mbed_official 390:35c2c1cf29cd 101 spi_frequency(obj, 1000000);
mbed_official 390:35c2c1cf29cd 102
mbed_official 390:35c2c1cf29cd 103 // pin out the spi pins
mbed_official 390:35c2c1cf29cd 104 pinmap_pinout(mosi, PinMap_SPI_MOSI);
mbed_official 390:35c2c1cf29cd 105 pinmap_pinout(miso, PinMap_SPI_MISO);
mbed_official 390:35c2c1cf29cd 106 pinmap_pinout(sclk, PinMap_SPI_SCLK);
mbed_official 441:d2c15dda23c1 107 if ((int)ssel != NC) {
mbed_official 390:35c2c1cf29cd 108 pinmap_pinout(ssel, PinMap_SPI_SSEL);
mbed_official 390:35c2c1cf29cd 109 }
mbed_official 390:35c2c1cf29cd 110 }
mbed_official 390:35c2c1cf29cd 111
mbed_official 390:35c2c1cf29cd 112 void spi_free(spi_t *obj) {}
mbed_official 390:35c2c1cf29cd 113
mbed_official 390:35c2c1cf29cd 114 void spi_format(spi_t *obj, int bits, int mode, int slave) {
mbed_official 441:d2c15dda23c1 115 int DSS; // DSS (data select size)
mbed_official 441:d2c15dda23c1 116 int polarity = (mode & 0x2) ? 1 : 0;
mbed_official 441:d2c15dda23c1 117 int phase = (mode & 0x1) ? 1 : 0;
mbed_official 441:d2c15dda23c1 118 uint16_t tmp = 0;
mbed_official 441:d2c15dda23c1 119 uint16_t mask = 0xf03;
mbed_official 443:ed48b4122bfb 120 uint16_t wk_spcmd0;
mbed_official 441:d2c15dda23c1 121 uint8_t splw;
mbed_official 390:35c2c1cf29cd 122
mbed_official 441:d2c15dda23c1 123 switch (mode) {
mbed_official 441:d2c15dda23c1 124 case 0:
mbed_official 441:d2c15dda23c1 125 case 1:
mbed_official 441:d2c15dda23c1 126 case 2:
mbed_official 441:d2c15dda23c1 127 case 3:
mbed_official 441:d2c15dda23c1 128 // Do Nothing
mbed_official 441:d2c15dda23c1 129 break;
mbed_official 441:d2c15dda23c1 130 default:
mbed_official 441:d2c15dda23c1 131 error("SPI format error");
mbed_official 441:d2c15dda23c1 132 return;
mbed_official 441:d2c15dda23c1 133 }
mbed_official 390:35c2c1cf29cd 134
mbed_official 390:35c2c1cf29cd 135 switch (bits) {
mbed_official 390:35c2c1cf29cd 136 case 8:
mbed_official 441:d2c15dda23c1 137 DSS = 0x7;
mbed_official 441:d2c15dda23c1 138 splw = 0x20;
mbed_official 441:d2c15dda23c1 139 break;
mbed_official 390:35c2c1cf29cd 140 case 16:
mbed_official 441:d2c15dda23c1 141 DSS = 0xf;
mbed_official 441:d2c15dda23c1 142 splw = 0x40;
mbed_official 441:d2c15dda23c1 143 break;
mbed_official 390:35c2c1cf29cd 144 case 32:
mbed_official 441:d2c15dda23c1 145 DSS = 0x2;
mbed_official 441:d2c15dda23c1 146 splw = 0x60;
mbed_official 441:d2c15dda23c1 147 break;
mbed_official 390:35c2c1cf29cd 148 default:
mbed_official 390:35c2c1cf29cd 149 error("SPI module don't support other than 8/16/32bits");
mbed_official 441:d2c15dda23c1 150 return;
mbed_official 390:35c2c1cf29cd 151 }
mbed_official 441:d2c15dda23c1 152 tmp |= phase;
mbed_official 441:d2c15dda23c1 153 tmp |= (polarity << 1);
mbed_official 390:35c2c1cf29cd 154 tmp |= (DSS << 8);
mbed_official 441:d2c15dda23c1 155 obj->bits = bits;
mbed_official 390:35c2c1cf29cd 156
mbed_official 441:d2c15dda23c1 157 spi_disable(obj);
mbed_official 443:ed48b4122bfb 158 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 159 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 160 wk_spcmd0 |= (mask & tmp);
mbed_official 443:ed48b4122bfb 161 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 441:d2c15dda23c1 162 obj->spi->SPDCR = splw;
mbed_official 390:35c2c1cf29cd 163 if (slave) {
mbed_official 441:d2c15dda23c1 164 obj->spi->SPCR &=~(1 << 3); // MSTR to 0
mbed_official 390:35c2c1cf29cd 165 } else {
mbed_official 441:d2c15dda23c1 166 obj->spi->SPCR |= (1 << 3); // MSTR to 1
mbed_official 390:35c2c1cf29cd 167 }
mbed_official 390:35c2c1cf29cd 168 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 169 }
mbed_official 390:35c2c1cf29cd 170
mbed_official 390:35c2c1cf29cd 171 void spi_frequency(spi_t *obj, int hz) {
mbed_official 441:d2c15dda23c1 172 uint32_t pclk_base;
mbed_official 441:d2c15dda23c1 173 uint32_t div;
mbed_official 441:d2c15dda23c1 174 uint32_t brdv = 0;
mbed_official 441:d2c15dda23c1 175 uint32_t hz_max;
mbed_official 441:d2c15dda23c1 176 uint32_t hz_min;
mbed_official 441:d2c15dda23c1 177 uint16_t mask = 0x000c;
mbed_official 443:ed48b4122bfb 178 uint16_t wk_spcmd0;
mbed_official 390:35c2c1cf29cd 179
mbed_official 441:d2c15dda23c1 180 /* set PCLK */
mbed_official 441:d2c15dda23c1 181 if (RZ_A1_IsClockMode0() == false) {
mbed_official 441:d2c15dda23c1 182 pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
mbed_official 390:35c2c1cf29cd 183 } else {
mbed_official 441:d2c15dda23c1 184 pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
mbed_official 441:d2c15dda23c1 185 }
mbed_official 441:d2c15dda23c1 186
mbed_official 441:d2c15dda23c1 187 hz_min = pclk_base / 2 / 256 / 8;
mbed_official 441:d2c15dda23c1 188 hz_max = pclk_base / 2;
mbed_official 441:d2c15dda23c1 189 if ((hz < hz_min) || (hz > hz_max)) {
mbed_official 390:35c2c1cf29cd 190 error("Couldn't setup requested SPI frequency");
mbed_official 390:35c2c1cf29cd 191 return;
mbed_official 390:35c2c1cf29cd 192 }
mbed_official 390:35c2c1cf29cd 193
mbed_official 441:d2c15dda23c1 194 div = (pclk_base / hz / 2);
mbed_official 441:d2c15dda23c1 195 while (div > 256) {
mbed_official 441:d2c15dda23c1 196 div >>= 1;
mbed_official 441:d2c15dda23c1 197 brdv++;
mbed_official 441:d2c15dda23c1 198 }
mbed_official 441:d2c15dda23c1 199 div -= 1;
mbed_official 441:d2c15dda23c1 200 brdv = (brdv << 2);
mbed_official 390:35c2c1cf29cd 201
mbed_official 441:d2c15dda23c1 202 spi_disable(obj);
mbed_official 441:d2c15dda23c1 203 obj->spi->SPBR = div;
mbed_official 443:ed48b4122bfb 204 wk_spcmd0 = obj->spi->SPCMD0;
mbed_official 443:ed48b4122bfb 205 wk_spcmd0 &= ~mask;
mbed_official 443:ed48b4122bfb 206 wk_spcmd0 |= (mask & brdv);
mbed_official 443:ed48b4122bfb 207 obj->spi->SPCMD0 = wk_spcmd0;
mbed_official 390:35c2c1cf29cd 208 spi_enable(obj);
mbed_official 390:35c2c1cf29cd 209 }
mbed_official 390:35c2c1cf29cd 210
mbed_official 390:35c2c1cf29cd 211 static inline void spi_disable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 212 obj->spi->SPCR &= ~(1 << 6); // SPE to 0
mbed_official 390:35c2c1cf29cd 213 }
mbed_official 390:35c2c1cf29cd 214
mbed_official 390:35c2c1cf29cd 215 static inline void spi_enable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 216 obj->spi->SPCR |= (1 << 6); // SPE to 1
mbed_official 390:35c2c1cf29cd 217 }
mbed_official 390:35c2c1cf29cd 218
mbed_official 390:35c2c1cf29cd 219 static inline int spi_readable(spi_t *obj) {
mbed_official 441:d2c15dda23c1 220 return obj->spi->SPSR & (1 << 7); // SPRF
mbed_official 390:35c2c1cf29cd 221 }
mbed_official 390:35c2c1cf29cd 222
mbed_official 390:35c2c1cf29cd 223 static inline int spi_tend(spi_t *obj) {
mbed_official 441:d2c15dda23c1 224 return obj->spi->SPSR & (1 << 6); // TEND
mbed_official 390:35c2c1cf29cd 225 }
mbed_official 390:35c2c1cf29cd 226
mbed_official 390:35c2c1cf29cd 227 static inline void spi_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 228 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 229 obj->spi->SPDR.UINT8[0] = (uint8_t)value;
mbed_official 441:d2c15dda23c1 230 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 231 obj->spi->SPDR.UINT16[0] = (uint16_t)value;
mbed_official 441:d2c15dda23c1 232 } else {
mbed_official 441:d2c15dda23c1 233 obj->spi->SPDR.UINT32 = (uint32_t)value;
mbed_official 441:d2c15dda23c1 234 }
mbed_official 390:35c2c1cf29cd 235 }
mbed_official 390:35c2c1cf29cd 236
mbed_official 390:35c2c1cf29cd 237 static inline int spi_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 238 int read_data;
mbed_official 441:d2c15dda23c1 239
mbed_official 441:d2c15dda23c1 240 if (obj->bits == 8) {
mbed_official 441:d2c15dda23c1 241 read_data = obj->spi->SPDR.UINT8[0];
mbed_official 441:d2c15dda23c1 242 } else if (obj->bits == 16) {
mbed_official 441:d2c15dda23c1 243 read_data = obj->spi->SPDR.UINT16[0];
mbed_official 441:d2c15dda23c1 244 } else {
mbed_official 441:d2c15dda23c1 245 read_data = obj->spi->SPDR.UINT32;
mbed_official 441:d2c15dda23c1 246 }
mbed_official 441:d2c15dda23c1 247
mbed_official 441:d2c15dda23c1 248 return read_data;
mbed_official 390:35c2c1cf29cd 249 }
mbed_official 390:35c2c1cf29cd 250
mbed_official 390:35c2c1cf29cd 251 int spi_master_write(spi_t *obj, int value) {
mbed_official 390:35c2c1cf29cd 252 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 253 while(!spi_tend(obj));
mbed_official 390:35c2c1cf29cd 254 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 255 }
mbed_official 390:35c2c1cf29cd 256
mbed_official 390:35c2c1cf29cd 257 int spi_slave_receive(spi_t *obj) {
mbed_official 390:35c2c1cf29cd 258 return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
mbed_official 390:35c2c1cf29cd 259 }
mbed_official 390:35c2c1cf29cd 260
mbed_official 390:35c2c1cf29cd 261 int spi_slave_read(spi_t *obj) {
mbed_official 441:d2c15dda23c1 262 return spi_read(obj);
mbed_official 390:35c2c1cf29cd 263 }
mbed_official 390:35c2c1cf29cd 264
mbed_official 390:35c2c1cf29cd 265 void spi_slave_write(spi_t *obj, int value) {
mbed_official 441:d2c15dda23c1 266 spi_write(obj, value);
mbed_official 390:35c2c1cf29cd 267 }
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 int spi_busy(spi_t *obj) {
mbed_official 441:d2c15dda23c1 270 return 0;
mbed_official 390:35c2c1cf29cd 271 }