Benoît Locher / mbedNet

Rewrite from scratch a TCP/IP stack for mbed. So far the following parts are usable: Drivers: - EMAC driver (from CMSIS 2.0) Protocols: - Ethernet protocol - ARP over ethernet for IPv4 - IPv4 over Ethernet - ICMPv4 over IPv4 - UDPv4 over IPv4 APIs: - Sockets for UDPv4 The structure of this stack is designed to be very modular. Each protocol can register one or more protocol to handle its payload, and in each protocol, an API can be hooked (like Sockets for example). This is an early release.

lpc17xx_clkpwr.c@0:19f5f51584de, 2011-06-12 (annotated)

Committer:
Benoit
Date:
Sun Jun 12 11:23:03 2011 +0000
Revision:
0:19f5f51584de
Initial release (alpha quality)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Benoit 0:19f5f51584de 1 /***********************************************************************//**
Benoit 0:19f5f51584de 2 * @file lpc17xx_clkpwr.c
Benoit 0:19f5f51584de 3 * @brief Contains all functions support for Clock and Power Control
Benoit 0:19f5f51584de 4 * firmware library on LPC17xx
Benoit 0:19f5f51584de 5 * @version 3.0
Benoit 0:19f5f51584de 6 * @date 18. June. 2010
Benoit 0:19f5f51584de 7 * @author NXP MCU SW Application Team
Benoit 0:19f5f51584de 8 **************************************************************************
Benoit 0:19f5f51584de 9 * Software that is described herein is for illustrative purposes only
Benoit 0:19f5f51584de 10 * which provides customers with programming information regarding the
Benoit 0:19f5f51584de 11 * products. This software is supplied "AS IS" without any warranties.
Benoit 0:19f5f51584de 12 * NXP Semiconductors assumes no responsibility or liability for the
Benoit 0:19f5f51584de 13 * use of the software, conveys no license or title under any patent,
Benoit 0:19f5f51584de 14 * copyright, or mask work right to the product. NXP Semiconductors
Benoit 0:19f5f51584de 15 * reserves the right to make changes in the software without
Benoit 0:19f5f51584de 16 * notification. NXP Semiconductors also make no representation or
Benoit 0:19f5f51584de 17 * warranty that such application will be suitable for the specified
Benoit 0:19f5f51584de 18 * use without further testing or modification.
Benoit 0:19f5f51584de 19 **********************************************************************/
Benoit 0:19f5f51584de 20
Benoit 0:19f5f51584de 21 /* Peripheral group ----------------------------------------------------------- */
Benoit 0:19f5f51584de 22 /** @addtogroup CLKPWR
Benoit 0:19f5f51584de 23 * @{
Benoit 0:19f5f51584de 24 */
Benoit 0:19f5f51584de 25
Benoit 0:19f5f51584de 26 /* Includes ------------------------------------------------------------------- */
Benoit 0:19f5f51584de 27 #include "lpc17xx_clkpwr.h"
Benoit 0:19f5f51584de 28
Benoit 0:19f5f51584de 29
Benoit 0:19f5f51584de 30 /* Public Functions ----------------------------------------------------------- */
Benoit 0:19f5f51584de 31 /** @addtogroup CLKPWR_Public_Functions
Benoit 0:19f5f51584de 32 * @{
Benoit 0:19f5f51584de 33 */
Benoit 0:19f5f51584de 34
Benoit 0:19f5f51584de 35 /*********************************************************************//**
Benoit 0:19f5f51584de 36 * @brief Set value of each Peripheral Clock Selection
Benoit 0:19f5f51584de 37 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 0:19f5f51584de 38 * should be one of the following:
Benoit 0:19f5f51584de 39 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 0:19f5f51584de 40 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 0:19f5f51584de 41 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 0:19f5f51584de 42 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 0:19f5f51584de 43 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 0:19f5f51584de 44 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 0:19f5f51584de 45 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 0:19f5f51584de 46 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 0:19f5f51584de 47 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 0:19f5f51584de 48 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 0:19f5f51584de 49 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 0:19f5f51584de 50 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 0:19f5f51584de 51 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 0:19f5f51584de 52 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 0:19f5f51584de 53 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 0:19f5f51584de 54 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 0:19f5f51584de 55 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 0:19f5f51584de 56 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 0:19f5f51584de 57 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 0:19f5f51584de 58 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 0:19f5f51584de 59 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 0:19f5f51584de 60 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 0:19f5f51584de 61 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 0:19f5f51584de 62 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 0:19f5f51584de 63 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 0:19f5f51584de 64 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 0:19f5f51584de 65 - CLKPWR_PCLKSEL_MC : MC
Benoit 0:19f5f51584de 66
Benoit 0:19f5f51584de 67 * @param[in] DivVal Value of divider, should be:
Benoit 0:19f5f51584de 68 * - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
Benoit 0:19f5f51584de 69 * - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
Benoit 0:19f5f51584de 70 * - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
Benoit 0:19f5f51584de 71 *
Benoit 0:19f5f51584de 72 * @return none
Benoit 0:19f5f51584de 73 **********************************************************************/
Benoit 0:19f5f51584de 74 void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
Benoit 0:19f5f51584de 75 {
Benoit 0:19f5f51584de 76 uint32_t bitpos;
Benoit 0:19f5f51584de 77
Benoit 0:19f5f51584de 78 bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
Benoit 0:19f5f51584de 79
Benoit 0:19f5f51584de 80 /* PCLKSEL0 selected */
Benoit 0:19f5f51584de 81 if (ClkType < 32)
Benoit 0:19f5f51584de 82 {
Benoit 0:19f5f51584de 83 /* Clear two bit at bit position */
Benoit 0:19f5f51584de 84 LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
Benoit 0:19f5f51584de 85
Benoit 0:19f5f51584de 86 /* Set two selected bit */
Benoit 0:19f5f51584de 87 LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
Benoit 0:19f5f51584de 88 }
Benoit 0:19f5f51584de 89 /* PCLKSEL1 selected */
Benoit 0:19f5f51584de 90 else
Benoit 0:19f5f51584de 91 {
Benoit 0:19f5f51584de 92 /* Clear two bit at bit position */
Benoit 0:19f5f51584de 93 LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
Benoit 0:19f5f51584de 94
Benoit 0:19f5f51584de 95 /* Set two selected bit */
Benoit 0:19f5f51584de 96 LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
Benoit 0:19f5f51584de 97 }
Benoit 0:19f5f51584de 98 }
Benoit 0:19f5f51584de 99
Benoit 0:19f5f51584de 100
Benoit 0:19f5f51584de 101 /*********************************************************************//**
Benoit 0:19f5f51584de 102 * @brief Get current value of each Peripheral Clock Selection
Benoit 0:19f5f51584de 103 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 0:19f5f51584de 104 * should be one of the following:
Benoit 0:19f5f51584de 105 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 0:19f5f51584de 106 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 0:19f5f51584de 107 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 0:19f5f51584de 108 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 0:19f5f51584de 109 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 0:19f5f51584de 110 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 0:19f5f51584de 111 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 0:19f5f51584de 112 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 0:19f5f51584de 113 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 0:19f5f51584de 114 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 0:19f5f51584de 115 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 0:19f5f51584de 116 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 0:19f5f51584de 117 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 0:19f5f51584de 118 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 0:19f5f51584de 119 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 0:19f5f51584de 120 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 0:19f5f51584de 121 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 0:19f5f51584de 122 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 0:19f5f51584de 123 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 0:19f5f51584de 124 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 0:19f5f51584de 125 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 0:19f5f51584de 126 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 0:19f5f51584de 127 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 0:19f5f51584de 128 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 0:19f5f51584de 129 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 0:19f5f51584de 130 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 0:19f5f51584de 131 - CLKPWR_PCLKSEL_MC : MC
Benoit 0:19f5f51584de 132
Benoit 0:19f5f51584de 133 * @return Value of Selected Peripheral Clock Selection
Benoit 0:19f5f51584de 134 **********************************************************************/
Benoit 0:19f5f51584de 135 uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
Benoit 0:19f5f51584de 136 {
Benoit 0:19f5f51584de 137 uint32_t bitpos, retval;
Benoit 0:19f5f51584de 138
Benoit 0:19f5f51584de 139 if (ClkType < 32)
Benoit 0:19f5f51584de 140 {
Benoit 0:19f5f51584de 141 bitpos = ClkType;
Benoit 0:19f5f51584de 142 retval = LPC_SC->PCLKSEL0;
Benoit 0:19f5f51584de 143 }
Benoit 0:19f5f51584de 144 else
Benoit 0:19f5f51584de 145 {
Benoit 0:19f5f51584de 146 bitpos = ClkType - 32;
Benoit 0:19f5f51584de 147 retval = LPC_SC->PCLKSEL1;
Benoit 0:19f5f51584de 148 }
Benoit 0:19f5f51584de 149
Benoit 0:19f5f51584de 150 retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
Benoit 0:19f5f51584de 151 return retval;
Benoit 0:19f5f51584de 152 }
Benoit 0:19f5f51584de 153
Benoit 0:19f5f51584de 154
Benoit 0:19f5f51584de 155
Benoit 0:19f5f51584de 156 /*********************************************************************//**
Benoit 0:19f5f51584de 157 * @brief Get current value of each Peripheral Clock
Benoit 0:19f5f51584de 158 * @param[in] ClkType Peripheral Clock Selection of each type,
Benoit 0:19f5f51584de 159 * should be one of the following:
Benoit 0:19f5f51584de 160 * - CLKPWR_PCLKSEL_WDT : WDT
Benoit 0:19f5f51584de 161 - CLKPWR_PCLKSEL_TIMER0 : Timer 0
Benoit 0:19f5f51584de 162 - CLKPWR_PCLKSEL_TIMER1 : Timer 1
Benoit 0:19f5f51584de 163 - CLKPWR_PCLKSEL_UART0 : UART 0
Benoit 0:19f5f51584de 164 - CLKPWR_PCLKSEL_UART1 : UART 1
Benoit 0:19f5f51584de 165 - CLKPWR_PCLKSEL_PWM1 : PWM 1
Benoit 0:19f5f51584de 166 - CLKPWR_PCLKSEL_I2C0 : I2C 0
Benoit 0:19f5f51584de 167 - CLKPWR_PCLKSEL_SPI : SPI
Benoit 0:19f5f51584de 168 - CLKPWR_PCLKSEL_SSP1 : SSP 1
Benoit 0:19f5f51584de 169 - CLKPWR_PCLKSEL_DAC : DAC
Benoit 0:19f5f51584de 170 - CLKPWR_PCLKSEL_ADC : ADC
Benoit 0:19f5f51584de 171 - CLKPWR_PCLKSEL_CAN1 : CAN 1
Benoit 0:19f5f51584de 172 - CLKPWR_PCLKSEL_CAN2 : CAN 2
Benoit 0:19f5f51584de 173 - CLKPWR_PCLKSEL_ACF : ACF
Benoit 0:19f5f51584de 174 - CLKPWR_PCLKSEL_QEI : QEI
Benoit 0:19f5f51584de 175 - CLKPWR_PCLKSEL_PCB : PCB
Benoit 0:19f5f51584de 176 - CLKPWR_PCLKSEL_I2C1 : I2C 1
Benoit 0:19f5f51584de 177 - CLKPWR_PCLKSEL_SSP0 : SSP 0
Benoit 0:19f5f51584de 178 - CLKPWR_PCLKSEL_TIMER2 : Timer 2
Benoit 0:19f5f51584de 179 - CLKPWR_PCLKSEL_TIMER3 : Timer 3
Benoit 0:19f5f51584de 180 - CLKPWR_PCLKSEL_UART2 : UART 2
Benoit 0:19f5f51584de 181 - CLKPWR_PCLKSEL_UART3 : UART 3
Benoit 0:19f5f51584de 182 - CLKPWR_PCLKSEL_I2C2 : I2C 2
Benoit 0:19f5f51584de 183 - CLKPWR_PCLKSEL_I2S : I2S
Benoit 0:19f5f51584de 184 - CLKPWR_PCLKSEL_RIT : RIT
Benoit 0:19f5f51584de 185 - CLKPWR_PCLKSEL_SYSCON : SYSCON
Benoit 0:19f5f51584de 186 - CLKPWR_PCLKSEL_MC : MC
Benoit 0:19f5f51584de 187
Benoit 0:19f5f51584de 188 * @return Value of Selected Peripheral Clock
Benoit 0:19f5f51584de 189 **********************************************************************/
Benoit 0:19f5f51584de 190 uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
Benoit 0:19f5f51584de 191 {
Benoit 0:19f5f51584de 192 uint32_t retval, div;
Benoit 0:19f5f51584de 193
Benoit 0:19f5f51584de 194 retval = SystemCoreClock;
Benoit 0:19f5f51584de 195 div = CLKPWR_GetPCLKSEL(ClkType);
Benoit 0:19f5f51584de 196
Benoit 0:19f5f51584de 197 switch (div)
Benoit 0:19f5f51584de 198 {
Benoit 0:19f5f51584de 199 case 0:
Benoit 0:19f5f51584de 200 div = 4;
Benoit 0:19f5f51584de 201 break;
Benoit 0:19f5f51584de 202
Benoit 0:19f5f51584de 203 case 1:
Benoit 0:19f5f51584de 204 div = 1;
Benoit 0:19f5f51584de 205 break;
Benoit 0:19f5f51584de 206
Benoit 0:19f5f51584de 207 case 2:
Benoit 0:19f5f51584de 208 div = 2;
Benoit 0:19f5f51584de 209 break;
Benoit 0:19f5f51584de 210
Benoit 0:19f5f51584de 211 case 3:
Benoit 0:19f5f51584de 212 div = 8;
Benoit 0:19f5f51584de 213 break;
Benoit 0:19f5f51584de 214 }
Benoit 0:19f5f51584de 215 retval /= div;
Benoit 0:19f5f51584de 216
Benoit 0:19f5f51584de 217 return retval;
Benoit 0:19f5f51584de 218 }
Benoit 0:19f5f51584de 219
Benoit 0:19f5f51584de 220
Benoit 0:19f5f51584de 221
Benoit 0:19f5f51584de 222 /*********************************************************************//**
Benoit 0:19f5f51584de 223 * @brief Configure power supply for each peripheral according to NewState
Benoit 0:19f5f51584de 224 * @param[in] PPType Type of peripheral used to enable power,
Benoit 0:19f5f51584de 225 * should be one of the following:
Benoit 0:19f5f51584de 226 * - CLKPWR_PCONP_PCTIM0 : Timer 0
Benoit 0:19f5f51584de 227 - CLKPWR_PCONP_PCTIM1 : Timer 1
Benoit 0:19f5f51584de 228 - CLKPWR_PCONP_PCUART0 : UART 0
Benoit 0:19f5f51584de 229 - CLKPWR_PCONP_PCUART1 : UART 1
Benoit 0:19f5f51584de 230 - CLKPWR_PCONP_PCPWM1 : PWM 1
Benoit 0:19f5f51584de 231 - CLKPWR_PCONP_PCI2C0 : I2C 0
Benoit 0:19f5f51584de 232 - CLKPWR_PCONP_PCSPI : SPI
Benoit 0:19f5f51584de 233 - CLKPWR_PCONP_PCRTC : RTC
Benoit 0:19f5f51584de 234 - CLKPWR_PCONP_PCSSP1 : SSP 1
Benoit 0:19f5f51584de 235 - CLKPWR_PCONP_PCAD : ADC
Benoit 0:19f5f51584de 236 - CLKPWR_PCONP_PCAN1 : CAN 1
Benoit 0:19f5f51584de 237 - CLKPWR_PCONP_PCAN2 : CAN 2
Benoit 0:19f5f51584de 238 - CLKPWR_PCONP_PCGPIO : GPIO
Benoit 0:19f5f51584de 239 - CLKPWR_PCONP_PCRIT : RIT
Benoit 0:19f5f51584de 240 - CLKPWR_PCONP_PCMC : MC
Benoit 0:19f5f51584de 241 - CLKPWR_PCONP_PCQEI : QEI
Benoit 0:19f5f51584de 242 - CLKPWR_PCONP_PCI2C1 : I2C 1
Benoit 0:19f5f51584de 243 - CLKPWR_PCONP_PCSSP0 : SSP 0
Benoit 0:19f5f51584de 244 - CLKPWR_PCONP_PCTIM2 : Timer 2
Benoit 0:19f5f51584de 245 - CLKPWR_PCONP_PCTIM3 : Timer 3
Benoit 0:19f5f51584de 246 - CLKPWR_PCONP_PCUART2 : UART 2
Benoit 0:19f5f51584de 247 - CLKPWR_PCONP_PCUART3 : UART 3
Benoit 0:19f5f51584de 248 - CLKPWR_PCONP_PCI2C2 : I2C 2
Benoit 0:19f5f51584de 249 - CLKPWR_PCONP_PCI2S : I2S
Benoit 0:19f5f51584de 250 - CLKPWR_PCONP_PCGPDMA : GPDMA
Benoit 0:19f5f51584de 251 - CLKPWR_PCONP_PCENET : Ethernet
Benoit 0:19f5f51584de 252 - CLKPWR_PCONP_PCUSB : USB
Benoit 0:19f5f51584de 253 *
Benoit 0:19f5f51584de 254 * @param[in] NewState New state of Peripheral Power, should be:
Benoit 0:19f5f51584de 255 * - ENABLE : Enable power for this peripheral
Benoit 0:19f5f51584de 256 * - DISABLE : Disable power for this peripheral
Benoit 0:19f5f51584de 257 *
Benoit 0:19f5f51584de 258 * @return none
Benoit 0:19f5f51584de 259 **********************************************************************/
Benoit 0:19f5f51584de 260 void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
Benoit 0:19f5f51584de 261 {
Benoit 0:19f5f51584de 262 if (NewState == ENABLE)
Benoit 0:19f5f51584de 263 {
Benoit 0:19f5f51584de 264 LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
Benoit 0:19f5f51584de 265 }
Benoit 0:19f5f51584de 266 else if (NewState == DISABLE)
Benoit 0:19f5f51584de 267 {
Benoit 0:19f5f51584de 268 LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
Benoit 0:19f5f51584de 269 }
Benoit 0:19f5f51584de 270 }
Benoit 0:19f5f51584de 271
Benoit 0:19f5f51584de 272
Benoit 0:19f5f51584de 273 /*********************************************************************//**
Benoit 0:19f5f51584de 274 * @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
Benoit 0:19f5f51584de 275 * @param[in] None
Benoit 0:19f5f51584de 276 * @return None
Benoit 0:19f5f51584de 277 **********************************************************************/
Benoit 0:19f5f51584de 278 void CLKPWR_Sleep(void)
Benoit 0:19f5f51584de 279 {
Benoit 0:19f5f51584de 280 LPC_SC->PCON = 0x00;
Benoit 0:19f5f51584de 281 /* Sleep Mode*/
Benoit 0:19f5f51584de 282 __WFI();
Benoit 0:19f5f51584de 283 }
Benoit 0:19f5f51584de 284
Benoit 0:19f5f51584de 285
Benoit 0:19f5f51584de 286 /*********************************************************************//**
Benoit 0:19f5f51584de 287 * @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
Benoit 0:19f5f51584de 288 * @param[in] None
Benoit 0:19f5f51584de 289 * @return None
Benoit 0:19f5f51584de 290 **********************************************************************/
Benoit 0:19f5f51584de 291 void CLKPWR_DeepSleep(void)
Benoit 0:19f5f51584de 292 {
Benoit 0:19f5f51584de 293 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 0:19f5f51584de 294 SCB->SCR = 0x4;
Benoit 0:19f5f51584de 295 LPC_SC->PCON = 0x8;
Benoit 0:19f5f51584de 296 /* Deep Sleep Mode*/
Benoit 0:19f5f51584de 297 __WFI();
Benoit 0:19f5f51584de 298 }
Benoit 0:19f5f51584de 299
Benoit 0:19f5f51584de 300
Benoit 0:19f5f51584de 301 /*********************************************************************//**
Benoit 0:19f5f51584de 302 * @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
Benoit 0:19f5f51584de 303 * @param[in] None
Benoit 0:19f5f51584de 304 * @return None
Benoit 0:19f5f51584de 305 **********************************************************************/
Benoit 0:19f5f51584de 306 void CLKPWR_PowerDown(void)
Benoit 0:19f5f51584de 307 {
Benoit 0:19f5f51584de 308 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 0:19f5f51584de 309 SCB->SCR = 0x4;
Benoit 0:19f5f51584de 310 LPC_SC->PCON = 0x09;
Benoit 0:19f5f51584de 311 /* Power Down Mode*/
Benoit 0:19f5f51584de 312 __WFI();
Benoit 0:19f5f51584de 313 }
Benoit 0:19f5f51584de 314
Benoit 0:19f5f51584de 315
Benoit 0:19f5f51584de 316 /*********************************************************************//**
Benoit 0:19f5f51584de 317 * @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
Benoit 0:19f5f51584de 318 * @param[in] None
Benoit 0:19f5f51584de 319 * @return None
Benoit 0:19f5f51584de 320 **********************************************************************/
Benoit 0:19f5f51584de 321 void CLKPWR_DeepPowerDown(void)
Benoit 0:19f5f51584de 322 {
Benoit 0:19f5f51584de 323 /* Deep-Sleep Mode, set SLEEPDEEP bit */
Benoit 0:19f5f51584de 324 SCB->SCR = 0x4;
Benoit 0:19f5f51584de 325 LPC_SC->PCON = 0x03;
Benoit 0:19f5f51584de 326 /* Deep Power Down Mode*/
Benoit 0:19f5f51584de 327 __WFI();
Benoit 0:19f5f51584de 328 }
Benoit 0:19f5f51584de 329
Benoit 0:19f5f51584de 330 /**
Benoit 0:19f5f51584de 331 * @}
Benoit 0:19f5f51584de 332 */
Benoit 0:19f5f51584de 333
Benoit 0:19f5f51584de 334 /**
Benoit 0:19f5f51584de 335 * @}
Benoit 0:19f5f51584de 336 */
Benoit 0:19f5f51584de 337
Benoit 0:19f5f51584de 338 /* --------------------------------- End Of File ------------------------------ */