Martin Olejar / Mbed 2 deprecated FRDM_MFRC522

MFRC522 example project for FRDM

Dependencies:   MFRC522 mbed

MFRC522.cpp@0:1d9c7c0b5015, 2013-12-14 (annotated)

Committer:
AtomX
Date:
Sat Dec 14 21:41:08 2013 +0000
Revision:
0:1d9c7c0b5015
Created MFRC522 project

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AtomX 0:1d9c7c0b5015 1 /*
AtomX 0:1d9c7c0b5015 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
AtomX 0:1d9c7c0b5015 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
AtomX 0:1d9c7c0b5015 4 * Released into the public domain.
AtomX 0:1d9c7c0b5015 5 */
AtomX 0:1d9c7c0b5015 6
AtomX 0:1d9c7c0b5015 7 #include "MFRC522.h"
AtomX 0:1d9c7c0b5015 8
AtomX 0:1d9c7c0b5015 9
AtomX 0:1d9c7c0b5015 10 #define MFRC522_MaxPICCs 9
AtomX 0:1d9c7c0b5015 11 #define MFRC522_MaxError 10
AtomX 0:1d9c7c0b5015 12
AtomX 0:1d9c7c0b5015 13 static std::string _TypeNamePICC[MFRC522_MaxPICCs] =
AtomX 0:1d9c7c0b5015 14 {
AtomX 0:1d9c7c0b5015 15 "Unknown type",
AtomX 0:1d9c7c0b5015 16 "PICC compliant with ISO/IEC 14443-4",
AtomX 0:1d9c7c0b5015 17 "PICC compliant with ISO/IEC 18092 (NFC)",
AtomX 0:1d9c7c0b5015 18 "MIFARE Mini, 320 bytes",
AtomX 0:1d9c7c0b5015 19 "MIFARE 1KB",
AtomX 0:1d9c7c0b5015 20 "MIFARE 4KB",
AtomX 0:1d9c7c0b5015 21 "MIFARE Ultralight or Ultralight C",
AtomX 0:1d9c7c0b5015 22 "MIFARE Plus",
AtomX 0:1d9c7c0b5015 23 "MIFARE TNP3XXX"
AtomX 0:1d9c7c0b5015 24 };
AtomX 0:1d9c7c0b5015 25
AtomX 0:1d9c7c0b5015 26 static std::string _ErrorMessage[MFRC522_MaxError] =
AtomX 0:1d9c7c0b5015 27 {
AtomX 0:1d9c7c0b5015 28 "Unknown error",
AtomX 0:1d9c7c0b5015 29 "Success",
AtomX 0:1d9c7c0b5015 30 "Error in communication",
AtomX 0:1d9c7c0b5015 31 "Collision detected",
AtomX 0:1d9c7c0b5015 32 "Timeout in communication",
AtomX 0:1d9c7c0b5015 33 "A buffer is not big enough",
AtomX 0:1d9c7c0b5015 34 "Internal error in the code, should not happen",
AtomX 0:1d9c7c0b5015 35 "Invalid argument",
AtomX 0:1d9c7c0b5015 36 "The CRC_A does not match",
AtomX 0:1d9c7c0b5015 37 "A MIFARE PICC responded with NAK"
AtomX 0:1d9c7c0b5015 38 };
AtomX 0:1d9c7c0b5015 39
AtomX 0:1d9c7c0b5015 40 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 41 // Functions for setting up the driver
AtomX 0:1d9c7c0b5015 42 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 43
AtomX 0:1d9c7c0b5015 44 /**
AtomX 0:1d9c7c0b5015 45 * Constructor.
AtomX 0:1d9c7c0b5015 46 * Prepares the output pins.
AtomX 0:1d9c7c0b5015 47 */
AtomX 0:1d9c7c0b5015 48 MFRC522::MFRC522(PinName mosi,
AtomX 0:1d9c7c0b5015 49 PinName miso,
AtomX 0:1d9c7c0b5015 50 PinName sclk,
AtomX 0:1d9c7c0b5015 51 PinName cs,
AtomX 0:1d9c7c0b5015 52 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
AtomX 0:1d9c7c0b5015 53 {
AtomX 0:1d9c7c0b5015 54 /* init MFRC522 SPI BUS */
AtomX 0:1d9c7c0b5015 55 m_SPI.format(8, 0);
AtomX 0:1d9c7c0b5015 56 m_SPI.frequency(8000000);
AtomX 0:1d9c7c0b5015 57
AtomX 0:1d9c7c0b5015 58 /* init MFRC522 SPI_CS pin */
AtomX 0:1d9c7c0b5015 59 m_CS = 1;
AtomX 0:1d9c7c0b5015 60
AtomX 0:1d9c7c0b5015 61 /* init MFRC522 RESET pin */
AtomX 0:1d9c7c0b5015 62 m_RESET = 1;
AtomX 0:1d9c7c0b5015 63 } // End constructor
AtomX 0:1d9c7c0b5015 64
AtomX 0:1d9c7c0b5015 65
AtomX 0:1d9c7c0b5015 66 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 67 // Basic interface functions for communicating with the MFRC522
AtomX 0:1d9c7c0b5015 68 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 69
AtomX 0:1d9c7c0b5015 70 /**
AtomX 0:1d9c7c0b5015 71 * Writes a byte to the specified register in the MFRC522 chip.
AtomX 0:1d9c7c0b5015 72 * The interface is described in the datasheet section 8.1.2.
AtomX 0:1d9c7c0b5015 73 */
AtomX 0:1d9c7c0b5015 74 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
AtomX 0:1d9c7c0b5015 75 {
AtomX 0:1d9c7c0b5015 76 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 77
AtomX 0:1d9c7c0b5015 78 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:1d9c7c0b5015 79 (void) m_SPI.write(reg & 0x7E);
AtomX 0:1d9c7c0b5015 80 (void) m_SPI.write(value);
AtomX 0:1d9c7c0b5015 81
AtomX 0:1d9c7c0b5015 82 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 83 } // End PCD_WriteRegister()
AtomX 0:1d9c7c0b5015 84
AtomX 0:1d9c7c0b5015 85 /**
AtomX 0:1d9c7c0b5015 86 * Writes a number of bytes to the specified register in the MFRC522 chip.
AtomX 0:1d9c7c0b5015 87 * The interface is described in the datasheet section 8.1.2.
AtomX 0:1d9c7c0b5015 88 */
AtomX 0:1d9c7c0b5015 89 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
AtomX 0:1d9c7c0b5015 90 {
AtomX 0:1d9c7c0b5015 91 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 92
AtomX 0:1d9c7c0b5015 93 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:1d9c7c0b5015 94 (void) m_SPI.write(reg & 0x7E);
AtomX 0:1d9c7c0b5015 95 for (uint8_t index = 0; index < count; index++)
AtomX 0:1d9c7c0b5015 96 {
AtomX 0:1d9c7c0b5015 97 (void) m_SPI.write(values[index]);
AtomX 0:1d9c7c0b5015 98 }
AtomX 0:1d9c7c0b5015 99
AtomX 0:1d9c7c0b5015 100 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 101 } // End PCD_WriteRegister()
AtomX 0:1d9c7c0b5015 102
AtomX 0:1d9c7c0b5015 103 /**
AtomX 0:1d9c7c0b5015 104 * Reads a byte from the specified register in the MFRC522 chip.
AtomX 0:1d9c7c0b5015 105 * The interface is described in the datasheet section 8.1.2.
AtomX 0:1d9c7c0b5015 106 */
AtomX 0:1d9c7c0b5015 107 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
AtomX 0:1d9c7c0b5015 108 {
AtomX 0:1d9c7c0b5015 109 uint8_t value;
AtomX 0:1d9c7c0b5015 110 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 111
AtomX 0:1d9c7c0b5015 112 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:1d9c7c0b5015 113 (void) m_SPI.write(0x80 | reg);
AtomX 0:1d9c7c0b5015 114 value = m_SPI.write(0); // Read the value back. Send 0 to stop reading.
AtomX 0:1d9c7c0b5015 115
AtomX 0:1d9c7c0b5015 116 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 117 return value;
AtomX 0:1d9c7c0b5015 118 } // End PCD_ReadRegister()
AtomX 0:1d9c7c0b5015 119
AtomX 0:1d9c7c0b5015 120 /**
AtomX 0:1d9c7c0b5015 121 * Reads a number of bytes from the specified register in the MFRC522 chip.
AtomX 0:1d9c7c0b5015 122 * The interface is described in the datasheet section 8.1.2.
AtomX 0:1d9c7c0b5015 123 */
AtomX 0:1d9c7c0b5015 124 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
AtomX 0:1d9c7c0b5015 125 {
AtomX 0:1d9c7c0b5015 126 if (count == 0) { return; }
AtomX 0:1d9c7c0b5015 127
AtomX 0:1d9c7c0b5015 128 //Serial.print("Reading "); Serial.print(count); Serial.println(" bytes from register.");
AtomX 0:1d9c7c0b5015 129 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
AtomX 0:1d9c7c0b5015 130 uint8_t index = 0; // Index in values array.
AtomX 0:1d9c7c0b5015 131
AtomX 0:1d9c7c0b5015 132 m_CS = 0; /* Select SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 133 count--; // One read is performed outside of the loop
AtomX 0:1d9c7c0b5015 134 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
AtomX 0:1d9c7c0b5015 135
AtomX 0:1d9c7c0b5015 136 while (index < count)
AtomX 0:1d9c7c0b5015 137 {
AtomX 0:1d9c7c0b5015 138 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
AtomX 0:1d9c7c0b5015 139 {
AtomX 0:1d9c7c0b5015 140 // Create bit mask for bit positions rxAlign..7
AtomX 0:1d9c7c0b5015 141 uint8_t mask = 0;
AtomX 0:1d9c7c0b5015 142 for (uint8_t i = rxAlign; i <= 7; i++)
AtomX 0:1d9c7c0b5015 143 {
AtomX 0:1d9c7c0b5015 144 mask |= (1 << i);
AtomX 0:1d9c7c0b5015 145 }
AtomX 0:1d9c7c0b5015 146
AtomX 0:1d9c7c0b5015 147 // Read value and tell that we want to read the same address again.
AtomX 0:1d9c7c0b5015 148 uint8_t value = m_SPI.write(address);
AtomX 0:1d9c7c0b5015 149
AtomX 0:1d9c7c0b5015 150 // Apply mask to both current value of values[0] and the new data in value.
AtomX 0:1d9c7c0b5015 151 values[0] = (values[index] & ~mask) | (value & mask);
AtomX 0:1d9c7c0b5015 152 }
AtomX 0:1d9c7c0b5015 153 else
AtomX 0:1d9c7c0b5015 154 {
AtomX 0:1d9c7c0b5015 155 // Read value and tell that we want to read the same address again.
AtomX 0:1d9c7c0b5015 156 values[index] = m_SPI.write(address);
AtomX 0:1d9c7c0b5015 157 }
AtomX 0:1d9c7c0b5015 158
AtomX 0:1d9c7c0b5015 159 index++;
AtomX 0:1d9c7c0b5015 160 }
AtomX 0:1d9c7c0b5015 161
AtomX 0:1d9c7c0b5015 162 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
AtomX 0:1d9c7c0b5015 163
AtomX 0:1d9c7c0b5015 164 m_CS = 1; /* Release SPI Chip MFRC522 */
AtomX 0:1d9c7c0b5015 165 } // End PCD_ReadRegister()
AtomX 0:1d9c7c0b5015 166
AtomX 0:1d9c7c0b5015 167 /**
AtomX 0:1d9c7c0b5015 168 * Sets the bits given in mask in register reg.
AtomX 0:1d9c7c0b5015 169 */
AtomX 0:1d9c7c0b5015 170 void MFRC522::PCD_SetRegisterBitMask(uint8_t reg, uint8_t mask)
AtomX 0:1d9c7c0b5015 171 {
AtomX 0:1d9c7c0b5015 172 uint8_t tmp;
AtomX 0:1d9c7c0b5015 173 tmp = PCD_ReadRegister(reg);
AtomX 0:1d9c7c0b5015 174 PCD_WriteRegister(reg, tmp | mask); // set bit mask
AtomX 0:1d9c7c0b5015 175 } // End PCD_SetRegisterBitMask()
AtomX 0:1d9c7c0b5015 176
AtomX 0:1d9c7c0b5015 177 /**
AtomX 0:1d9c7c0b5015 178 * Clears the bits given in mask from register reg.
AtomX 0:1d9c7c0b5015 179 */
AtomX 0:1d9c7c0b5015 180 void MFRC522::PCD_ClearRegisterBitMask(uint8_t reg, uint8_t mask)
AtomX 0:1d9c7c0b5015 181 {
AtomX 0:1d9c7c0b5015 182 uint8_t tmp;
AtomX 0:1d9c7c0b5015 183 tmp = PCD_ReadRegister(reg);
AtomX 0:1d9c7c0b5015 184 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
AtomX 0:1d9c7c0b5015 185 } // End PCD_ClearRegisterBitMask()
AtomX 0:1d9c7c0b5015 186
AtomX 0:1d9c7c0b5015 187
AtomX 0:1d9c7c0b5015 188 /**
AtomX 0:1d9c7c0b5015 189 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
AtomX 0:1d9c7c0b5015 190 *
AtomX 0:1d9c7c0b5015 191 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 192 */
AtomX 0:1d9c7c0b5015 193 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
AtomX 0:1d9c7c0b5015 194 {
AtomX 0:1d9c7c0b5015 195 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
AtomX 0:1d9c7c0b5015 196 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
AtomX 0:1d9c7c0b5015 197 PCD_SetRegisterBitMask(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
AtomX 0:1d9c7c0b5015 198 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
AtomX 0:1d9c7c0b5015 199 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
AtomX 0:1d9c7c0b5015 200
AtomX 0:1d9c7c0b5015 201 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73�s.
AtomX 0:1d9c7c0b5015 202 uint16_t i = 5000;
AtomX 0:1d9c7c0b5015 203 uint8_t n;
AtomX 0:1d9c7c0b5015 204 while (1)
AtomX 0:1d9c7c0b5015 205 {
AtomX 0:1d9c7c0b5015 206 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
AtomX 0:1d9c7c0b5015 207 if (n & 0x04)
AtomX 0:1d9c7c0b5015 208 {
AtomX 0:1d9c7c0b5015 209 // CRCIRq bit set - calculation done
AtomX 0:1d9c7c0b5015 210 break;
AtomX 0:1d9c7c0b5015 211 }
AtomX 0:1d9c7c0b5015 212 if (--i == 0)
AtomX 0:1d9c7c0b5015 213 {
AtomX 0:1d9c7c0b5015 214 // The emergency break. We will eventually terminate on this one after 89ms.
AtomX 0:1d9c7c0b5015 215 // Communication with the MFRC522 might be down.
AtomX 0:1d9c7c0b5015 216 return STATUS_TIMEOUT;
AtomX 0:1d9c7c0b5015 217 }
AtomX 0:1d9c7c0b5015 218 }
AtomX 0:1d9c7c0b5015 219
AtomX 0:1d9c7c0b5015 220 // Stop calculating CRC for new content in the FIFO.
AtomX 0:1d9c7c0b5015 221 PCD_WriteRegister(CommandReg, PCD_Idle);
AtomX 0:1d9c7c0b5015 222
AtomX 0:1d9c7c0b5015 223 // Transfer the result from the registers to the result buffer
AtomX 0:1d9c7c0b5015 224 result[0] = PCD_ReadRegister(CRCResultRegL);
AtomX 0:1d9c7c0b5015 225 result[1] = PCD_ReadRegister(CRCResultRegH);
AtomX 0:1d9c7c0b5015 226 return STATUS_OK;
AtomX 0:1d9c7c0b5015 227 } // End PCD_CalculateCRC()
AtomX 0:1d9c7c0b5015 228
AtomX 0:1d9c7c0b5015 229
AtomX 0:1d9c7c0b5015 230 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 231 // Functions for manipulating the MFRC522
AtomX 0:1d9c7c0b5015 232 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 233
AtomX 0:1d9c7c0b5015 234 /**
AtomX 0:1d9c7c0b5015 235 * Initializes the MFRC522 chip.
AtomX 0:1d9c7c0b5015 236 */
AtomX 0:1d9c7c0b5015 237 void MFRC522::PCD_Init()
AtomX 0:1d9c7c0b5015 238 {
AtomX 0:1d9c7c0b5015 239 /* Reset MFRC522 */
AtomX 0:1d9c7c0b5015 240 m_RESET = 0;
AtomX 0:1d9c7c0b5015 241 wait_ms(10);
AtomX 0:1d9c7c0b5015 242 m_RESET = 1;
AtomX 0:1d9c7c0b5015 243 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74�s. Let us be generous: 50ms.
AtomX 0:1d9c7c0b5015 244 wait_ms(50);
AtomX 0:1d9c7c0b5015 245
AtomX 0:1d9c7c0b5015 246 // When communicating with a PICC we need a timeout if something goes wrong.
AtomX 0:1d9c7c0b5015 247 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
AtomX 0:1d9c7c0b5015 248 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
AtomX 0:1d9c7c0b5015 249 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
AtomX 0:1d9c7c0b5015 250 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25�s.
AtomX 0:1d9c7c0b5015 251 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
AtomX 0:1d9c7c0b5015 252 PCD_WriteRegister(TReloadRegL, 0xE8);
AtomX 0:1d9c7c0b5015 253
AtomX 0:1d9c7c0b5015 254 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
AtomX 0:1d9c7c0b5015 255 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
AtomX 0:1d9c7c0b5015 256 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
AtomX 0:1d9c7c0b5015 257 } // End PCD_Init()
AtomX 0:1d9c7c0b5015 258
AtomX 0:1d9c7c0b5015 259 /**
AtomX 0:1d9c7c0b5015 260 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
AtomX 0:1d9c7c0b5015 261 */
AtomX 0:1d9c7c0b5015 262 void MFRC522::PCD_Reset()
AtomX 0:1d9c7c0b5015 263 {
AtomX 0:1d9c7c0b5015 264 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
AtomX 0:1d9c7c0b5015 265 // The datasheet does not mention how long the SoftRest command takes to complete.
AtomX 0:1d9c7c0b5015 266 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
AtomX 0:1d9c7c0b5015 267 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74�s. Let us be generous: 50ms.
AtomX 0:1d9c7c0b5015 268 wait_ms(50);
AtomX 0:1d9c7c0b5015 269
AtomX 0:1d9c7c0b5015 270 // Wait for the PowerDown bit in CommandReg to be cleared
AtomX 0:1d9c7c0b5015 271 while (PCD_ReadRegister(CommandReg) & (1<<4))
AtomX 0:1d9c7c0b5015 272 {
AtomX 0:1d9c7c0b5015 273 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
AtomX 0:1d9c7c0b5015 274 }
AtomX 0:1d9c7c0b5015 275 } // End PCD_Reset()
AtomX 0:1d9c7c0b5015 276
AtomX 0:1d9c7c0b5015 277 /**
AtomX 0:1d9c7c0b5015 278 * Turns the antenna on by enabling pins TX1 and TX2.
AtomX 0:1d9c7c0b5015 279 * After a reset these pins disabled.
AtomX 0:1d9c7c0b5015 280 */
AtomX 0:1d9c7c0b5015 281 void MFRC522::PCD_AntennaOn()
AtomX 0:1d9c7c0b5015 282 {
AtomX 0:1d9c7c0b5015 283 uint8_t value = PCD_ReadRegister(TxControlReg);
AtomX 0:1d9c7c0b5015 284 if ((value & 0x03) != 0x03)
AtomX 0:1d9c7c0b5015 285 {
AtomX 0:1d9c7c0b5015 286 PCD_WriteRegister(TxControlReg, value | 0x03);
AtomX 0:1d9c7c0b5015 287 }
AtomX 0:1d9c7c0b5015 288 } // End PCD_AntennaOn()
AtomX 0:1d9c7c0b5015 289
AtomX 0:1d9c7c0b5015 290 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 291 // Functions for communicating with PICCs
AtomX 0:1d9c7c0b5015 292 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 293
AtomX 0:1d9c7c0b5015 294 /**
AtomX 0:1d9c7c0b5015 295 * Executes the Transceive command.
AtomX 0:1d9c7c0b5015 296 * CRC validation can only be done if backData and backLen are specified.
AtomX 0:1d9c7c0b5015 297 *
AtomX 0:1d9c7c0b5015 298 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 299 */
AtomX 0:1d9c7c0b5015 300 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData, ///< Pointer to the data to transfer to the FIFO.
AtomX 0:1d9c7c0b5015 301 uint8_t sendLen, ///< Number of bytes to transfer to the FIFO.
AtomX 0:1d9c7c0b5015 302 uint8_t *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
AtomX 0:1d9c7c0b5015 303 uint8_t *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 0:1d9c7c0b5015 304 uint8_t *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits. Default NULL.
AtomX 0:1d9c7c0b5015 305 uint8_t rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 0:1d9c7c0b5015 306 bool checkCRC) ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 0:1d9c7c0b5015 307 {
AtomX 0:1d9c7c0b5015 308 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
AtomX 0:1d9c7c0b5015 309 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
AtomX 0:1d9c7c0b5015 310 } // End PCD_TransceiveData()
AtomX 0:1d9c7c0b5015 311
AtomX 0:1d9c7c0b5015 312 /**
AtomX 0:1d9c7c0b5015 313 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
AtomX 0:1d9c7c0b5015 314 * CRC validation can only be done if backData and backLen are specified.
AtomX 0:1d9c7c0b5015 315 *
AtomX 0:1d9c7c0b5015 316 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 317 */
AtomX 0:1d9c7c0b5015 318 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command, ///< The command to execute. One of the PCD_Command enums.
AtomX 0:1d9c7c0b5015 319 uint8_t waitIRq, ///< The bits in the ComIrqReg register that signals successful completion of the command.
AtomX 0:1d9c7c0b5015 320 uint8_t *sendData, ///< Pointer to the data to transfer to the FIFO.
AtomX 0:1d9c7c0b5015 321 uint8_t sendLen, ///< Number of bytes to transfer to the FIFO.
AtomX 0:1d9c7c0b5015 322 uint8_t *backData, ///< NULL or pointer to buffer if data should be read back after executing the command.
AtomX 0:1d9c7c0b5015 323 uint8_t *backLen, ///< In: Max number of bytes to write to *backData. Out: The number of bytes returned.
AtomX 0:1d9c7c0b5015 324 uint8_t *validBits, ///< In/Out: The number of valid bits in the last byte. 0 for 8 valid bits.
AtomX 0:1d9c7c0b5015 325 uint8_t rxAlign, ///< In: Defines the bit position in backData[0] for the first bit received. Default 0.
AtomX 0:1d9c7c0b5015 326 bool checkCRC) ///< In: True => The last two bytes of the response is assumed to be a CRC_A that must be validated.
AtomX 0:1d9c7c0b5015 327 {
AtomX 0:1d9c7c0b5015 328 uint8_t n, _validBits = 0;
AtomX 0:1d9c7c0b5015 329 uint32_t i;
AtomX 0:1d9c7c0b5015 330
AtomX 0:1d9c7c0b5015 331 // Prepare values for BitFramingReg
AtomX 0:1d9c7c0b5015 332 uint8_t txLastBits = validBits ? *validBits : 0;
AtomX 0:1d9c7c0b5015 333 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
AtomX 0:1d9c7c0b5015 334
AtomX 0:1d9c7c0b5015 335 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
AtomX 0:1d9c7c0b5015 336 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
AtomX 0:1d9c7c0b5015 337 PCD_SetRegisterBitMask(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
AtomX 0:1d9c7c0b5015 338 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
AtomX 0:1d9c7c0b5015 339 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
AtomX 0:1d9c7c0b5015 340 PCD_WriteRegister(CommandReg, command); // Execute the command
AtomX 0:1d9c7c0b5015 341 if (command == PCD_Transceive)
AtomX 0:1d9c7c0b5015 342 {
AtomX 0:1d9c7c0b5015 343 PCD_SetRegisterBitMask(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
AtomX 0:1d9c7c0b5015 344 }
AtomX 0:1d9c7c0b5015 345
AtomX 0:1d9c7c0b5015 346 // Wait for the command to complete.
AtomX 0:1d9c7c0b5015 347 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
AtomX 0:1d9c7c0b5015 348 // Each iteration of the do-while-loop takes 17.86�s.
AtomX 0:1d9c7c0b5015 349 i = 2000;
AtomX 0:1d9c7c0b5015 350 while (1)
AtomX 0:1d9c7c0b5015 351 {
AtomX 0:1d9c7c0b5015 352 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
AtomX 0:1d9c7c0b5015 353 if (n & waitIRq)
AtomX 0:1d9c7c0b5015 354 { // One of the interrupts that signal success has been set.
AtomX 0:1d9c7c0b5015 355 break;
AtomX 0:1d9c7c0b5015 356 }
AtomX 0:1d9c7c0b5015 357
AtomX 0:1d9c7c0b5015 358 if (n & 0x01)
AtomX 0:1d9c7c0b5015 359 { // Timer interrupt - nothing received in 25ms
AtomX 0:1d9c7c0b5015 360 return STATUS_TIMEOUT;
AtomX 0:1d9c7c0b5015 361 }
AtomX 0:1d9c7c0b5015 362
AtomX 0:1d9c7c0b5015 363 if (--i == 0)
AtomX 0:1d9c7c0b5015 364 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
AtomX 0:1d9c7c0b5015 365 return STATUS_TIMEOUT;
AtomX 0:1d9c7c0b5015 366 }
AtomX 0:1d9c7c0b5015 367 }
AtomX 0:1d9c7c0b5015 368
AtomX 0:1d9c7c0b5015 369 // Stop now if any errors except collisions were detected.
AtomX 0:1d9c7c0b5015 370 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
AtomX 0:1d9c7c0b5015 371 if (errorRegValue & 0x13)
AtomX 0:1d9c7c0b5015 372 { // BufferOvfl ParityErr ProtocolErr
AtomX 0:1d9c7c0b5015 373 return STATUS_ERROR;
AtomX 0:1d9c7c0b5015 374 }
AtomX 0:1d9c7c0b5015 375
AtomX 0:1d9c7c0b5015 376 // If the caller wants data back, get it from the MFRC522.
AtomX 0:1d9c7c0b5015 377 if (backData && backLen)
AtomX 0:1d9c7c0b5015 378 {
AtomX 0:1d9c7c0b5015 379 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
AtomX 0:1d9c7c0b5015 380 if (n > *backLen)
AtomX 0:1d9c7c0b5015 381 {
AtomX 0:1d9c7c0b5015 382 return STATUS_NO_ROOM;
AtomX 0:1d9c7c0b5015 383 }
AtomX 0:1d9c7c0b5015 384
AtomX 0:1d9c7c0b5015 385 *backLen = n; // Number of bytes returned
AtomX 0:1d9c7c0b5015 386 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
AtomX 0:1d9c7c0b5015 387 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
AtomX 0:1d9c7c0b5015 388 if (validBits)
AtomX 0:1d9c7c0b5015 389 {
AtomX 0:1d9c7c0b5015 390 *validBits = _validBits;
AtomX 0:1d9c7c0b5015 391 }
AtomX 0:1d9c7c0b5015 392 }
AtomX 0:1d9c7c0b5015 393
AtomX 0:1d9c7c0b5015 394 // Tell about collisions
AtomX 0:1d9c7c0b5015 395 if (errorRegValue & 0x08) { // CollErr
AtomX 0:1d9c7c0b5015 396 return STATUS_COLLISION;
AtomX 0:1d9c7c0b5015 397 }
AtomX 0:1d9c7c0b5015 398
AtomX 0:1d9c7c0b5015 399 // Perform CRC_A validation if requested.
AtomX 0:1d9c7c0b5015 400 if (backData && backLen && checkCRC)
AtomX 0:1d9c7c0b5015 401 {
AtomX 0:1d9c7c0b5015 402 // In this case a MIFARE Classic NAK is not OK.
AtomX 0:1d9c7c0b5015 403 if (*backLen == 1 && _validBits == 4)
AtomX 0:1d9c7c0b5015 404 {
AtomX 0:1d9c7c0b5015 405 return STATUS_MIFARE_NACK;
AtomX 0:1d9c7c0b5015 406 }
AtomX 0:1d9c7c0b5015 407
AtomX 0:1d9c7c0b5015 408 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
AtomX 0:1d9c7c0b5015 409 if (*backLen < 2 || _validBits != 0)
AtomX 0:1d9c7c0b5015 410 {
AtomX 0:1d9c7c0b5015 411 return STATUS_CRC_WRONG;
AtomX 0:1d9c7c0b5015 412 }
AtomX 0:1d9c7c0b5015 413
AtomX 0:1d9c7c0b5015 414 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
AtomX 0:1d9c7c0b5015 415 uint8_t controlBuffer[2];
AtomX 0:1d9c7c0b5015 416 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
AtomX 0:1d9c7c0b5015 417 if (n != STATUS_OK)
AtomX 0:1d9c7c0b5015 418 {
AtomX 0:1d9c7c0b5015 419 return n;
AtomX 0:1d9c7c0b5015 420 }
AtomX 0:1d9c7c0b5015 421
AtomX 0:1d9c7c0b5015 422 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
AtomX 0:1d9c7c0b5015 423 {
AtomX 0:1d9c7c0b5015 424 return STATUS_CRC_WRONG;
AtomX 0:1d9c7c0b5015 425 }
AtomX 0:1d9c7c0b5015 426 }
AtomX 0:1d9c7c0b5015 427
AtomX 0:1d9c7c0b5015 428 return STATUS_OK;
AtomX 0:1d9c7c0b5015 429 } // End PCD_CommunicateWithPICC()
AtomX 0:1d9c7c0b5015 430
AtomX 0:1d9c7c0b5015 431 /**
AtomX 0:1d9c7c0b5015 432 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
AtomX 0:1d9c7c0b5015 433 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:1d9c7c0b5015 434 *
AtomX 0:1d9c7c0b5015 435 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 436 */
AtomX 0:1d9c7c0b5015 437 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:1d9c7c0b5015 438 {
AtomX 0:1d9c7c0b5015 439 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
AtomX 0:1d9c7c0b5015 440 } // End PICC_RequestA()
AtomX 0:1d9c7c0b5015 441
AtomX 0:1d9c7c0b5015 442 /**
AtomX 0:1d9c7c0b5015 443 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
AtomX 0:1d9c7c0b5015 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:1d9c7c0b5015 445 *
AtomX 0:1d9c7c0b5015 446 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 447 */
AtomX 0:1d9c7c0b5015 448 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:1d9c7c0b5015 449 {
AtomX 0:1d9c7c0b5015 450 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
AtomX 0:1d9c7c0b5015 451 } // End PICC_WakeupA()
AtomX 0:1d9c7c0b5015 452
AtomX 0:1d9c7c0b5015 453 /**
AtomX 0:1d9c7c0b5015 454 * Transmits REQA or WUPA commands.
AtomX 0:1d9c7c0b5015 455 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
AtomX 0:1d9c7c0b5015 456 *
AtomX 0:1d9c7c0b5015 457 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 458 */
AtomX 0:1d9c7c0b5015 459 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
AtomX 0:1d9c7c0b5015 460 {
AtomX 0:1d9c7c0b5015 461 uint8_t validBits;
AtomX 0:1d9c7c0b5015 462 uint8_t status;
AtomX 0:1d9c7c0b5015 463
AtomX 0:1d9c7c0b5015 464 if (bufferATQA == NULL || *bufferSize < 2) { // The ATQA response is 2 bytes long.
AtomX 0:1d9c7c0b5015 465 return STATUS_NO_ROOM;
AtomX 0:1d9c7c0b5015 466 }
AtomX 0:1d9c7c0b5015 467
AtomX 0:1d9c7c0b5015 468 PCD_ClearRegisterBitMask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
AtomX 0:1d9c7c0b5015 469 validBits = 7; // For REQA and WUPA we need the short frame format - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
AtomX 0:1d9c7c0b5015 470 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
AtomX 0:1d9c7c0b5015 471 if (status != STATUS_OK)
AtomX 0:1d9c7c0b5015 472 {
AtomX 0:1d9c7c0b5015 473 return status;
AtomX 0:1d9c7c0b5015 474 }
AtomX 0:1d9c7c0b5015 475
AtomX 0:1d9c7c0b5015 476 if (*bufferSize != 2 || validBits != 0) { // ATQA must be exactly 16 bits.
AtomX 0:1d9c7c0b5015 477 return STATUS_ERROR;
AtomX 0:1d9c7c0b5015 478 }
AtomX 0:1d9c7c0b5015 479
AtomX 0:1d9c7c0b5015 480 return STATUS_OK;
AtomX 0:1d9c7c0b5015 481 } // End PICC_REQA_or_WUPA()
AtomX 0:1d9c7c0b5015 482
AtomX 0:1d9c7c0b5015 483 /**
AtomX 0:1d9c7c0b5015 484 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
AtomX 0:1d9c7c0b5015 485 * Before calling this function the PICCs must be placed in the READY(*) state by calling PICC_RequestA() or PICC_WakeupA().
AtomX 0:1d9c7c0b5015 486 * On success:
AtomX 0:1d9c7c0b5015 487 * - The chosen PICC is in state ACTIVE(*) and all other PICCs have returned to state IDLE/HALT. (Figure 7 of the ISO/IEC 14443-3 draft.)
AtomX 0:1d9c7c0b5015 488 * - The UID size and value of the chosen PICC is returned in *uid along with the SAK.
AtomX 0:1d9c7c0b5015 489 *
AtomX 0:1d9c7c0b5015 490 * A PICC UID consists of 4, 7 or 10 bytes.
AtomX 0:1d9c7c0b5015 491 * Only 4 bytes can be specified in a SELECT command, so for the longer UIDs two or three iterations are used:
AtomX 0:1d9c7c0b5015 492 * UID size Number of UID bytes Cascade levels Example of PICC
AtomX 0:1d9c7c0b5015 493 * ======== =================== ============== ===============
AtomX 0:1d9c7c0b5015 494 * single 4 1 MIFARE Classic
AtomX 0:1d9c7c0b5015 495 * double 7 2 MIFARE Ultralight
AtomX 0:1d9c7c0b5015 496 * triple 10 3 Not currently in use?
AtomX 0:1d9c7c0b5015 497 *
AtomX 0:1d9c7c0b5015 498 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 499 */
AtomX 0:1d9c7c0b5015 500 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
AtomX 0:1d9c7c0b5015 501 {
AtomX 0:1d9c7c0b5015 502 bool uidComplete;
AtomX 0:1d9c7c0b5015 503 bool selectDone;
AtomX 0:1d9c7c0b5015 504 bool useCascadeTag;
AtomX 0:1d9c7c0b5015 505 uint8_t cascadeLevel = 1;
AtomX 0:1d9c7c0b5015 506 uint8_t result;
AtomX 0:1d9c7c0b5015 507 uint8_t count;
AtomX 0:1d9c7c0b5015 508 uint8_t index;
AtomX 0:1d9c7c0b5015 509 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
AtomX 0:1d9c7c0b5015 510 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
AtomX 0:1d9c7c0b5015 511 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
AtomX 0:1d9c7c0b5015 512 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
AtomX 0:1d9c7c0b5015 513 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
AtomX 0:1d9c7c0b5015 514 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
AtomX 0:1d9c7c0b5015 515 uint8_t *responseBuffer;
AtomX 0:1d9c7c0b5015 516 uint8_t responseLength;
AtomX 0:1d9c7c0b5015 517
AtomX 0:1d9c7c0b5015 518 // Description of buffer structure:
AtomX 0:1d9c7c0b5015 519 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
AtomX 0:1d9c7c0b5015 520 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
AtomX 0:1d9c7c0b5015 521 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
AtomX 0:1d9c7c0b5015 522 // Byte 3: UID-data
AtomX 0:1d9c7c0b5015 523 // Byte 4: UID-data
AtomX 0:1d9c7c0b5015 524 // Byte 5: UID-data
AtomX 0:1d9c7c0b5015 525 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
AtomX 0:1d9c7c0b5015 526 // Byte 7: CRC_A
AtomX 0:1d9c7c0b5015 527 // Byte 8: CRC_A
AtomX 0:1d9c7c0b5015 528 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
AtomX 0:1d9c7c0b5015 529 //
AtomX 0:1d9c7c0b5015 530 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
AtomX 0:1d9c7c0b5015 531 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
AtomX 0:1d9c7c0b5015 532 // ======== ============= ===== ===== ===== =====
AtomX 0:1d9c7c0b5015 533 // 4 bytes 1 uid0 uid1 uid2 uid3
AtomX 0:1d9c7c0b5015 534 // 7 bytes 1 CT uid0 uid1 uid2
AtomX 0:1d9c7c0b5015 535 // 2 uid3 uid4 uid5 uid6
AtomX 0:1d9c7c0b5015 536 // 10 bytes 1 CT uid0 uid1 uid2
AtomX 0:1d9c7c0b5015 537 // 2 CT uid3 uid4 uid5
AtomX 0:1d9c7c0b5015 538 // 3 uid6 uid7 uid8 uid9
AtomX 0:1d9c7c0b5015 539
AtomX 0:1d9c7c0b5015 540 // Sanity checks
AtomX 0:1d9c7c0b5015 541 if (validBits > 80)
AtomX 0:1d9c7c0b5015 542 {
AtomX 0:1d9c7c0b5015 543 return STATUS_INVALID;
AtomX 0:1d9c7c0b5015 544 }
AtomX 0:1d9c7c0b5015 545
AtomX 0:1d9c7c0b5015 546 // Prepare MFRC522
AtomX 0:1d9c7c0b5015 547 PCD_ClearRegisterBitMask(CollReg, 0x80); // ValuesAfterColl=1 => Bits received after collision are cleared.
AtomX 0:1d9c7c0b5015 548
AtomX 0:1d9c7c0b5015 549 // Repeat Cascade Level loop until we have a complete UID.
AtomX 0:1d9c7c0b5015 550 uidComplete = false;
AtomX 0:1d9c7c0b5015 551 while ( ! uidComplete)
AtomX 0:1d9c7c0b5015 552 {
AtomX 0:1d9c7c0b5015 553 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
AtomX 0:1d9c7c0b5015 554 switch (cascadeLevel)
AtomX 0:1d9c7c0b5015 555 {
AtomX 0:1d9c7c0b5015 556 case 1:
AtomX 0:1d9c7c0b5015 557 buffer[0] = PICC_CMD_SEL_CL1;
AtomX 0:1d9c7c0b5015 558 uidIndex = 0;
AtomX 0:1d9c7c0b5015 559 useCascadeTag = validBits && uid->size > 4; // When we know that the UID has more than 4 bytes
AtomX 0:1d9c7c0b5015 560 break;
AtomX 0:1d9c7c0b5015 561
AtomX 0:1d9c7c0b5015 562 case 2:
AtomX 0:1d9c7c0b5015 563 buffer[0] = PICC_CMD_SEL_CL2;
AtomX 0:1d9c7c0b5015 564 uidIndex = 3;
AtomX 0:1d9c7c0b5015 565 useCascadeTag = validBits && uid->size > 7; // When we know that the UID has more than 7 bytes
AtomX 0:1d9c7c0b5015 566 break;
AtomX 0:1d9c7c0b5015 567
AtomX 0:1d9c7c0b5015 568 case 3:
AtomX 0:1d9c7c0b5015 569 buffer[0] = PICC_CMD_SEL_CL3;
AtomX 0:1d9c7c0b5015 570 uidIndex = 6;
AtomX 0:1d9c7c0b5015 571 useCascadeTag = false; // Never used in CL3.
AtomX 0:1d9c7c0b5015 572 break;
AtomX 0:1d9c7c0b5015 573
AtomX 0:1d9c7c0b5015 574 default:
AtomX 0:1d9c7c0b5015 575 return STATUS_INTERNAL_ERROR;
AtomX 0:1d9c7c0b5015 576 //break;
AtomX 0:1d9c7c0b5015 577 }
AtomX 0:1d9c7c0b5015 578
AtomX 0:1d9c7c0b5015 579 // How many UID bits are known in this Cascade Level?
AtomX 0:1d9c7c0b5015 580 if(validBits > (8 * uidIndex))
AtomX 0:1d9c7c0b5015 581 {
AtomX 0:1d9c7c0b5015 582 currentLevelKnownBits = validBits - (8 * uidIndex);
AtomX 0:1d9c7c0b5015 583 }
AtomX 0:1d9c7c0b5015 584 else
AtomX 0:1d9c7c0b5015 585 {
AtomX 0:1d9c7c0b5015 586 currentLevelKnownBits = 0;
AtomX 0:1d9c7c0b5015 587 }
AtomX 0:1d9c7c0b5015 588 // Copy the known bits from uid->uidByte[] to buffer[]
AtomX 0:1d9c7c0b5015 589 index = 2; // destination index in buffer[]
AtomX 0:1d9c7c0b5015 590 if (useCascadeTag)
AtomX 0:1d9c7c0b5015 591 {
AtomX 0:1d9c7c0b5015 592 buffer[index++] = PICC_CMD_CT;
AtomX 0:1d9c7c0b5015 593 }
AtomX 0:1d9c7c0b5015 594
AtomX 0:1d9c7c0b5015 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
AtomX 0:1d9c7c0b5015 596 if (bytesToCopy)
AtomX 0:1d9c7c0b5015 597 {
AtomX 0:1d9c7c0b5015 598 uint8_t maxBytes = useCascadeTag ? 3 : 4; // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
AtomX 0:1d9c7c0b5015 599 if (bytesToCopy > maxBytes)
AtomX 0:1d9c7c0b5015 600 {
AtomX 0:1d9c7c0b5015 601 bytesToCopy = maxBytes;
AtomX 0:1d9c7c0b5015 602 }
AtomX 0:1d9c7c0b5015 603
AtomX 0:1d9c7c0b5015 604 for (count = 0; count < bytesToCopy; count++)
AtomX 0:1d9c7c0b5015 605 {
AtomX 0:1d9c7c0b5015 606 buffer[index++] = uid->uidByte[uidIndex + count];
AtomX 0:1d9c7c0b5015 607 }
AtomX 0:1d9c7c0b5015 608 }
AtomX 0:1d9c7c0b5015 609 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
AtomX 0:1d9c7c0b5015 610 if (useCascadeTag)
AtomX 0:1d9c7c0b5015 611 {
AtomX 0:1d9c7c0b5015 612 currentLevelKnownBits += 8;
AtomX 0:1d9c7c0b5015 613 }
AtomX 0:1d9c7c0b5015 614
AtomX 0:1d9c7c0b5015 615 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
AtomX 0:1d9c7c0b5015 616 selectDone = false;
AtomX 0:1d9c7c0b5015 617 while ( ! selectDone)
AtomX 0:1d9c7c0b5015 618 {
AtomX 0:1d9c7c0b5015 619 // Find out how many bits and bytes to send and receive.
AtomX 0:1d9c7c0b5015 620 if (currentLevelKnownBits >= 32) { // All UID bits in this Cascade Level are known. This is a SELECT.
AtomX 0:1d9c7c0b5015 621 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
AtomX 0:1d9c7c0b5015 622 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
AtomX 0:1d9c7c0b5015 623 // Calulate BCC - Block Check Character
AtomX 0:1d9c7c0b5015 624 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
AtomX 0:1d9c7c0b5015 625 // Calculate CRC_A
AtomX 0:1d9c7c0b5015 626 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
AtomX 0:1d9c7c0b5015 627 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 628 {
AtomX 0:1d9c7c0b5015 629 return result;
AtomX 0:1d9c7c0b5015 630 }
AtomX 0:1d9c7c0b5015 631 txLastBits = 0; // 0 => All 8 bits are valid.
AtomX 0:1d9c7c0b5015 632 bufferUsed = 9;
AtomX 0:1d9c7c0b5015 633 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
AtomX 0:1d9c7c0b5015 634 responseBuffer = &buffer[6];
AtomX 0:1d9c7c0b5015 635 responseLength = 3;
AtomX 0:1d9c7c0b5015 636 }
AtomX 0:1d9c7c0b5015 637 else { // This is an ANTICOLLISION.
AtomX 0:1d9c7c0b5015 638 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
AtomX 0:1d9c7c0b5015 639 txLastBits = currentLevelKnownBits % 8;
AtomX 0:1d9c7c0b5015 640 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
AtomX 0:1d9c7c0b5015 641 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
AtomX 0:1d9c7c0b5015 642 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
AtomX 0:1d9c7c0b5015 643 bufferUsed = index + (txLastBits ? 1 : 0);
AtomX 0:1d9c7c0b5015 644 // Store response in the unused part of buffer
AtomX 0:1d9c7c0b5015 645 responseBuffer = &buffer[index];
AtomX 0:1d9c7c0b5015 646 responseLength = sizeof(buffer) - index;
AtomX 0:1d9c7c0b5015 647 }
AtomX 0:1d9c7c0b5015 648
AtomX 0:1d9c7c0b5015 649 // Set bit adjustments
AtomX 0:1d9c7c0b5015 650 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
AtomX 0:1d9c7c0b5015 651 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
AtomX 0:1d9c7c0b5015 652
AtomX 0:1d9c7c0b5015 653 // Transmit the buffer and receive the response.
AtomX 0:1d9c7c0b5015 654 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
AtomX 0:1d9c7c0b5015 655 if (result == STATUS_COLLISION) { // More than one PICC in the field => collision.
AtomX 0:1d9c7c0b5015 656 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
AtomX 0:1d9c7c0b5015 657 if (result & 0x20) { // CollPosNotValid
AtomX 0:1d9c7c0b5015 658 return STATUS_COLLISION; // Without a valid collision position we cannot continue
AtomX 0:1d9c7c0b5015 659 }
AtomX 0:1d9c7c0b5015 660 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
AtomX 0:1d9c7c0b5015 661 if (collisionPos == 0)
AtomX 0:1d9c7c0b5015 662 {
AtomX 0:1d9c7c0b5015 663 collisionPos = 32;
AtomX 0:1d9c7c0b5015 664 }
AtomX 0:1d9c7c0b5015 665 if (collisionPos <= currentLevelKnownBits) { // No progress - should not happen
AtomX 0:1d9c7c0b5015 666 return STATUS_INTERNAL_ERROR;
AtomX 0:1d9c7c0b5015 667 }
AtomX 0:1d9c7c0b5015 668 // Choose the PICC with the bit set.
AtomX 0:1d9c7c0b5015 669 currentLevelKnownBits = collisionPos;
AtomX 0:1d9c7c0b5015 670 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
AtomX 0:1d9c7c0b5015 671 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
AtomX 0:1d9c7c0b5015 672 buffer[index] |= (1 << count);
AtomX 0:1d9c7c0b5015 673 }
AtomX 0:1d9c7c0b5015 674 else if (result != STATUS_OK) {
AtomX 0:1d9c7c0b5015 675 return result;
AtomX 0:1d9c7c0b5015 676 }
AtomX 0:1d9c7c0b5015 677 else { // STATUS_OK
AtomX 0:1d9c7c0b5015 678 if (currentLevelKnownBits >= 32) { // This was a SELECT.
AtomX 0:1d9c7c0b5015 679 selectDone = true; // No more anticollision
AtomX 0:1d9c7c0b5015 680 // We continue below outside the while.
AtomX 0:1d9c7c0b5015 681 }
AtomX 0:1d9c7c0b5015 682 else { // This was an ANTICOLLISION.
AtomX 0:1d9c7c0b5015 683 // We now have all 32 bits of the UID in this Cascade Level
AtomX 0:1d9c7c0b5015 684 currentLevelKnownBits = 32;
AtomX 0:1d9c7c0b5015 685 // Run loop again to do the SELECT.
AtomX 0:1d9c7c0b5015 686 }
AtomX 0:1d9c7c0b5015 687 }
AtomX 0:1d9c7c0b5015 688 } // End of while ( ! selectDone)
AtomX 0:1d9c7c0b5015 689
AtomX 0:1d9c7c0b5015 690 // We do not check the CBB - it was constructed by us above.
AtomX 0:1d9c7c0b5015 691
AtomX 0:1d9c7c0b5015 692 // Copy the found UID bytes from buffer[] to uid->uidByte[]
AtomX 0:1d9c7c0b5015 693 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
AtomX 0:1d9c7c0b5015 694 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
AtomX 0:1d9c7c0b5015 695 for (count = 0; count < bytesToCopy; count++)
AtomX 0:1d9c7c0b5015 696 {
AtomX 0:1d9c7c0b5015 697 uid->uidByte[uidIndex + count] = buffer[index++];
AtomX 0:1d9c7c0b5015 698 }
AtomX 0:1d9c7c0b5015 699
AtomX 0:1d9c7c0b5015 700 // Check response SAK (Select Acknowledge)
AtomX 0:1d9c7c0b5015 701 if (responseLength != 3 || txLastBits != 0) { // SAK must be exactly 24 bits (1 byte + CRC_A).
AtomX 0:1d9c7c0b5015 702 return STATUS_ERROR;
AtomX 0:1d9c7c0b5015 703 }
AtomX 0:1d9c7c0b5015 704 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
AtomX 0:1d9c7c0b5015 705 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
AtomX 0:1d9c7c0b5015 706 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 707 {
AtomX 0:1d9c7c0b5015 708 return result;
AtomX 0:1d9c7c0b5015 709 }
AtomX 0:1d9c7c0b5015 710 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
AtomX 0:1d9c7c0b5015 711 {
AtomX 0:1d9c7c0b5015 712 return STATUS_CRC_WRONG;
AtomX 0:1d9c7c0b5015 713 }
AtomX 0:1d9c7c0b5015 714 if (responseBuffer[0] & 0x04) { // Cascade bit set - UID not complete yes
AtomX 0:1d9c7c0b5015 715 cascadeLevel++;
AtomX 0:1d9c7c0b5015 716 }
AtomX 0:1d9c7c0b5015 717 else
AtomX 0:1d9c7c0b5015 718 {
AtomX 0:1d9c7c0b5015 719 uidComplete = true;
AtomX 0:1d9c7c0b5015 720 uid->sak = responseBuffer[0];
AtomX 0:1d9c7c0b5015 721 }
AtomX 0:1d9c7c0b5015 722 } // End of while ( ! uidComplete)
AtomX 0:1d9c7c0b5015 723
AtomX 0:1d9c7c0b5015 724 // Set correct uid->size
AtomX 0:1d9c7c0b5015 725 uid->size = 3 * cascadeLevel + 1;
AtomX 0:1d9c7c0b5015 726
AtomX 0:1d9c7c0b5015 727 return STATUS_OK;
AtomX 0:1d9c7c0b5015 728 } // End PICC_Select()
AtomX 0:1d9c7c0b5015 729
AtomX 0:1d9c7c0b5015 730 /**
AtomX 0:1d9c7c0b5015 731 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
AtomX 0:1d9c7c0b5015 732 *
AtomX 0:1d9c7c0b5015 733 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 734 */
AtomX 0:1d9c7c0b5015 735 uint8_t MFRC522::PICC_HaltA()
AtomX 0:1d9c7c0b5015 736 {
AtomX 0:1d9c7c0b5015 737 uint8_t result;
AtomX 0:1d9c7c0b5015 738 uint8_t buffer[4];
AtomX 0:1d9c7c0b5015 739
AtomX 0:1d9c7c0b5015 740 // Build command buffer
AtomX 0:1d9c7c0b5015 741 buffer[0] = PICC_CMD_HLTA;
AtomX 0:1d9c7c0b5015 742 buffer[1] = 0;
AtomX 0:1d9c7c0b5015 743 // Calculate CRC_A
AtomX 0:1d9c7c0b5015 744 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
AtomX 0:1d9c7c0b5015 745 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 746 {
AtomX 0:1d9c7c0b5015 747 return result;
AtomX 0:1d9c7c0b5015 748 }
AtomX 0:1d9c7c0b5015 749
AtomX 0:1d9c7c0b5015 750 // Send the command.
AtomX 0:1d9c7c0b5015 751 // The standard says:
AtomX 0:1d9c7c0b5015 752 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
AtomX 0:1d9c7c0b5015 753 // HLTA command, this response shall be interpreted as 'not acknowledge'.
AtomX 0:1d9c7c0b5015 754 // We interpret that this way: Only STATUS_TIMEOUT is an success.
AtomX 0:1d9c7c0b5015 755 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
AtomX 0:1d9c7c0b5015 756 if (result == STATUS_TIMEOUT)
AtomX 0:1d9c7c0b5015 757 {
AtomX 0:1d9c7c0b5015 758 return STATUS_OK;
AtomX 0:1d9c7c0b5015 759 }
AtomX 0:1d9c7c0b5015 760 if (result == STATUS_OK) { // That is ironically NOT ok in this case ;-)
AtomX 0:1d9c7c0b5015 761 return STATUS_ERROR;
AtomX 0:1d9c7c0b5015 762 }
AtomX 0:1d9c7c0b5015 763 return result;
AtomX 0:1d9c7c0b5015 764 } // End PICC_HaltA()
AtomX 0:1d9c7c0b5015 765
AtomX 0:1d9c7c0b5015 766
AtomX 0:1d9c7c0b5015 767 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 768 // Functions for communicating with MIFARE PICCs
AtomX 0:1d9c7c0b5015 769 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 770
AtomX 0:1d9c7c0b5015 771 /**
AtomX 0:1d9c7c0b5015 772 * Executes the MFRC522 MFAuthent command.
AtomX 0:1d9c7c0b5015 773 * This command manages MIFARE authentication to enable a secure communication to any MIFARE Mini, MIFARE 1K and MIFARE 4K card.
AtomX 0:1d9c7c0b5015 774 * The authentication is described in the MFRC522 datasheet section 10.3.1.9 and http://www.nxp.com/documents/data_sheet/MF1S503x.pdf section 10.1.
AtomX 0:1d9c7c0b5015 775 * For use with MIFARE Classic PICCs.
AtomX 0:1d9c7c0b5015 776 * The PICC must be selected - ie in state ACTIVE(*) - before calling this function.
AtomX 0:1d9c7c0b5015 777 * Remember to call PCD_StopCrypto1() after communicating with the authenticated PICC - otherwise no new communications can start.
AtomX 0:1d9c7c0b5015 778 *
AtomX 0:1d9c7c0b5015 779 * All keys are set to FFFFFFFFFFFFh at chip delivery.
AtomX 0:1d9c7c0b5015 780 *
AtomX 0:1d9c7c0b5015 781 * @return STATUS_OK on success, STATUS_??? otherwise. Probably STATUS_TIMEOUT if you supply the wrong key.
AtomX 0:1d9c7c0b5015 782 */
AtomX 0:1d9c7c0b5015 783 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
AtomX 0:1d9c7c0b5015 784 {
AtomX 0:1d9c7c0b5015 785 uint8_t waitIRq = 0x10; // IdleIRq
AtomX 0:1d9c7c0b5015 786
AtomX 0:1d9c7c0b5015 787 // Build command buffer
AtomX 0:1d9c7c0b5015 788 uint8_t sendData[12];
AtomX 0:1d9c7c0b5015 789 sendData[0] = command;
AtomX 0:1d9c7c0b5015 790 sendData[1] = blockAddr;
AtomX 0:1d9c7c0b5015 791 for (uint8_t i = 0; i < MF_KEY_SIZE; i++) { // 6 key bytes
AtomX 0:1d9c7c0b5015 792 sendData[2+i] = key->keyByte[i];
AtomX 0:1d9c7c0b5015 793 }
AtomX 0:1d9c7c0b5015 794 for (uint8_t i = 0; i < 4; i++) { // The first 4 bytes of the UID
AtomX 0:1d9c7c0b5015 795 sendData[8+i] = uid->uidByte[i];
AtomX 0:1d9c7c0b5015 796 }
AtomX 0:1d9c7c0b5015 797
AtomX 0:1d9c7c0b5015 798 // Start the authentication.
AtomX 0:1d9c7c0b5015 799 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
AtomX 0:1d9c7c0b5015 800 } // End PCD_Authenticate()
AtomX 0:1d9c7c0b5015 801
AtomX 0:1d9c7c0b5015 802 /**
AtomX 0:1d9c7c0b5015 803 * Used to exit the PCD from its authenticated state.
AtomX 0:1d9c7c0b5015 804 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
AtomX 0:1d9c7c0b5015 805 */
AtomX 0:1d9c7c0b5015 806 void MFRC522::PCD_StopCrypto1()
AtomX 0:1d9c7c0b5015 807 {
AtomX 0:1d9c7c0b5015 808 // Clear MFCrypto1On bit
AtomX 0:1d9c7c0b5015 809 PCD_ClearRegisterBitMask(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
AtomX 0:1d9c7c0b5015 810 } // End PCD_StopCrypto1()
AtomX 0:1d9c7c0b5015 811
AtomX 0:1d9c7c0b5015 812 /**
AtomX 0:1d9c7c0b5015 813 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
AtomX 0:1d9c7c0b5015 814 *
AtomX 0:1d9c7c0b5015 815 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 816 *
AtomX 0:1d9c7c0b5015 817 * For MIFARE Ultralight only addresses 00h to 0Fh are decoded.
AtomX 0:1d9c7c0b5015 818 * The MF0ICU1 returns a NAK for higher addresses.
AtomX 0:1d9c7c0b5015 819 * The MF0ICU1 responds to the READ command by sending 16 bytes starting from the page address defined by the command argument.
AtomX 0:1d9c7c0b5015 820 * For example; if blockAddr is 03h then pages 03h, 04h, 05h, 06h are returned.
AtomX 0:1d9c7c0b5015 821 * A roll-back is implemented: If blockAddr is 0Eh, then the contents of pages 0Eh, 0Fh, 00h and 01h are returned.
AtomX 0:1d9c7c0b5015 822 *
AtomX 0:1d9c7c0b5015 823 * The buffer must be at least 18 bytes because a CRC_A is also returned.
AtomX 0:1d9c7c0b5015 824 * Checks the CRC_A before returning STATUS_OK.
AtomX 0:1d9c7c0b5015 825 *
AtomX 0:1d9c7c0b5015 826 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 827 */
AtomX 0:1d9c7c0b5015 828 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
AtomX 0:1d9c7c0b5015 829 {
AtomX 0:1d9c7c0b5015 830 uint8_t result;
AtomX 0:1d9c7c0b5015 831
AtomX 0:1d9c7c0b5015 832 // Sanity check
AtomX 0:1d9c7c0b5015 833 if (buffer == NULL || *bufferSize < 18)
AtomX 0:1d9c7c0b5015 834 {
AtomX 0:1d9c7c0b5015 835 return STATUS_NO_ROOM;
AtomX 0:1d9c7c0b5015 836 }
AtomX 0:1d9c7c0b5015 837
AtomX 0:1d9c7c0b5015 838 // Build command buffer
AtomX 0:1d9c7c0b5015 839 buffer[0] = PICC_CMD_MF_READ;
AtomX 0:1d9c7c0b5015 840 buffer[1] = blockAddr;
AtomX 0:1d9c7c0b5015 841 // Calculate CRC_A
AtomX 0:1d9c7c0b5015 842 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
AtomX 0:1d9c7c0b5015 843 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 844 {
AtomX 0:1d9c7c0b5015 845 return result;
AtomX 0:1d9c7c0b5015 846 }
AtomX 0:1d9c7c0b5015 847
AtomX 0:1d9c7c0b5015 848 // Transmit the buffer and receive the response, validate CRC_A.
AtomX 0:1d9c7c0b5015 849 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
AtomX 0:1d9c7c0b5015 850 } // End MIFARE_Read()
AtomX 0:1d9c7c0b5015 851
AtomX 0:1d9c7c0b5015 852 /**
AtomX 0:1d9c7c0b5015 853 * Writes 16 bytes to the active PICC.
AtomX 0:1d9c7c0b5015 854 *
AtomX 0:1d9c7c0b5015 855 * For MIFARE Classic the sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 856 *
AtomX 0:1d9c7c0b5015 857 * For MIFARE Ultralight the opretaion is called "COMPATIBILITY WRITE".
AtomX 0:1d9c7c0b5015 858 * Even though 16 bytes are transferred to the Ultralight PICC, only the least significant 4 bytes (bytes 0 to 3)
AtomX 0:1d9c7c0b5015 859 * are written to the specified address. It is recommended to set the remaining bytes 04h to 0Fh to all logic 0.
AtomX 0:1d9c7c0b5015 860 * *
AtomX 0:1d9c7c0b5015 861 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 862 */
AtomX 0:1d9c7c0b5015 863 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
AtomX 0:1d9c7c0b5015 864 {
AtomX 0:1d9c7c0b5015 865 uint8_t result;
AtomX 0:1d9c7c0b5015 866
AtomX 0:1d9c7c0b5015 867 // Sanity check
AtomX 0:1d9c7c0b5015 868 if (buffer == NULL || bufferSize < 16)
AtomX 0:1d9c7c0b5015 869 {
AtomX 0:1d9c7c0b5015 870 return STATUS_INVALID;
AtomX 0:1d9c7c0b5015 871 }
AtomX 0:1d9c7c0b5015 872
AtomX 0:1d9c7c0b5015 873 // Mifare Classic protocol requires two communications to perform a write.
AtomX 0:1d9c7c0b5015 874 // Step 1: Tell the PICC we want to write to block blockAddr.
AtomX 0:1d9c7c0b5015 875 uint8_t cmdBuffer[2];
AtomX 0:1d9c7c0b5015 876 cmdBuffer[0] = PICC_CMD_MF_WRITE;
AtomX 0:1d9c7c0b5015 877 cmdBuffer[1] = blockAddr;
AtomX 0:1d9c7c0b5015 878 result = PCD_MIFARE_Transceive(cmdBuffer, 2); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:1d9c7c0b5015 879 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 880 {
AtomX 0:1d9c7c0b5015 881 return result;
AtomX 0:1d9c7c0b5015 882 }
AtomX 0:1d9c7c0b5015 883
AtomX 0:1d9c7c0b5015 884 // Step 2: Transfer the data
AtomX 0:1d9c7c0b5015 885 result = PCD_MIFARE_Transceive( buffer, bufferSize); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:1d9c7c0b5015 886 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 887 {
AtomX 0:1d9c7c0b5015 888 return result;
AtomX 0:1d9c7c0b5015 889 }
AtomX 0:1d9c7c0b5015 890
AtomX 0:1d9c7c0b5015 891 return STATUS_OK;
AtomX 0:1d9c7c0b5015 892 } // End MIFARE_Write()
AtomX 0:1d9c7c0b5015 893
AtomX 0:1d9c7c0b5015 894 /**
AtomX 0:1d9c7c0b5015 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
AtomX 0:1d9c7c0b5015 896 *
AtomX 0:1d9c7c0b5015 897 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 898 */
AtomX 0:1d9c7c0b5015 899 uint8_t MFRC522::MIFARE_Ultralight_Write(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
AtomX 0:1d9c7c0b5015 900 {
AtomX 0:1d9c7c0b5015 901 uint8_t result;
AtomX 0:1d9c7c0b5015 902
AtomX 0:1d9c7c0b5015 903 // Sanity check
AtomX 0:1d9c7c0b5015 904 if (buffer == NULL || bufferSize < 4)
AtomX 0:1d9c7c0b5015 905 {
AtomX 0:1d9c7c0b5015 906 return STATUS_INVALID;
AtomX 0:1d9c7c0b5015 907 }
AtomX 0:1d9c7c0b5015 908
AtomX 0:1d9c7c0b5015 909 // Build commmand buffer
AtomX 0:1d9c7c0b5015 910 uint8_t cmdBuffer[6];
AtomX 0:1d9c7c0b5015 911 cmdBuffer[0] = PICC_CMD_UL_WRITE;
AtomX 0:1d9c7c0b5015 912 cmdBuffer[1] = page;
AtomX 0:1d9c7c0b5015 913 memcpy(&cmdBuffer[2], buffer, 4);
AtomX 0:1d9c7c0b5015 914
AtomX 0:1d9c7c0b5015 915 // Perform the write
AtomX 0:1d9c7c0b5015 916 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:1d9c7c0b5015 917 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 918 {
AtomX 0:1d9c7c0b5015 919 return result;
AtomX 0:1d9c7c0b5015 920 }
AtomX 0:1d9c7c0b5015 921 return STATUS_OK;
AtomX 0:1d9c7c0b5015 922 } // End MIFARE_Ultralight_Write()
AtomX 0:1d9c7c0b5015 923
AtomX 0:1d9c7c0b5015 924 /**
AtomX 0:1d9c7c0b5015 925 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
AtomX 0:1d9c7c0b5015 926 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 927 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:1d9c7c0b5015 928 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:1d9c7c0b5015 929 *
AtomX 0:1d9c7c0b5015 930 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 931 */
AtomX 0:1d9c7c0b5015 932 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
AtomX 0:1d9c7c0b5015 933 {
AtomX 0:1d9c7c0b5015 934 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
AtomX 0:1d9c7c0b5015 935 } // End MIFARE_Decrement()
AtomX 0:1d9c7c0b5015 936
AtomX 0:1d9c7c0b5015 937 /**
AtomX 0:1d9c7c0b5015 938 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
AtomX 0:1d9c7c0b5015 939 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 940 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:1d9c7c0b5015 941 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:1d9c7c0b5015 942 *
AtomX 0:1d9c7c0b5015 943 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 944 */
AtomX 0:1d9c7c0b5015 945 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
AtomX 0:1d9c7c0b5015 946 {
AtomX 0:1d9c7c0b5015 947 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
AtomX 0:1d9c7c0b5015 948 } // End MIFARE_Increment()
AtomX 0:1d9c7c0b5015 949
AtomX 0:1d9c7c0b5015 950 /**
AtomX 0:1d9c7c0b5015 951 * MIFARE Restore copies the value of the addressed block into a volatile memory.
AtomX 0:1d9c7c0b5015 952 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 953 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:1d9c7c0b5015 954 * Use MIFARE_Transfer() to store the result in a block.
AtomX 0:1d9c7c0b5015 955 *
AtomX 0:1d9c7c0b5015 956 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 957 */
AtomX 0:1d9c7c0b5015 958 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
AtomX 0:1d9c7c0b5015 959 {
AtomX 0:1d9c7c0b5015 960 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
AtomX 0:1d9c7c0b5015 961 // Doing only a single step does not work, so I chose to transfer 0L in step two.
AtomX 0:1d9c7c0b5015 962 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
AtomX 0:1d9c7c0b5015 963 } // End MIFARE_Restore()
AtomX 0:1d9c7c0b5015 964
AtomX 0:1d9c7c0b5015 965 /**
AtomX 0:1d9c7c0b5015 966 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
AtomX 0:1d9c7c0b5015 967 *
AtomX 0:1d9c7c0b5015 968 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 969 */
AtomX 0:1d9c7c0b5015 970 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
AtomX 0:1d9c7c0b5015 971 {
AtomX 0:1d9c7c0b5015 972 uint8_t result;
AtomX 0:1d9c7c0b5015 973 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
AtomX 0:1d9c7c0b5015 974
AtomX 0:1d9c7c0b5015 975 // Step 1: Tell the PICC the command and block address
AtomX 0:1d9c7c0b5015 976 cmdBuffer[0] = command;
AtomX 0:1d9c7c0b5015 977 cmdBuffer[1] = blockAddr;
AtomX 0:1d9c7c0b5015 978 result = PCD_MIFARE_Transceive( cmdBuffer, 2); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:1d9c7c0b5015 979 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 980 {
AtomX 0:1d9c7c0b5015 981 return result;
AtomX 0:1d9c7c0b5015 982 }
AtomX 0:1d9c7c0b5015 983
AtomX 0:1d9c7c0b5015 984 // Step 2: Transfer the data
AtomX 0:1d9c7c0b5015 985 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true); // Adds CRC_A and accept timeout as success.
AtomX 0:1d9c7c0b5015 986 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 987 {
AtomX 0:1d9c7c0b5015 988 return result;
AtomX 0:1d9c7c0b5015 989 }
AtomX 0:1d9c7c0b5015 990
AtomX 0:1d9c7c0b5015 991 return STATUS_OK;
AtomX 0:1d9c7c0b5015 992 } // End MIFARE_TwoStepHelper()
AtomX 0:1d9c7c0b5015 993
AtomX 0:1d9c7c0b5015 994 /**
AtomX 0:1d9c7c0b5015 995 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
AtomX 0:1d9c7c0b5015 996 * For MIFARE Classic only. The sector containing the block must be authenticated before calling this function.
AtomX 0:1d9c7c0b5015 997 * Only for blocks in "value block" mode, ie with access bits [C1 C2 C3] = [110] or [001].
AtomX 0:1d9c7c0b5015 998 *
AtomX 0:1d9c7c0b5015 999 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 1000 */
AtomX 0:1d9c7c0b5015 1001 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
AtomX 0:1d9c7c0b5015 1002 {
AtomX 0:1d9c7c0b5015 1003 uint8_t result;
AtomX 0:1d9c7c0b5015 1004 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
AtomX 0:1d9c7c0b5015 1005
AtomX 0:1d9c7c0b5015 1006 // Tell the PICC we want to transfer the result into block blockAddr.
AtomX 0:1d9c7c0b5015 1007 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
AtomX 0:1d9c7c0b5015 1008 cmdBuffer[1] = blockAddr;
AtomX 0:1d9c7c0b5015 1009 result = PCD_MIFARE_Transceive( cmdBuffer, 2); // Adds CRC_A and checks that the response is MF_ACK.
AtomX 0:1d9c7c0b5015 1010 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 1011 {
AtomX 0:1d9c7c0b5015 1012 return result;
AtomX 0:1d9c7c0b5015 1013 }
AtomX 0:1d9c7c0b5015 1014 return STATUS_OK;
AtomX 0:1d9c7c0b5015 1015 } // End MIFARE_Transfer()
AtomX 0:1d9c7c0b5015 1016
AtomX 0:1d9c7c0b5015 1017
AtomX 0:1d9c7c0b5015 1018 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 1019 // Support functions
AtomX 0:1d9c7c0b5015 1020 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 1021
AtomX 0:1d9c7c0b5015 1022 /**
AtomX 0:1d9c7c0b5015 1023 * Wrapper for MIFARE protocol communication.
AtomX 0:1d9c7c0b5015 1024 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
AtomX 0:1d9c7c0b5015 1025 *
AtomX 0:1d9c7c0b5015 1026 * @return STATUS_OK on success, STATUS_??? otherwise.
AtomX 0:1d9c7c0b5015 1027 */
AtomX 0:1d9c7c0b5015 1028 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
AtomX 0:1d9c7c0b5015 1029 {
AtomX 0:1d9c7c0b5015 1030 uint8_t result;
AtomX 0:1d9c7c0b5015 1031 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
AtomX 0:1d9c7c0b5015 1032
AtomX 0:1d9c7c0b5015 1033 // Sanity check
AtomX 0:1d9c7c0b5015 1034 if (sendData == NULL || sendLen > 16)
AtomX 0:1d9c7c0b5015 1035 {
AtomX 0:1d9c7c0b5015 1036 return STATUS_INVALID;
AtomX 0:1d9c7c0b5015 1037 }
AtomX 0:1d9c7c0b5015 1038
AtomX 0:1d9c7c0b5015 1039 // Copy sendData[] to cmdBuffer[] and add CRC_A
AtomX 0:1d9c7c0b5015 1040 memcpy(cmdBuffer, sendData, sendLen);
AtomX 0:1d9c7c0b5015 1041 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
AtomX 0:1d9c7c0b5015 1042 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 1043 {
AtomX 0:1d9c7c0b5015 1044 return result;
AtomX 0:1d9c7c0b5015 1045 }
AtomX 0:1d9c7c0b5015 1046 sendLen += 2;
AtomX 0:1d9c7c0b5015 1047
AtomX 0:1d9c7c0b5015 1048 // Transceive the data, store the reply in cmdBuffer[]
AtomX 0:1d9c7c0b5015 1049 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
AtomX 0:1d9c7c0b5015 1050 uint8_t cmdBufferSize = sizeof(cmdBuffer);
AtomX 0:1d9c7c0b5015 1051 uint8_t validBits = 0;
AtomX 0:1d9c7c0b5015 1052 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
AtomX 0:1d9c7c0b5015 1053 if (acceptTimeout && result == STATUS_TIMEOUT)
AtomX 0:1d9c7c0b5015 1054 {
AtomX 0:1d9c7c0b5015 1055 return STATUS_OK;
AtomX 0:1d9c7c0b5015 1056 }
AtomX 0:1d9c7c0b5015 1057
AtomX 0:1d9c7c0b5015 1058 if (result != STATUS_OK)
AtomX 0:1d9c7c0b5015 1059 {
AtomX 0:1d9c7c0b5015 1060 return result;
AtomX 0:1d9c7c0b5015 1061 }
AtomX 0:1d9c7c0b5015 1062
AtomX 0:1d9c7c0b5015 1063 // The PICC must reply with a 4 bit ACK
AtomX 0:1d9c7c0b5015 1064 if (cmdBufferSize != 1 || validBits != 4)
AtomX 0:1d9c7c0b5015 1065 {
AtomX 0:1d9c7c0b5015 1066 return STATUS_ERROR;
AtomX 0:1d9c7c0b5015 1067 }
AtomX 0:1d9c7c0b5015 1068
AtomX 0:1d9c7c0b5015 1069 if (cmdBuffer[0] != MF_ACK)
AtomX 0:1d9c7c0b5015 1070 {
AtomX 0:1d9c7c0b5015 1071 return STATUS_MIFARE_NACK;
AtomX 0:1d9c7c0b5015 1072 }
AtomX 0:1d9c7c0b5015 1073
AtomX 0:1d9c7c0b5015 1074 return STATUS_OK;
AtomX 0:1d9c7c0b5015 1075 } // End PCD_MIFARE_Transceive()
AtomX 0:1d9c7c0b5015 1076
AtomX 0:1d9c7c0b5015 1077
AtomX 0:1d9c7c0b5015 1078 /**
AtomX 0:1d9c7c0b5015 1079 * Translates the SAK (Select Acknowledge) to a PICC type.
AtomX 0:1d9c7c0b5015 1080 *
AtomX 0:1d9c7c0b5015 1081 * @return PICC_Type
AtomX 0:1d9c7c0b5015 1082 */
AtomX 0:1d9c7c0b5015 1083 uint8_t MFRC522::PICC_GetType(uint8_t sak)
AtomX 0:1d9c7c0b5015 1084 {
AtomX 0:1d9c7c0b5015 1085 uint8_t retType = PICC_TYPE_UNKNOWN;
AtomX 0:1d9c7c0b5015 1086
AtomX 0:1d9c7c0b5015 1087 if (sak & 0x04) // UID not complete
AtomX 0:1d9c7c0b5015 1088 {
AtomX 0:1d9c7c0b5015 1089 retType = PICC_TYPE_NOT_COMPLETE;
AtomX 0:1d9c7c0b5015 1090 }
AtomX 0:1d9c7c0b5015 1091 else
AtomX 0:1d9c7c0b5015 1092 {
AtomX 0:1d9c7c0b5015 1093 switch (sak)
AtomX 0:1d9c7c0b5015 1094 {
AtomX 0:1d9c7c0b5015 1095 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
AtomX 0:1d9c7c0b5015 1096 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
AtomX 0:1d9c7c0b5015 1097 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
AtomX 0:1d9c7c0b5015 1098 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
AtomX 0:1d9c7c0b5015 1099 case 0x10:
AtomX 0:1d9c7c0b5015 1100 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
AtomX 0:1d9c7c0b5015 1101 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
AtomX 0:1d9c7c0b5015 1102 default:
AtomX 0:1d9c7c0b5015 1103 if (sak & 0x20)
AtomX 0:1d9c7c0b5015 1104 {
AtomX 0:1d9c7c0b5015 1105 retType = PICC_TYPE_ISO_14443_4;
AtomX 0:1d9c7c0b5015 1106 }
AtomX 0:1d9c7c0b5015 1107 else if (sak & 0x40)
AtomX 0:1d9c7c0b5015 1108 {
AtomX 0:1d9c7c0b5015 1109 retType = PICC_TYPE_ISO_18092;
AtomX 0:1d9c7c0b5015 1110 }
AtomX 0:1d9c7c0b5015 1111 break;
AtomX 0:1d9c7c0b5015 1112 }
AtomX 0:1d9c7c0b5015 1113 }
AtomX 0:1d9c7c0b5015 1114
AtomX 0:1d9c7c0b5015 1115 return (retType);
AtomX 0:1d9c7c0b5015 1116 } // End PICC_GetType()
AtomX 0:1d9c7c0b5015 1117
AtomX 0:1d9c7c0b5015 1118 /**
AtomX 0:1d9c7c0b5015 1119 * Returns a string pointer to the PICC type name.
AtomX 0:1d9c7c0b5015 1120 *
AtomX 0:1d9c7c0b5015 1121 */
AtomX 0:1d9c7c0b5015 1122 std::string MFRC522::PICC_GetTypeName(uint8_t piccType)
AtomX 0:1d9c7c0b5015 1123 {
AtomX 0:1d9c7c0b5015 1124 if(piccType == PICC_TYPE_NOT_COMPLETE)
AtomX 0:1d9c7c0b5015 1125 {
AtomX 0:1d9c7c0b5015 1126 return ("SAK indicates UID is not complete.");
AtomX 0:1d9c7c0b5015 1127 }
AtomX 0:1d9c7c0b5015 1128
AtomX 0:1d9c7c0b5015 1129 return(_TypeNamePICC[piccType]);
AtomX 0:1d9c7c0b5015 1130 } // End PICC_GetTypeName()
AtomX 0:1d9c7c0b5015 1131
AtomX 0:1d9c7c0b5015 1132 /**
AtomX 0:1d9c7c0b5015 1133 * Returns a string pointer to a status code name.
AtomX 0:1d9c7c0b5015 1134 *
AtomX 0:1d9c7c0b5015 1135 */
AtomX 0:1d9c7c0b5015 1136 std::string MFRC522::GetStatusCodeName(uint8_t code)
AtomX 0:1d9c7c0b5015 1137 {
AtomX 0:1d9c7c0b5015 1138 return(_ErrorMessage[code]);
AtomX 0:1d9c7c0b5015 1139 } // End GetStatusCodeName()
AtomX 0:1d9c7c0b5015 1140
AtomX 0:1d9c7c0b5015 1141 /**
AtomX 0:1d9c7c0b5015 1142 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
AtomX 0:1d9c7c0b5015 1143 */
AtomX 0:1d9c7c0b5015 1144 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer, ///< Pointer to byte 6, 7 and 8 in the sector trailer. Bytes [0..2] will be set.
AtomX 0:1d9c7c0b5015 1145 uint8_t g0, ///< Access bits [C1 C2 C3] for block 0 (for sectors 0-31) or blocks 0-4 (for sectors 32-39)
AtomX 0:1d9c7c0b5015 1146 uint8_t g1, ///< Access bits C1 C2 C3] for block 1 (for sectors 0-31) or blocks 5-9 (for sectors 32-39)
AtomX 0:1d9c7c0b5015 1147 uint8_t g2, ///< Access bits C1 C2 C3] for block 2 (for sectors 0-31) or blocks 10-14 (for sectors 32-39)
AtomX 0:1d9c7c0b5015 1148 uint8_t g3) ///< Access bits C1 C2 C3] for the sector trailer, block 3 (for sectors 0-31) or block 15 (for sectors 32-39)
AtomX 0:1d9c7c0b5015 1149 {
AtomX 0:1d9c7c0b5015 1150 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
AtomX 0:1d9c7c0b5015 1151 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
AtomX 0:1d9c7c0b5015 1152 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
AtomX 0:1d9c7c0b5015 1153
AtomX 0:1d9c7c0b5015 1154 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
AtomX 0:1d9c7c0b5015 1155 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
AtomX 0:1d9c7c0b5015 1156 accessBitBuffer[2] = c3 << 4 | c2;
AtomX 0:1d9c7c0b5015 1157 } // End MIFARE_SetAccessBits()
AtomX 0:1d9c7c0b5015 1158
AtomX 0:1d9c7c0b5015 1159 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 1160 // Convenience functions - does not add extra functionality
AtomX 0:1d9c7c0b5015 1161 /////////////////////////////////////////////////////////////////////////////////////
AtomX 0:1d9c7c0b5015 1162
AtomX 0:1d9c7c0b5015 1163 /**
AtomX 0:1d9c7c0b5015 1164 * Returns true if a PICC responds to PICC_CMD_REQA.
AtomX 0:1d9c7c0b5015 1165 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
AtomX 0:1d9c7c0b5015 1166 *
AtomX 0:1d9c7c0b5015 1167 * @return bool
AtomX 0:1d9c7c0b5015 1168 */
AtomX 0:1d9c7c0b5015 1169 bool MFRC522::PICC_IsNewCardPresent()
AtomX 0:1d9c7c0b5015 1170 {
AtomX 0:1d9c7c0b5015 1171 uint8_t bufferATQA[2];
AtomX 0:1d9c7c0b5015 1172 uint8_t bufferSize = sizeof(bufferATQA);
AtomX 0:1d9c7c0b5015 1173 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
AtomX 0:1d9c7c0b5015 1174 return (result == STATUS_OK || result == STATUS_COLLISION);
AtomX 0:1d9c7c0b5015 1175 } // End PICC_IsNewCardPresent()
AtomX 0:1d9c7c0b5015 1176
AtomX 0:1d9c7c0b5015 1177 /**
AtomX 0:1d9c7c0b5015 1178 * Simple wrapper around PICC_Select.
AtomX 0:1d9c7c0b5015 1179 * Returns true if a UID could be read.
AtomX 0:1d9c7c0b5015 1180 * Remember to call PICC_IsNewCardPresent(), PICC_RequestA() or PICC_WakeupA() first.
AtomX 0:1d9c7c0b5015 1181 * The read UID is available in the class variable uid.
AtomX 0:1d9c7c0b5015 1182 *
AtomX 0:1d9c7c0b5015 1183 * @return bool
AtomX 0:1d9c7c0b5015 1184 */
AtomX 0:1d9c7c0b5015 1185 bool MFRC522::PICC_ReadCardSerial()
AtomX 0:1d9c7c0b5015 1186 {
AtomX 0:1d9c7c0b5015 1187 uint8_t result = PICC_Select(&uid);
AtomX 0:1d9c7c0b5015 1188 return (result == STATUS_OK);
AtomX 0:1d9c7c0b5015 1189 } // End PICC_ReadCardSerial()