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source/nordic_sdk/components/device/nrf51.h@9:118fd63123a5, 2017-01-13 (annotated)

Committer:: Asimov
Date:: Fri Jan 13 20:59:21 2017 +0000
Revision:: 9:118fd63123a5
Parent:: 0:bc2961fa1ef0

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User	Revision	Line number	New contents of line
Jonathan Austin	0:bc2961fa1ef0	1	/*
Jonathan Austin	0:bc2961fa1ef0	2	* Copyright (c) Nordic Semiconductor ASA
Jonathan Austin	0:bc2961fa1ef0	3	* All rights reserved.
Jonathan Austin	0:bc2961fa1ef0	4	*
Jonathan Austin	0:bc2961fa1ef0	5	* Redistribution and use in source and binary forms, with or without modification,
Jonathan Austin	0:bc2961fa1ef0	6	* are permitted provided that the following conditions are met:
Jonathan Austin	0:bc2961fa1ef0	7	*
Jonathan Austin	0:bc2961fa1ef0	8	* 1. Redistributions of source code must retain the above copyright notice, this
Jonathan Austin	0:bc2961fa1ef0	9	* list of conditions and the following disclaimer.
Jonathan Austin	0:bc2961fa1ef0	10	*
Jonathan Austin	0:bc2961fa1ef0	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
Jonathan Austin	0:bc2961fa1ef0	12	* list of conditions and the following disclaimer in the documentation and/or
Jonathan Austin	0:bc2961fa1ef0	13	* other materials provided with the distribution.
Jonathan Austin	0:bc2961fa1ef0	14	*
Jonathan Austin	0:bc2961fa1ef0	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Jonathan Austin	0:bc2961fa1ef0	16	* contributors to this software may be used to endorse or promote products
Jonathan Austin	0:bc2961fa1ef0	17	* derived from this software without specific prior written permission.
Jonathan Austin	0:bc2961fa1ef0	18	*
Jonathan Austin	0:bc2961fa1ef0	19	*
Jonathan Austin	0:bc2961fa1ef0	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Jonathan Austin	0:bc2961fa1ef0	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Jonathan Austin	0:bc2961fa1ef0	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Jonathan Austin	0:bc2961fa1ef0	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Jonathan Austin	0:bc2961fa1ef0	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Jonathan Austin	0:bc2961fa1ef0	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Jonathan Austin	0:bc2961fa1ef0	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Jonathan Austin	0:bc2961fa1ef0	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Jonathan Austin	0:bc2961fa1ef0	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Jonathan Austin	0:bc2961fa1ef0	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Jonathan Austin	0:bc2961fa1ef0	30	*
Jonathan Austin	0:bc2961fa1ef0	31	*/
Jonathan Austin	0:bc2961fa1ef0	32
Jonathan Austin	0:bc2961fa1ef0	33	#ifndef NRF51_H
Jonathan Austin	0:bc2961fa1ef0	34	#define NRF51_H
Jonathan Austin	0:bc2961fa1ef0	35
Jonathan Austin	0:bc2961fa1ef0	36	#ifdef __cplusplus
Jonathan Austin	0:bc2961fa1ef0	37	extern "C" {
Jonathan Austin	0:bc2961fa1ef0	38	#endif
Jonathan Austin	0:bc2961fa1ef0	39
Jonathan Austin	0:bc2961fa1ef0	40
Jonathan Austin	0:bc2961fa1ef0	41	/* ------------------------- Interrupt Number Definition ------------------------ */
Jonathan Austin	0:bc2961fa1ef0	42
Jonathan Austin	0:bc2961fa1ef0	43	typedef enum {
Jonathan Austin	0:bc2961fa1ef0	44	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Jonathan Austin	0:bc2961fa1ef0	45	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
Jonathan Austin	0:bc2961fa1ef0	46	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
Jonathan Austin	0:bc2961fa1ef0	47	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
Jonathan Austin	0:bc2961fa1ef0	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
Jonathan Austin	0:bc2961fa1ef0	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
Jonathan Austin	0:bc2961fa1ef0	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
Jonathan Austin	0:bc2961fa1ef0	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
Jonathan Austin	0:bc2961fa1ef0	52	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
Jonathan Austin	0:bc2961fa1ef0	53	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
Jonathan Austin	0:bc2961fa1ef0	54	RADIO_IRQn = 1, /!< 1 RADIO /
Jonathan Austin	0:bc2961fa1ef0	55	UART0_IRQn = 2, /!< 2 UART0 /
Jonathan Austin	0:bc2961fa1ef0	56	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
Jonathan Austin	0:bc2961fa1ef0	57	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
Jonathan Austin	0:bc2961fa1ef0	58	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
Jonathan Austin	0:bc2961fa1ef0	59	ADC_IRQn = 7, /!< 7 ADC /
Jonathan Austin	0:bc2961fa1ef0	60	TIMER0_IRQn = 8, /!< 8 TIMER0 /
Jonathan Austin	0:bc2961fa1ef0	61	TIMER1_IRQn = 9, /!< 9 TIMER1 /
Jonathan Austin	0:bc2961fa1ef0	62	TIMER2_IRQn = 10, /!< 10 TIMER2 /
Jonathan Austin	0:bc2961fa1ef0	63	RTC0_IRQn = 11, /!< 11 RTC0 /
Jonathan Austin	0:bc2961fa1ef0	64	TEMP_IRQn = 12, /!< 12 TEMP /
Jonathan Austin	0:bc2961fa1ef0	65	RNG_IRQn = 13, /!< 13 RNG /
Jonathan Austin	0:bc2961fa1ef0	66	ECB_IRQn = 14, /!< 14 ECB /
Jonathan Austin	0:bc2961fa1ef0	67	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
Jonathan Austin	0:bc2961fa1ef0	68	WDT_IRQn = 16, /!< 16 WDT /
Jonathan Austin	0:bc2961fa1ef0	69	RTC1_IRQn = 17, /!< 17 RTC1 /
Jonathan Austin	0:bc2961fa1ef0	70	QDEC_IRQn = 18, /!< 18 QDEC /
Jonathan Austin	0:bc2961fa1ef0	71	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
Jonathan Austin	0:bc2961fa1ef0	72	SWI0_IRQn = 20, /!< 20 SWI0 /
Jonathan Austin	0:bc2961fa1ef0	73	SWI1_IRQn = 21, /!< 21 SWI1 /
Jonathan Austin	0:bc2961fa1ef0	74	SWI2_IRQn = 22, /!< 22 SWI2 /
Jonathan Austin	0:bc2961fa1ef0	75	SWI3_IRQn = 23, /!< 23 SWI3 /
Jonathan Austin	0:bc2961fa1ef0	76	SWI4_IRQn = 24, /!< 24 SWI4 /
Jonathan Austin	0:bc2961fa1ef0	77	SWI5_IRQn = 25 /!< 25 SWI5 /
Jonathan Austin	0:bc2961fa1ef0	78	} IRQn_Type;
Jonathan Austin	0:bc2961fa1ef0	79
Jonathan Austin	0:bc2961fa1ef0	80
Jonathan Austin	0:bc2961fa1ef0	81	/** @addtogroup Configuration_of_CMSIS
Jonathan Austin	0:bc2961fa1ef0	82	* @{
Jonathan Austin	0:bc2961fa1ef0	83	*/
Jonathan Austin	0:bc2961fa1ef0	84
Jonathan Austin	0:bc2961fa1ef0	85
Jonathan Austin	0:bc2961fa1ef0	86	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	87	/* ================ Processor and Core Peripheral Section ================ */
Jonathan Austin	0:bc2961fa1ef0	88	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	89
Jonathan Austin	0:bc2961fa1ef0	90	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
Jonathan Austin	0:bc2961fa1ef0	91	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
Jonathan Austin	0:bc2961fa1ef0	92	#define __MPU_PRESENT 0 /!< MPU present or not /
Jonathan Austin	0:bc2961fa1ef0	93	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
Jonathan Austin	0:bc2961fa1ef0	94	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Jonathan Austin	0:bc2961fa1ef0	95	/** @} / / End of group Configuration_of_CMSIS */
Jonathan Austin	0:bc2961fa1ef0	96
Jonathan Austin	0:bc2961fa1ef0	97	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
Jonathan Austin	0:bc2961fa1ef0	98	#include "system_nrf51.h" /!< nrf51 System /
Jonathan Austin	0:bc2961fa1ef0	99
Jonathan Austin	0:bc2961fa1ef0	100
Jonathan Austin	0:bc2961fa1ef0	101	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	102	/* ================ Device Specific Peripheral Section ================ */
Jonathan Austin	0:bc2961fa1ef0	103	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	104
Jonathan Austin	0:bc2961fa1ef0	105
Jonathan Austin	0:bc2961fa1ef0	106	/** @addtogroup Device_Peripheral_Registers
Jonathan Austin	0:bc2961fa1ef0	107	* @{
Jonathan Austin	0:bc2961fa1ef0	108	*/
Jonathan Austin	0:bc2961fa1ef0	109
Jonathan Austin	0:bc2961fa1ef0	110
Jonathan Austin	0:bc2961fa1ef0	111	/* ------------------- Start of section using anonymous unions ------------------ */
Jonathan Austin	0:bc2961fa1ef0	112	#if defined(__CC_ARM)
Jonathan Austin	0:bc2961fa1ef0	113	#pragma push
Jonathan Austin	0:bc2961fa1ef0	114	#pragma anon_unions
Jonathan Austin	0:bc2961fa1ef0	115	#elif defined(__ICCARM__)
Jonathan Austin	0:bc2961fa1ef0	116	#pragma language=extended
Jonathan Austin	0:bc2961fa1ef0	117	#elif defined(__GNUC__)
Jonathan Austin	0:bc2961fa1ef0	118	/* anonymous unions are enabled by default */
Jonathan Austin	0:bc2961fa1ef0	119	#elif defined(__TMS470__)
Jonathan Austin	0:bc2961fa1ef0	120	/* anonymous unions are enabled by default */
Jonathan Austin	0:bc2961fa1ef0	121	#elif defined(__TASKING__)
Jonathan Austin	0:bc2961fa1ef0	122	#pragma warning 586
Jonathan Austin	0:bc2961fa1ef0	123	#else
Jonathan Austin	0:bc2961fa1ef0	124	#warning Not supported compiler type
Jonathan Austin	0:bc2961fa1ef0	125	#endif
Jonathan Austin	0:bc2961fa1ef0	126
Jonathan Austin	0:bc2961fa1ef0	127
Jonathan Austin	0:bc2961fa1ef0	128	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	129	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
Jonathan Austin	0:bc2961fa1ef0	130	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
Jonathan Austin	0:bc2961fa1ef0	131	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
Jonathan Austin	0:bc2961fa1ef0	132	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
Jonathan Austin	0:bc2961fa1ef0	133	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
Jonathan Austin	0:bc2961fa1ef0	134	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
Jonathan Austin	0:bc2961fa1ef0	135	} AMLI_RAMPRI_Type;
Jonathan Austin	0:bc2961fa1ef0	136
Jonathan Austin	0:bc2961fa1ef0	137	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	138	__IO uint32_t SCK; /!< Pin select for SCK. /
Jonathan Austin	0:bc2961fa1ef0	139	__IO uint32_t MOSI; /!< Pin select for MOSI. /
Jonathan Austin	0:bc2961fa1ef0	140	__IO uint32_t MISO; /!< Pin select for MISO. /
Jonathan Austin	0:bc2961fa1ef0	141	} SPIM_PSEL_Type;
Jonathan Austin	0:bc2961fa1ef0	142
Jonathan Austin	0:bc2961fa1ef0	143	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	144	__IO uint32_t PTR; /!< Data pointer. /
Jonathan Austin	0:bc2961fa1ef0	145	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
Jonathan Austin	0:bc2961fa1ef0	146	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
Jonathan Austin	0:bc2961fa1ef0	147	} SPIM_RXD_Type;
Jonathan Austin	0:bc2961fa1ef0	148
Jonathan Austin	0:bc2961fa1ef0	149	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	150	__IO uint32_t PTR; /!< Data pointer. /
Jonathan Austin	0:bc2961fa1ef0	151	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
Jonathan Austin	0:bc2961fa1ef0	152	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
Jonathan Austin	0:bc2961fa1ef0	153	} SPIM_TXD_Type;
Jonathan Austin	0:bc2961fa1ef0	154
Jonathan Austin	0:bc2961fa1ef0	155	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	156	__O uint32_t EN; /!< Enable channel group. /
Jonathan Austin	0:bc2961fa1ef0	157	__O uint32_t DIS; /!< Disable channel group. /
Jonathan Austin	0:bc2961fa1ef0	158	} PPI_TASKS_CHG_Type;
Jonathan Austin	0:bc2961fa1ef0	159
Jonathan Austin	0:bc2961fa1ef0	160	typedef struct {
Jonathan Austin	0:bc2961fa1ef0	161	__IO uint32_t EEP; /!< Channel event end-point. /
Jonathan Austin	0:bc2961fa1ef0	162	__IO uint32_t TEP; /!< Channel task end-point. /
Jonathan Austin	0:bc2961fa1ef0	163	} PPI_CH_Type;
Jonathan Austin	0:bc2961fa1ef0	164
Jonathan Austin	0:bc2961fa1ef0	165
Jonathan Austin	0:bc2961fa1ef0	166	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	167	/* ================ POWER ================ */
Jonathan Austin	0:bc2961fa1ef0	168	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	169
Jonathan Austin	0:bc2961fa1ef0	170
Jonathan Austin	0:bc2961fa1ef0	171	/**
Jonathan Austin	0:bc2961fa1ef0	172	* @brief Power Control. (POWER)
Jonathan Austin	0:bc2961fa1ef0	173	*/
Jonathan Austin	0:bc2961fa1ef0	174
Jonathan Austin	0:bc2961fa1ef0	175	typedef struct { /!< POWER Structure /
Jonathan Austin	0:bc2961fa1ef0	176	__I uint32_t RESERVED0[30];
Jonathan Austin	0:bc2961fa1ef0	177	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
Jonathan Austin	0:bc2961fa1ef0	178	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
Jonathan Austin	0:bc2961fa1ef0	179	__I uint32_t RESERVED1[34];
Jonathan Austin	0:bc2961fa1ef0	180	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
Jonathan Austin	0:bc2961fa1ef0	181	__I uint32_t RESERVED2[126];
Jonathan Austin	0:bc2961fa1ef0	182	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	183	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	184	__I uint32_t RESERVED3[61];
Jonathan Austin	0:bc2961fa1ef0	185	__IO uint32_t RESETREAS; /!< Reset reason. /
Jonathan Austin	0:bc2961fa1ef0	186	__I uint32_t RESERVED4[9];
Jonathan Austin	0:bc2961fa1ef0	187	__I uint32_t RAMSTATUS; /!< Ram status register. /
Jonathan Austin	0:bc2961fa1ef0	188	__I uint32_t RESERVED5[53];
Jonathan Austin	0:bc2961fa1ef0	189	__O uint32_t SYSTEMOFF; /!< System off register. /
Jonathan Austin	0:bc2961fa1ef0	190	__I uint32_t RESERVED6[3];
Jonathan Austin	0:bc2961fa1ef0	191	__IO uint32_t POFCON; /!< Power failure configuration. /
Jonathan Austin	0:bc2961fa1ef0	192	__I uint32_t RESERVED7[2];
Jonathan Austin	0:bc2961fa1ef0	193	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Jonathan Austin	0:bc2961fa1ef0	194	register. */
Jonathan Austin	0:bc2961fa1ef0	195	__I uint32_t RESERVED8;
Jonathan Austin	0:bc2961fa1ef0	196	__IO uint32_t RAMON; /!< Ram on/off. /
Jonathan Austin	0:bc2961fa1ef0	197	__I uint32_t RESERVED9[7];
Jonathan Austin	0:bc2961fa1ef0	198	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Jonathan Austin	0:bc2961fa1ef0	199	is a retained register. */
Jonathan Austin	0:bc2961fa1ef0	200	__I uint32_t RESERVED10[3];
Jonathan Austin	0:bc2961fa1ef0	201	__IO uint32_t RAMONB; /!< Ram on/off. /
Jonathan Austin	0:bc2961fa1ef0	202	__I uint32_t RESERVED11[8];
Jonathan Austin	0:bc2961fa1ef0	203	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
Jonathan Austin	0:bc2961fa1ef0	204	__I uint32_t RESERVED12[291];
Jonathan Austin	0:bc2961fa1ef0	205	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
Jonathan Austin	0:bc2961fa1ef0	206	} NRF_POWER_Type;
Jonathan Austin	0:bc2961fa1ef0	207
Jonathan Austin	0:bc2961fa1ef0	208
Jonathan Austin	0:bc2961fa1ef0	209	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	210	/* ================ CLOCK ================ */
Jonathan Austin	0:bc2961fa1ef0	211	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	212
Jonathan Austin	0:bc2961fa1ef0	213
Jonathan Austin	0:bc2961fa1ef0	214	/**
Jonathan Austin	0:bc2961fa1ef0	215	* @brief Clock control. (CLOCK)
Jonathan Austin	0:bc2961fa1ef0	216	*/
Jonathan Austin	0:bc2961fa1ef0	217
Jonathan Austin	0:bc2961fa1ef0	218	typedef struct { /!< CLOCK Structure /
Jonathan Austin	0:bc2961fa1ef0	219	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
Jonathan Austin	0:bc2961fa1ef0	220	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
Jonathan Austin	0:bc2961fa1ef0	221	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
Jonathan Austin	0:bc2961fa1ef0	222	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
Jonathan Austin	0:bc2961fa1ef0	223	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
Jonathan Austin	0:bc2961fa1ef0	224	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
Jonathan Austin	0:bc2961fa1ef0	225	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
Jonathan Austin	0:bc2961fa1ef0	226	__I uint32_t RESERVED0[57];
Jonathan Austin	0:bc2961fa1ef0	227	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
Jonathan Austin	0:bc2961fa1ef0	228	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
Jonathan Austin	0:bc2961fa1ef0	229	__I uint32_t RESERVED1;
Jonathan Austin	0:bc2961fa1ef0	230	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
Jonathan Austin	0:bc2961fa1ef0	231	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
Jonathan Austin	0:bc2961fa1ef0	232	__I uint32_t RESERVED2[124];
Jonathan Austin	0:bc2961fa1ef0	233	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	234	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	235	__I uint32_t RESERVED3[63];
Jonathan Austin	0:bc2961fa1ef0	236	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
Jonathan Austin	0:bc2961fa1ef0	237	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
Jonathan Austin	0:bc2961fa1ef0	238	__I uint32_t RESERVED4;
Jonathan Austin	0:bc2961fa1ef0	239	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
Jonathan Austin	0:bc2961fa1ef0	240	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
Jonathan Austin	0:bc2961fa1ef0	241	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Jonathan Austin	0:bc2961fa1ef0	242	triggered. */
Jonathan Austin	0:bc2961fa1ef0	243	__I uint32_t RESERVED5[62];
Jonathan Austin	0:bc2961fa1ef0	244	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
Jonathan Austin	0:bc2961fa1ef0	245	__I uint32_t RESERVED6[7];
Jonathan Austin	0:bc2961fa1ef0	246	__IO uint32_t CTIV; /!< Calibration timer interval. /
Jonathan Austin	0:bc2961fa1ef0	247	__I uint32_t RESERVED7[5];
Jonathan Austin	0:bc2961fa1ef0	248	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
Jonathan Austin	0:bc2961fa1ef0	249	} NRF_CLOCK_Type;
Jonathan Austin	0:bc2961fa1ef0	250
Jonathan Austin	0:bc2961fa1ef0	251
Jonathan Austin	0:bc2961fa1ef0	252	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	253	/* ================ MPU ================ */
Jonathan Austin	0:bc2961fa1ef0	254	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	255
Jonathan Austin	0:bc2961fa1ef0	256
Jonathan Austin	0:bc2961fa1ef0	257	/**
Jonathan Austin	0:bc2961fa1ef0	258	* @brief Memory Protection Unit. (MPU)
Jonathan Austin	0:bc2961fa1ef0	259	*/
Jonathan Austin	0:bc2961fa1ef0	260
Jonathan Austin	0:bc2961fa1ef0	261	typedef struct { /!< MPU Structure /
Jonathan Austin	0:bc2961fa1ef0	262	__I uint32_t RESERVED0[330];
Jonathan Austin	0:bc2961fa1ef0	263	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
Jonathan Austin	0:bc2961fa1ef0	264	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
Jonathan Austin	0:bc2961fa1ef0	265	__I uint32_t RESERVED1[52];
Jonathan Austin	0:bc2961fa1ef0	266	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
Jonathan Austin	0:bc2961fa1ef0	267	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
Jonathan Austin	0:bc2961fa1ef0	268	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
Jonathan Austin	0:bc2961fa1ef0	269	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
Jonathan Austin	0:bc2961fa1ef0	270	} NRF_MPU_Type;
Jonathan Austin	0:bc2961fa1ef0	271
Jonathan Austin	0:bc2961fa1ef0	272
Jonathan Austin	0:bc2961fa1ef0	273	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	274	/* ================ AMLI ================ */
Jonathan Austin	0:bc2961fa1ef0	275	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	276
Jonathan Austin	0:bc2961fa1ef0	277
Jonathan Austin	0:bc2961fa1ef0	278	/**
Jonathan Austin	0:bc2961fa1ef0	279	* @brief AHB Multi-Layer Interface. (AMLI)
Jonathan Austin	0:bc2961fa1ef0	280	*/
Jonathan Austin	0:bc2961fa1ef0	281
Jonathan Austin	0:bc2961fa1ef0	282	typedef struct { /!< AMLI Structure /
Jonathan Austin	0:bc2961fa1ef0	283	__I uint32_t RESERVED0[896];
Jonathan Austin	0:bc2961fa1ef0	284	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
Jonathan Austin	0:bc2961fa1ef0	285	} NRF_AMLI_Type;
Jonathan Austin	0:bc2961fa1ef0	286
Jonathan Austin	0:bc2961fa1ef0	287
Jonathan Austin	0:bc2961fa1ef0	288	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	289	/* ================ RADIO ================ */
Jonathan Austin	0:bc2961fa1ef0	290	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	291
Jonathan Austin	0:bc2961fa1ef0	292
Jonathan Austin	0:bc2961fa1ef0	293	/**
Jonathan Austin	0:bc2961fa1ef0	294	* @brief The radio. (RADIO)
Jonathan Austin	0:bc2961fa1ef0	295	*/
Jonathan Austin	0:bc2961fa1ef0	296
Jonathan Austin	0:bc2961fa1ef0	297	typedef struct { /!< RADIO Structure /
Jonathan Austin	0:bc2961fa1ef0	298	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
Jonathan Austin	0:bc2961fa1ef0	299	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
Jonathan Austin	0:bc2961fa1ef0	300	__O uint32_t TASKS_START; /!< Start radio. /
Jonathan Austin	0:bc2961fa1ef0	301	__O uint32_t TASKS_STOP; /!< Stop radio. /
Jonathan Austin	0:bc2961fa1ef0	302	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
Jonathan Austin	0:bc2961fa1ef0	303	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
Jonathan Austin	0:bc2961fa1ef0	304	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
Jonathan Austin	0:bc2961fa1ef0	305	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
Jonathan Austin	0:bc2961fa1ef0	306	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
Jonathan Austin	0:bc2961fa1ef0	307	__I uint32_t RESERVED0[55];
Jonathan Austin	0:bc2961fa1ef0	308	__IO uint32_t EVENTS_READY; /!< Ready event. /
Jonathan Austin	0:bc2961fa1ef0	309	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
Jonathan Austin	0:bc2961fa1ef0	310	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
Jonathan Austin	0:bc2961fa1ef0	311	__IO uint32_t EVENTS_END; /!< End event. /
Jonathan Austin	0:bc2961fa1ef0	312	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
Jonathan Austin	0:bc2961fa1ef0	313	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
Jonathan Austin	0:bc2961fa1ef0	314	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
Jonathan Austin	0:bc2961fa1ef0	315	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Jonathan Austin	0:bc2961fa1ef0	316	sample is ready for readout at the RSSISAMPLE register. */
Jonathan Austin	0:bc2961fa1ef0	317	__I uint32_t RESERVED1[2];
Jonathan Austin	0:bc2961fa1ef0	318	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
Jonathan Austin	0:bc2961fa1ef0	319	__I uint32_t RESERVED2[53];
Jonathan Austin	0:bc2961fa1ef0	320	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
Jonathan Austin	0:bc2961fa1ef0	321	__I uint32_t RESERVED3[64];
Jonathan Austin	0:bc2961fa1ef0	322	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	323	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	324	__I uint32_t RESERVED4[61];
Jonathan Austin	0:bc2961fa1ef0	325	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
Jonathan Austin	0:bc2961fa1ef0	326	__I uint32_t RESERVED5;
Jonathan Austin	0:bc2961fa1ef0	327	__I uint32_t RXMATCH; /!< Received address. /
Jonathan Austin	0:bc2961fa1ef0	328	__I uint32_t RXCRC; /!< Received CRC. /
Jonathan Austin	0:bc2961fa1ef0	329	__I uint32_t DAI; /!< Device address match index. /
Jonathan Austin	0:bc2961fa1ef0	330	__I uint32_t RESERVED6[60];
Jonathan Austin	0:bc2961fa1ef0	331	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
Jonathan Austin	0:bc2961fa1ef0	332	__IO uint32_t FREQUENCY; /!< Frequency. /
Jonathan Austin	0:bc2961fa1ef0	333	__IO uint32_t TXPOWER; /!< Output power. /
Jonathan Austin	0:bc2961fa1ef0	334	__IO uint32_t MODE; /!< Data rate and modulation. /
Jonathan Austin	0:bc2961fa1ef0	335	__IO uint32_t PCNF0; /!< Packet configuration 0. /
Jonathan Austin	0:bc2961fa1ef0	336	__IO uint32_t PCNF1; /!< Packet configuration 1. /
Jonathan Austin	0:bc2961fa1ef0	337	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
Jonathan Austin	0:bc2961fa1ef0	338	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
Jonathan Austin	0:bc2961fa1ef0	339	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
Jonathan Austin	0:bc2961fa1ef0	340	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
Jonathan Austin	0:bc2961fa1ef0	341	__IO uint32_t TXADDRESS; /!< Transmit address select. /
Jonathan Austin	0:bc2961fa1ef0	342	__IO uint32_t RXADDRESSES; /!< Receive address select. /
Jonathan Austin	0:bc2961fa1ef0	343	__IO uint32_t CRCCNF; /!< CRC configuration. /
Jonathan Austin	0:bc2961fa1ef0	344	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
Jonathan Austin	0:bc2961fa1ef0	345	__IO uint32_t CRCINIT; /!< CRC initial value. /
Jonathan Austin	0:bc2961fa1ef0	346	__IO uint32_t TEST; /!< Test features enable register. /
Jonathan Austin	0:bc2961fa1ef0	347	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
Jonathan Austin	0:bc2961fa1ef0	348	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
Jonathan Austin	0:bc2961fa1ef0	349	__I uint32_t RESERVED7;
Jonathan Austin	0:bc2961fa1ef0	350	__I uint32_t STATE; /!< Current radio state. /
Jonathan Austin	0:bc2961fa1ef0	351	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
Jonathan Austin	0:bc2961fa1ef0	352	__I uint32_t RESERVED8[2];
Jonathan Austin	0:bc2961fa1ef0	353	__IO uint32_t BCC; /!< Bit counter compare. /
Jonathan Austin	0:bc2961fa1ef0	354	__I uint32_t RESERVED9[39];
Jonathan Austin	0:bc2961fa1ef0	355	__IO uint32_t DAB[8]; /!< Device address base segment. /
Jonathan Austin	0:bc2961fa1ef0	356	__IO uint32_t DAP[8]; /!< Device address prefix. /
Jonathan Austin	0:bc2961fa1ef0	357	__IO uint32_t DACNF; /!< Device address match configuration. /
Jonathan Austin	0:bc2961fa1ef0	358	__I uint32_t RESERVED10[56];
Jonathan Austin	0:bc2961fa1ef0	359	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
Jonathan Austin	0:bc2961fa1ef0	360	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
Jonathan Austin	0:bc2961fa1ef0	361	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
Jonathan Austin	0:bc2961fa1ef0	362	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
Jonathan Austin	0:bc2961fa1ef0	363	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
Jonathan Austin	0:bc2961fa1ef0	364	__I uint32_t RESERVED11[561];
Jonathan Austin	0:bc2961fa1ef0	365	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	366	} NRF_RADIO_Type;
Jonathan Austin	0:bc2961fa1ef0	367
Jonathan Austin	0:bc2961fa1ef0	368
Jonathan Austin	0:bc2961fa1ef0	369	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	370	/* ================ UART ================ */
Jonathan Austin	0:bc2961fa1ef0	371	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	372
Jonathan Austin	0:bc2961fa1ef0	373
Jonathan Austin	0:bc2961fa1ef0	374	/**
Jonathan Austin	0:bc2961fa1ef0	375	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
Jonathan Austin	0:bc2961fa1ef0	376	*/
Jonathan Austin	0:bc2961fa1ef0	377
Jonathan Austin	0:bc2961fa1ef0	378	typedef struct { /!< UART Structure /
Jonathan Austin	0:bc2961fa1ef0	379	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
Jonathan Austin	0:bc2961fa1ef0	380	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
Jonathan Austin	0:bc2961fa1ef0	381	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
Jonathan Austin	0:bc2961fa1ef0	382	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
Jonathan Austin	0:bc2961fa1ef0	383	__I uint32_t RESERVED0[3];
Jonathan Austin	0:bc2961fa1ef0	384	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
Jonathan Austin	0:bc2961fa1ef0	385	__I uint32_t RESERVED1[56];
Jonathan Austin	0:bc2961fa1ef0	386	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
Jonathan Austin	0:bc2961fa1ef0	387	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
Jonathan Austin	0:bc2961fa1ef0	388	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
Jonathan Austin	0:bc2961fa1ef0	389	__I uint32_t RESERVED2[4];
Jonathan Austin	0:bc2961fa1ef0	390	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
Jonathan Austin	0:bc2961fa1ef0	391	__I uint32_t RESERVED3;
Jonathan Austin	0:bc2961fa1ef0	392	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
Jonathan Austin	0:bc2961fa1ef0	393	__I uint32_t RESERVED4[7];
Jonathan Austin	0:bc2961fa1ef0	394	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
Jonathan Austin	0:bc2961fa1ef0	395	__I uint32_t RESERVED5[46];
Jonathan Austin	0:bc2961fa1ef0	396	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
Jonathan Austin	0:bc2961fa1ef0	397	__I uint32_t RESERVED6[64];
Jonathan Austin	0:bc2961fa1ef0	398	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	399	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	400	__I uint32_t RESERVED7[93];
Jonathan Austin	0:bc2961fa1ef0	401	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
Jonathan Austin	0:bc2961fa1ef0	402	__I uint32_t RESERVED8[31];
Jonathan Austin	0:bc2961fa1ef0	403	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
Jonathan Austin	0:bc2961fa1ef0	404	__I uint32_t RESERVED9;
Jonathan Austin	0:bc2961fa1ef0	405	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
Jonathan Austin	0:bc2961fa1ef0	406	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
Jonathan Austin	0:bc2961fa1ef0	407	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
Jonathan Austin	0:bc2961fa1ef0	408	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
Jonathan Austin	0:bc2961fa1ef0	409	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Jonathan Austin	0:bc2961fa1ef0	410	Once read the character is consumed. If read when no character
Jonathan Austin	0:bc2961fa1ef0	411	available, the UART will stop working. */
Jonathan Austin	0:bc2961fa1ef0	412	__O uint32_t TXD; /!< TXD register. /
Jonathan Austin	0:bc2961fa1ef0	413	__I uint32_t RESERVED10;
Jonathan Austin	0:bc2961fa1ef0	414	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
Jonathan Austin	0:bc2961fa1ef0	415	__I uint32_t RESERVED11[17];
Jonathan Austin	0:bc2961fa1ef0	416	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
Jonathan Austin	0:bc2961fa1ef0	417	__I uint32_t RESERVED12[675];
Jonathan Austin	0:bc2961fa1ef0	418	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	419	} NRF_UART_Type;
Jonathan Austin	0:bc2961fa1ef0	420
Jonathan Austin	0:bc2961fa1ef0	421
Jonathan Austin	0:bc2961fa1ef0	422	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	423	/* ================ SPI ================ */
Jonathan Austin	0:bc2961fa1ef0	424	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	425
Jonathan Austin	0:bc2961fa1ef0	426
Jonathan Austin	0:bc2961fa1ef0	427	/**
Jonathan Austin	0:bc2961fa1ef0	428	* @brief SPI master 0. (SPI)
Jonathan Austin	0:bc2961fa1ef0	429	*/
Jonathan Austin	0:bc2961fa1ef0	430
Jonathan Austin	0:bc2961fa1ef0	431	typedef struct { /!< SPI Structure /
Jonathan Austin	0:bc2961fa1ef0	432	__I uint32_t RESERVED0[66];
Jonathan Austin	0:bc2961fa1ef0	433	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
Jonathan Austin	0:bc2961fa1ef0	434	__I uint32_t RESERVED1[126];
Jonathan Austin	0:bc2961fa1ef0	435	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	436	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	437	__I uint32_t RESERVED2[125];
Jonathan Austin	0:bc2961fa1ef0	438	__IO uint32_t ENABLE; /!< Enable SPI. /
Jonathan Austin	0:bc2961fa1ef0	439	__I uint32_t RESERVED3;
Jonathan Austin	0:bc2961fa1ef0	440	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
Jonathan Austin	0:bc2961fa1ef0	441	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
Jonathan Austin	0:bc2961fa1ef0	442	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
Jonathan Austin	0:bc2961fa1ef0	443	__I uint32_t RESERVED4;
Jonathan Austin	0:bc2961fa1ef0	444	__I uint32_t RXD; /!< RX data. /
Jonathan Austin	0:bc2961fa1ef0	445	__IO uint32_t TXD; /!< TX data. /
Jonathan Austin	0:bc2961fa1ef0	446	__I uint32_t RESERVED5;
Jonathan Austin	0:bc2961fa1ef0	447	__IO uint32_t FREQUENCY; /!< SPI frequency /
Jonathan Austin	0:bc2961fa1ef0	448	__I uint32_t RESERVED6[11];
Jonathan Austin	0:bc2961fa1ef0	449	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	450	__I uint32_t RESERVED7[681];
Jonathan Austin	0:bc2961fa1ef0	451	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	452	} NRF_SPI_Type;
Jonathan Austin	0:bc2961fa1ef0	453
Jonathan Austin	0:bc2961fa1ef0	454
Jonathan Austin	0:bc2961fa1ef0	455	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	456	/* ================ TWI ================ */
Jonathan Austin	0:bc2961fa1ef0	457	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	458
Jonathan Austin	0:bc2961fa1ef0	459
Jonathan Austin	0:bc2961fa1ef0	460	/**
Jonathan Austin	0:bc2961fa1ef0	461	* @brief Two-wire interface master 0. (TWI)
Jonathan Austin	0:bc2961fa1ef0	462	*/
Jonathan Austin	0:bc2961fa1ef0	463
Jonathan Austin	0:bc2961fa1ef0	464	typedef struct { /!< TWI Structure /
Jonathan Austin	0:bc2961fa1ef0	465	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
Jonathan Austin	0:bc2961fa1ef0	466	__I uint32_t RESERVED0;
Jonathan Austin	0:bc2961fa1ef0	467	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
Jonathan Austin	0:bc2961fa1ef0	468	__I uint32_t RESERVED1[2];
Jonathan Austin	0:bc2961fa1ef0	469	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
Jonathan Austin	0:bc2961fa1ef0	470	__I uint32_t RESERVED2;
Jonathan Austin	0:bc2961fa1ef0	471	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
Jonathan Austin	0:bc2961fa1ef0	472	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
Jonathan Austin	0:bc2961fa1ef0	473	__I uint32_t RESERVED3[56];
Jonathan Austin	0:bc2961fa1ef0	474	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
Jonathan Austin	0:bc2961fa1ef0	475	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
Jonathan Austin	0:bc2961fa1ef0	476	__I uint32_t RESERVED4[4];
Jonathan Austin	0:bc2961fa1ef0	477	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
Jonathan Austin	0:bc2961fa1ef0	478	__I uint32_t RESERVED5;
Jonathan Austin	0:bc2961fa1ef0	479	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
Jonathan Austin	0:bc2961fa1ef0	480	__I uint32_t RESERVED6[4];
Jonathan Austin	0:bc2961fa1ef0	481	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
Jonathan Austin	0:bc2961fa1ef0	482	__I uint32_t RESERVED7[3];
Jonathan Austin	0:bc2961fa1ef0	483	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
Jonathan Austin	0:bc2961fa1ef0	484	__I uint32_t RESERVED8[45];
Jonathan Austin	0:bc2961fa1ef0	485	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
Jonathan Austin	0:bc2961fa1ef0	486	__I uint32_t RESERVED9[64];
Jonathan Austin	0:bc2961fa1ef0	487	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	488	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	489	__I uint32_t RESERVED10[110];
Jonathan Austin	0:bc2961fa1ef0	490	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
Jonathan Austin	0:bc2961fa1ef0	491	__I uint32_t RESERVED11[14];
Jonathan Austin	0:bc2961fa1ef0	492	__IO uint32_t ENABLE; /!< Enable two-wire master. /
Jonathan Austin	0:bc2961fa1ef0	493	__I uint32_t RESERVED12;
Jonathan Austin	0:bc2961fa1ef0	494	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
Jonathan Austin	0:bc2961fa1ef0	495	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
Jonathan Austin	0:bc2961fa1ef0	496	__I uint32_t RESERVED13[2];
Jonathan Austin	0:bc2961fa1ef0	497	__I uint32_t RXD; /!< RX data register. /
Jonathan Austin	0:bc2961fa1ef0	498	__IO uint32_t TXD; /!< TX data register. /
Jonathan Austin	0:bc2961fa1ef0	499	__I uint32_t RESERVED14;
Jonathan Austin	0:bc2961fa1ef0	500	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
Jonathan Austin	0:bc2961fa1ef0	501	__I uint32_t RESERVED15[24];
Jonathan Austin	0:bc2961fa1ef0	502	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
Jonathan Austin	0:bc2961fa1ef0	503	__I uint32_t RESERVED16[668];
Jonathan Austin	0:bc2961fa1ef0	504	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	505	} NRF_TWI_Type;
Jonathan Austin	0:bc2961fa1ef0	506
Jonathan Austin	0:bc2961fa1ef0	507
Jonathan Austin	0:bc2961fa1ef0	508	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	509	/* ================ SPIS ================ */
Jonathan Austin	0:bc2961fa1ef0	510	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	511
Jonathan Austin	0:bc2961fa1ef0	512
Jonathan Austin	0:bc2961fa1ef0	513	/**
Jonathan Austin	0:bc2961fa1ef0	514	* @brief SPI slave 1. (SPIS)
Jonathan Austin	0:bc2961fa1ef0	515	*/
Jonathan Austin	0:bc2961fa1ef0	516
Jonathan Austin	0:bc2961fa1ef0	517	typedef struct { /!< SPIS Structure /
Jonathan Austin	0:bc2961fa1ef0	518	__I uint32_t RESERVED0[9];
Jonathan Austin	0:bc2961fa1ef0	519	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
Jonathan Austin	0:bc2961fa1ef0	520	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
Jonathan Austin	0:bc2961fa1ef0	521	__I uint32_t RESERVED1[54];
Jonathan Austin	0:bc2961fa1ef0	522	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
Jonathan Austin	0:bc2961fa1ef0	523	__I uint32_t RESERVED2[2];
Jonathan Austin	0:bc2961fa1ef0	524	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
Jonathan Austin	0:bc2961fa1ef0	525	__I uint32_t RESERVED3[5];
Jonathan Austin	0:bc2961fa1ef0	526	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
Jonathan Austin	0:bc2961fa1ef0	527	__I uint32_t RESERVED4[53];
Jonathan Austin	0:bc2961fa1ef0	528	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
Jonathan Austin	0:bc2961fa1ef0	529	__I uint32_t RESERVED5[64];
Jonathan Austin	0:bc2961fa1ef0	530	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	531	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	532	__I uint32_t RESERVED6[61];
Jonathan Austin	0:bc2961fa1ef0	533	__I uint32_t SEMSTAT; /!< Semaphore status. /
Jonathan Austin	0:bc2961fa1ef0	534	__I uint32_t RESERVED7[15];
Jonathan Austin	0:bc2961fa1ef0	535	__IO uint32_t STATUS; /!< Status from last transaction. /
Jonathan Austin	0:bc2961fa1ef0	536	__I uint32_t RESERVED8[47];
Jonathan Austin	0:bc2961fa1ef0	537	__IO uint32_t ENABLE; /!< Enable SPIS. /
Jonathan Austin	0:bc2961fa1ef0	538	__I uint32_t RESERVED9;
Jonathan Austin	0:bc2961fa1ef0	539	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
Jonathan Austin	0:bc2961fa1ef0	540	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
Jonathan Austin	0:bc2961fa1ef0	541	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
Jonathan Austin	0:bc2961fa1ef0	542	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
Jonathan Austin	0:bc2961fa1ef0	543	__I uint32_t RESERVED10[7];
Jonathan Austin	0:bc2961fa1ef0	544	__IO uint32_t RXDPTR; /!< RX data pointer. /
Jonathan Austin	0:bc2961fa1ef0	545	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
Jonathan Austin	0:bc2961fa1ef0	546	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
Jonathan Austin	0:bc2961fa1ef0	547	__I uint32_t RESERVED11;
Jonathan Austin	0:bc2961fa1ef0	548	__IO uint32_t TXDPTR; /!< TX data pointer. /
Jonathan Austin	0:bc2961fa1ef0	549	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
Jonathan Austin	0:bc2961fa1ef0	550	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
Jonathan Austin	0:bc2961fa1ef0	551	__I uint32_t RESERVED12;
Jonathan Austin	0:bc2961fa1ef0	552	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	553	__I uint32_t RESERVED13;
Jonathan Austin	0:bc2961fa1ef0	554	__IO uint32_t DEF; /!< Default character. /
Jonathan Austin	0:bc2961fa1ef0	555	__I uint32_t RESERVED14[24];
Jonathan Austin	0:bc2961fa1ef0	556	__IO uint32_t ORC; /!< Over-read character. /
Jonathan Austin	0:bc2961fa1ef0	557	__I uint32_t RESERVED15[654];
Jonathan Austin	0:bc2961fa1ef0	558	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	559	} NRF_SPIS_Type;
Jonathan Austin	0:bc2961fa1ef0	560
Jonathan Austin	0:bc2961fa1ef0	561
Jonathan Austin	0:bc2961fa1ef0	562	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	563	/* ================ SPIM ================ */
Jonathan Austin	0:bc2961fa1ef0	564	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	565
Jonathan Austin	0:bc2961fa1ef0	566
Jonathan Austin	0:bc2961fa1ef0	567	/**
Jonathan Austin	0:bc2961fa1ef0	568	* @brief SPI master with easyDMA 1. (SPIM)
Jonathan Austin	0:bc2961fa1ef0	569	*/
Jonathan Austin	0:bc2961fa1ef0	570
Jonathan Austin	0:bc2961fa1ef0	571	typedef struct { /!< SPIM Structure /
Jonathan Austin	0:bc2961fa1ef0	572	__I uint32_t RESERVED0[4];
Jonathan Austin	0:bc2961fa1ef0	573	__O uint32_t TASKS_START; /!< Start SPI transaction. /
Jonathan Austin	0:bc2961fa1ef0	574	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
Jonathan Austin	0:bc2961fa1ef0	575	__I uint32_t RESERVED1;
Jonathan Austin	0:bc2961fa1ef0	576	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
Jonathan Austin	0:bc2961fa1ef0	577	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
Jonathan Austin	0:bc2961fa1ef0	578	__I uint32_t RESERVED2[56];
Jonathan Austin	0:bc2961fa1ef0	579	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
Jonathan Austin	0:bc2961fa1ef0	580	__I uint32_t RESERVED3[2];
Jonathan Austin	0:bc2961fa1ef0	581	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
Jonathan Austin	0:bc2961fa1ef0	582	__I uint32_t RESERVED4[3];
Jonathan Austin	0:bc2961fa1ef0	583	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
Jonathan Austin	0:bc2961fa1ef0	584	__I uint32_t RESERVED5[10];
Jonathan Austin	0:bc2961fa1ef0	585	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
Jonathan Austin	0:bc2961fa1ef0	586	__I uint32_t RESERVED6[109];
Jonathan Austin	0:bc2961fa1ef0	587	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	588	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	589	__I uint32_t RESERVED7[125];
Jonathan Austin	0:bc2961fa1ef0	590	__IO uint32_t ENABLE; /!< Enable SPIM. /
Jonathan Austin	0:bc2961fa1ef0	591	__I uint32_t RESERVED8;
Jonathan Austin	0:bc2961fa1ef0	592	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
Jonathan Austin	0:bc2961fa1ef0	593	__I uint32_t RESERVED9[4];
Jonathan Austin	0:bc2961fa1ef0	594	__IO uint32_t FREQUENCY; /!< SPI frequency. /
Jonathan Austin	0:bc2961fa1ef0	595	__I uint32_t RESERVED10[3];
Jonathan Austin	0:bc2961fa1ef0	596	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
Jonathan Austin	0:bc2961fa1ef0	597	__I uint32_t RESERVED11;
Jonathan Austin	0:bc2961fa1ef0	598	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
Jonathan Austin	0:bc2961fa1ef0	599	__I uint32_t RESERVED12;
Jonathan Austin	0:bc2961fa1ef0	600	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	601	__I uint32_t RESERVED13[26];
Jonathan Austin	0:bc2961fa1ef0	602	__IO uint32_t ORC; /!< Over-read character. /
Jonathan Austin	0:bc2961fa1ef0	603	__I uint32_t RESERVED14[654];
Jonathan Austin	0:bc2961fa1ef0	604	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	605	} NRF_SPIM_Type;
Jonathan Austin	0:bc2961fa1ef0	606
Jonathan Austin	0:bc2961fa1ef0	607
Jonathan Austin	0:bc2961fa1ef0	608	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	609	/* ================ GPIOTE ================ */
Jonathan Austin	0:bc2961fa1ef0	610	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	611
Jonathan Austin	0:bc2961fa1ef0	612
Jonathan Austin	0:bc2961fa1ef0	613	/**
Jonathan Austin	0:bc2961fa1ef0	614	* @brief GPIO tasks and events. (GPIOTE)
Jonathan Austin	0:bc2961fa1ef0	615	*/
Jonathan Austin	0:bc2961fa1ef0	616
Jonathan Austin	0:bc2961fa1ef0	617	typedef struct { /!< GPIOTE Structure /
Jonathan Austin	0:bc2961fa1ef0	618	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
Jonathan Austin	0:bc2961fa1ef0	619	__I uint32_t RESERVED0[60];
Jonathan Austin	0:bc2961fa1ef0	620	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
Jonathan Austin	0:bc2961fa1ef0	621	__I uint32_t RESERVED1[27];
Jonathan Austin	0:bc2961fa1ef0	622	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
Jonathan Austin	0:bc2961fa1ef0	623	__I uint32_t RESERVED2[97];
Jonathan Austin	0:bc2961fa1ef0	624	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	625	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	626	__I uint32_t RESERVED3[129];
Jonathan Austin	0:bc2961fa1ef0	627	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
Jonathan Austin	0:bc2961fa1ef0	628	__I uint32_t RESERVED4[695];
Jonathan Austin	0:bc2961fa1ef0	629	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	630	} NRF_GPIOTE_Type;
Jonathan Austin	0:bc2961fa1ef0	631
Jonathan Austin	0:bc2961fa1ef0	632
Jonathan Austin	0:bc2961fa1ef0	633	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	634	/* ================ ADC ================ */
Jonathan Austin	0:bc2961fa1ef0	635	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	636
Jonathan Austin	0:bc2961fa1ef0	637
Jonathan Austin	0:bc2961fa1ef0	638	/**
Jonathan Austin	0:bc2961fa1ef0	639	* @brief Analog to digital converter. (ADC)
Jonathan Austin	0:bc2961fa1ef0	640	*/
Jonathan Austin	0:bc2961fa1ef0	641
Jonathan Austin	0:bc2961fa1ef0	642	typedef struct { /!< ADC Structure /
Jonathan Austin	0:bc2961fa1ef0	643	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
Jonathan Austin	0:bc2961fa1ef0	644	__O uint32_t TASKS_STOP; /!< Stop ADC. /
Jonathan Austin	0:bc2961fa1ef0	645	__I uint32_t RESERVED0[62];
Jonathan Austin	0:bc2961fa1ef0	646	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
Jonathan Austin	0:bc2961fa1ef0	647	__I uint32_t RESERVED1[128];
Jonathan Austin	0:bc2961fa1ef0	648	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	649	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	650	__I uint32_t RESERVED2[61];
Jonathan Austin	0:bc2961fa1ef0	651	__I uint32_t BUSY; /!< ADC busy register. /
Jonathan Austin	0:bc2961fa1ef0	652	__I uint32_t RESERVED3[63];
Jonathan Austin	0:bc2961fa1ef0	653	__IO uint32_t ENABLE; /!< ADC enable. /
Jonathan Austin	0:bc2961fa1ef0	654	__IO uint32_t CONFIG; /!< ADC configuration register. /
Jonathan Austin	0:bc2961fa1ef0	655	__I uint32_t RESULT; /!< Result of ADC conversion. /
Jonathan Austin	0:bc2961fa1ef0	656	__I uint32_t RESERVED4[700];
Jonathan Austin	0:bc2961fa1ef0	657	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	658	} NRF_ADC_Type;
Jonathan Austin	0:bc2961fa1ef0	659
Jonathan Austin	0:bc2961fa1ef0	660
Jonathan Austin	0:bc2961fa1ef0	661	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	662	/* ================ TIMER ================ */
Jonathan Austin	0:bc2961fa1ef0	663	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	664
Jonathan Austin	0:bc2961fa1ef0	665
Jonathan Austin	0:bc2961fa1ef0	666	/**
Jonathan Austin	0:bc2961fa1ef0	667	* @brief Timer 0. (TIMER)
Jonathan Austin	0:bc2961fa1ef0	668	*/
Jonathan Austin	0:bc2961fa1ef0	669
Jonathan Austin	0:bc2961fa1ef0	670	typedef struct { /!< TIMER Structure /
Jonathan Austin	0:bc2961fa1ef0	671	__O uint32_t TASKS_START; /!< Start Timer. /
Jonathan Austin	0:bc2961fa1ef0	672	__O uint32_t TASKS_STOP; /!< Stop Timer. /
Jonathan Austin	0:bc2961fa1ef0	673	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
Jonathan Austin	0:bc2961fa1ef0	674	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
Jonathan Austin	0:bc2961fa1ef0	675	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
Jonathan Austin	0:bc2961fa1ef0	676	__I uint32_t RESERVED0[11];
Jonathan Austin	0:bc2961fa1ef0	677	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
Jonathan Austin	0:bc2961fa1ef0	678	__I uint32_t RESERVED1[60];
Jonathan Austin	0:bc2961fa1ef0	679	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
Jonathan Austin	0:bc2961fa1ef0	680	__I uint32_t RESERVED2[44];
Jonathan Austin	0:bc2961fa1ef0	681	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
Jonathan Austin	0:bc2961fa1ef0	682	__I uint32_t RESERVED3[64];
Jonathan Austin	0:bc2961fa1ef0	683	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	684	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	685	__I uint32_t RESERVED4[126];
Jonathan Austin	0:bc2961fa1ef0	686	__IO uint32_t MODE; /!< Timer Mode selection. /
Jonathan Austin	0:bc2961fa1ef0	687	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
Jonathan Austin	0:bc2961fa1ef0	688	__I uint32_t RESERVED5;
Jonathan Austin	0:bc2961fa1ef0	689	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Jonathan Austin	0:bc2961fa1ef0	690	clock frequency is divided by 2^SCALE. */
Jonathan Austin	0:bc2961fa1ef0	691	__I uint32_t RESERVED6[11];
Jonathan Austin	0:bc2961fa1ef0	692	__IO uint32_t CC[4]; /!< Capture/compare registers. /
Jonathan Austin	0:bc2961fa1ef0	693	__I uint32_t RESERVED7[683];
Jonathan Austin	0:bc2961fa1ef0	694	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	695	} NRF_TIMER_Type;
Jonathan Austin	0:bc2961fa1ef0	696
Jonathan Austin	0:bc2961fa1ef0	697
Jonathan Austin	0:bc2961fa1ef0	698	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	699	/* ================ RTC ================ */
Jonathan Austin	0:bc2961fa1ef0	700	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	701
Jonathan Austin	0:bc2961fa1ef0	702
Jonathan Austin	0:bc2961fa1ef0	703	/**
Jonathan Austin	0:bc2961fa1ef0	704	* @brief Real time counter 0. (RTC)
Jonathan Austin	0:bc2961fa1ef0	705	*/
Jonathan Austin	0:bc2961fa1ef0	706
Jonathan Austin	0:bc2961fa1ef0	707	typedef struct { /!< RTC Structure /
Jonathan Austin	0:bc2961fa1ef0	708	__O uint32_t TASKS_START; /!< Start RTC Counter. /
Jonathan Austin	0:bc2961fa1ef0	709	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
Jonathan Austin	0:bc2961fa1ef0	710	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
Jonathan Austin	0:bc2961fa1ef0	711	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
Jonathan Austin	0:bc2961fa1ef0	712	__I uint32_t RESERVED0[60];
Jonathan Austin	0:bc2961fa1ef0	713	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
Jonathan Austin	0:bc2961fa1ef0	714	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
Jonathan Austin	0:bc2961fa1ef0	715	__I uint32_t RESERVED1[14];
Jonathan Austin	0:bc2961fa1ef0	716	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
Jonathan Austin	0:bc2961fa1ef0	717	__I uint32_t RESERVED2[109];
Jonathan Austin	0:bc2961fa1ef0	718	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	719	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	720	__I uint32_t RESERVED3[13];
Jonathan Austin	0:bc2961fa1ef0	721	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
Jonathan Austin	0:bc2961fa1ef0	722	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Jonathan Austin	0:bc2961fa1ef0	723	the value of EVTEN. */
Jonathan Austin	0:bc2961fa1ef0	724	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Jonathan Austin	0:bc2961fa1ef0	725	gives the value of EVTEN. */
Jonathan Austin	0:bc2961fa1ef0	726	__I uint32_t RESERVED4[110];
Jonathan Austin	0:bc2961fa1ef0	727	__I uint32_t COUNTER; /!< Current COUNTER value. /
Jonathan Austin	0:bc2961fa1ef0	728	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Jonathan Austin	0:bc2961fa1ef0	729	Must be written when RTC is STOPed. */
Jonathan Austin	0:bc2961fa1ef0	730	__I uint32_t RESERVED5[13];
Jonathan Austin	0:bc2961fa1ef0	731	__IO uint32_t CC[4]; /!< Capture/compare registers. /
Jonathan Austin	0:bc2961fa1ef0	732	__I uint32_t RESERVED6[683];
Jonathan Austin	0:bc2961fa1ef0	733	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	734	} NRF_RTC_Type;
Jonathan Austin	0:bc2961fa1ef0	735
Jonathan Austin	0:bc2961fa1ef0	736
Jonathan Austin	0:bc2961fa1ef0	737	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	738	/* ================ TEMP ================ */
Jonathan Austin	0:bc2961fa1ef0	739	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	740
Jonathan Austin	0:bc2961fa1ef0	741
Jonathan Austin	0:bc2961fa1ef0	742	/**
Jonathan Austin	0:bc2961fa1ef0	743	* @brief Temperature Sensor. (TEMP)
Jonathan Austin	0:bc2961fa1ef0	744	*/
Jonathan Austin	0:bc2961fa1ef0	745
Jonathan Austin	0:bc2961fa1ef0	746	typedef struct { /!< TEMP Structure /
Jonathan Austin	0:bc2961fa1ef0	747	__O uint32_t TASKS_START; /!< Start temperature measurement. /
Jonathan Austin	0:bc2961fa1ef0	748	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
Jonathan Austin	0:bc2961fa1ef0	749	__I uint32_t RESERVED0[62];
Jonathan Austin	0:bc2961fa1ef0	750	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
Jonathan Austin	0:bc2961fa1ef0	751	__I uint32_t RESERVED1[128];
Jonathan Austin	0:bc2961fa1ef0	752	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	753	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	754	__I uint32_t RESERVED2[127];
Jonathan Austin	0:bc2961fa1ef0	755	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
Jonathan Austin	0:bc2961fa1ef0	756	__I uint32_t RESERVED3[700];
Jonathan Austin	0:bc2961fa1ef0	757	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	758	} NRF_TEMP_Type;
Jonathan Austin	0:bc2961fa1ef0	759
Jonathan Austin	0:bc2961fa1ef0	760
Jonathan Austin	0:bc2961fa1ef0	761	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	762	/* ================ RNG ================ */
Jonathan Austin	0:bc2961fa1ef0	763	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	764
Jonathan Austin	0:bc2961fa1ef0	765
Jonathan Austin	0:bc2961fa1ef0	766	/**
Jonathan Austin	0:bc2961fa1ef0	767	* @brief Random Number Generator. (RNG)
Jonathan Austin	0:bc2961fa1ef0	768	*/
Jonathan Austin	0:bc2961fa1ef0	769
Jonathan Austin	0:bc2961fa1ef0	770	typedef struct { /!< RNG Structure /
Jonathan Austin	0:bc2961fa1ef0	771	__O uint32_t TASKS_START; /!< Start the random number generator. /
Jonathan Austin	0:bc2961fa1ef0	772	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
Jonathan Austin	0:bc2961fa1ef0	773	__I uint32_t RESERVED0[62];
Jonathan Austin	0:bc2961fa1ef0	774	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
Jonathan Austin	0:bc2961fa1ef0	775	__I uint32_t RESERVED1[63];
Jonathan Austin	0:bc2961fa1ef0	776	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
Jonathan Austin	0:bc2961fa1ef0	777	__I uint32_t RESERVED2[64];
Jonathan Austin	0:bc2961fa1ef0	778	__IO uint32_t INTENSET; /!< Interrupt enable set register /
Jonathan Austin	0:bc2961fa1ef0	779	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
Jonathan Austin	0:bc2961fa1ef0	780	__I uint32_t RESERVED3[126];
Jonathan Austin	0:bc2961fa1ef0	781	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	782	__I uint32_t VALUE; /!< RNG random number. /
Jonathan Austin	0:bc2961fa1ef0	783	__I uint32_t RESERVED4[700];
Jonathan Austin	0:bc2961fa1ef0	784	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	785	} NRF_RNG_Type;
Jonathan Austin	0:bc2961fa1ef0	786
Jonathan Austin	0:bc2961fa1ef0	787
Jonathan Austin	0:bc2961fa1ef0	788	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	789	/* ================ ECB ================ */
Jonathan Austin	0:bc2961fa1ef0	790	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	791
Jonathan Austin	0:bc2961fa1ef0	792
Jonathan Austin	0:bc2961fa1ef0	793	/**
Jonathan Austin	0:bc2961fa1ef0	794	* @brief AES ECB Mode Encryption. (ECB)
Jonathan Austin	0:bc2961fa1ef0	795	*/
Jonathan Austin	0:bc2961fa1ef0	796
Jonathan Austin	0:bc2961fa1ef0	797	typedef struct { /!< ECB Structure /
Jonathan Austin	0:bc2961fa1ef0	798	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Jonathan Austin	0:bc2961fa1ef0	799	will not initiate a new encryption and the ERRORECB event will
Jonathan Austin	0:bc2961fa1ef0	800	be triggered. */
Jonathan Austin	0:bc2961fa1ef0	801	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Jonathan Austin	0:bc2961fa1ef0	802	this will will trigger the ERRORECB event. */
Jonathan Austin	0:bc2961fa1ef0	803	__I uint32_t RESERVED0[62];
Jonathan Austin	0:bc2961fa1ef0	804	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
Jonathan Austin	0:bc2961fa1ef0	805	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Jonathan Austin	0:bc2961fa1ef0	806	error. */
Jonathan Austin	0:bc2961fa1ef0	807	__I uint32_t RESERVED1[127];
Jonathan Austin	0:bc2961fa1ef0	808	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	809	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	810	__I uint32_t RESERVED2[126];
Jonathan Austin	0:bc2961fa1ef0	811	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
Jonathan Austin	0:bc2961fa1ef0	812	__I uint32_t RESERVED3[701];
Jonathan Austin	0:bc2961fa1ef0	813	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	814	} NRF_ECB_Type;
Jonathan Austin	0:bc2961fa1ef0	815
Jonathan Austin	0:bc2961fa1ef0	816
Jonathan Austin	0:bc2961fa1ef0	817	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	818	/* ================ AAR ================ */
Jonathan Austin	0:bc2961fa1ef0	819	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	820
Jonathan Austin	0:bc2961fa1ef0	821
Jonathan Austin	0:bc2961fa1ef0	822	/**
Jonathan Austin	0:bc2961fa1ef0	823	* @brief Accelerated Address Resolver. (AAR)
Jonathan Austin	0:bc2961fa1ef0	824	*/
Jonathan Austin	0:bc2961fa1ef0	825
Jonathan Austin	0:bc2961fa1ef0	826	typedef struct { /!< AAR Structure /
Jonathan Austin	0:bc2961fa1ef0	827	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Jonathan Austin	0:bc2961fa1ef0	828	data structure. */
Jonathan Austin	0:bc2961fa1ef0	829	__I uint32_t RESERVED0;
Jonathan Austin	0:bc2961fa1ef0	830	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
Jonathan Austin	0:bc2961fa1ef0	831	__I uint32_t RESERVED1[61];
Jonathan Austin	0:bc2961fa1ef0	832	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
Jonathan Austin	0:bc2961fa1ef0	833	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
Jonathan Austin	0:bc2961fa1ef0	834	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
Jonathan Austin	0:bc2961fa1ef0	835	__I uint32_t RESERVED2[126];
Jonathan Austin	0:bc2961fa1ef0	836	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	837	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	838	__I uint32_t RESERVED3[61];
Jonathan Austin	0:bc2961fa1ef0	839	__I uint32_t STATUS; /!< Resolution status. /
Jonathan Austin	0:bc2961fa1ef0	840	__I uint32_t RESERVED4[63];
Jonathan Austin	0:bc2961fa1ef0	841	__IO uint32_t ENABLE; /!< Enable AAR. /
Jonathan Austin	0:bc2961fa1ef0	842	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
Jonathan Austin	0:bc2961fa1ef0	843	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
Jonathan Austin	0:bc2961fa1ef0	844	__I uint32_t RESERVED5;
Jonathan Austin	0:bc2961fa1ef0	845	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
Jonathan Austin	0:bc2961fa1ef0	846	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Jonathan Austin	0:bc2961fa1ef0	847	during resolution. A minimum of 3 bytes must be reserved. */
Jonathan Austin	0:bc2961fa1ef0	848	__I uint32_t RESERVED6[697];
Jonathan Austin	0:bc2961fa1ef0	849	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	850	} NRF_AAR_Type;
Jonathan Austin	0:bc2961fa1ef0	851
Jonathan Austin	0:bc2961fa1ef0	852
Jonathan Austin	0:bc2961fa1ef0	853	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	854	/* ================ CCM ================ */
Jonathan Austin	0:bc2961fa1ef0	855	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	856
Jonathan Austin	0:bc2961fa1ef0	857
Jonathan Austin	0:bc2961fa1ef0	858	/**
Jonathan Austin	0:bc2961fa1ef0	859	* @brief AES CCM Mode Encryption. (CCM)
Jonathan Austin	0:bc2961fa1ef0	860	*/
Jonathan Austin	0:bc2961fa1ef0	861
Jonathan Austin	0:bc2961fa1ef0	862	typedef struct { /!< CCM Structure /
Jonathan Austin	0:bc2961fa1ef0	863	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Jonathan Austin	0:bc2961fa1ef0	864	itself when completed. */
Jonathan Austin	0:bc2961fa1ef0	865	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Jonathan Austin	0:bc2961fa1ef0	866	completed. */
Jonathan Austin	0:bc2961fa1ef0	867	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
Jonathan Austin	0:bc2961fa1ef0	868	__I uint32_t RESERVED0[61];
Jonathan Austin	0:bc2961fa1ef0	869	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
Jonathan Austin	0:bc2961fa1ef0	870	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
Jonathan Austin	0:bc2961fa1ef0	871	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
Jonathan Austin	0:bc2961fa1ef0	872	__I uint32_t RESERVED1[61];
Jonathan Austin	0:bc2961fa1ef0	873	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
Jonathan Austin	0:bc2961fa1ef0	874	__I uint32_t RESERVED2[64];
Jonathan Austin	0:bc2961fa1ef0	875	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	876	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	877	__I uint32_t RESERVED3[61];
Jonathan Austin	0:bc2961fa1ef0	878	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
Jonathan Austin	0:bc2961fa1ef0	879	__I uint32_t RESERVED4[63];
Jonathan Austin	0:bc2961fa1ef0	880	__IO uint32_t ENABLE; /!< CCM enable. /
Jonathan Austin	0:bc2961fa1ef0	881	__IO uint32_t MODE; /!< Operation mode. /
Jonathan Austin	0:bc2961fa1ef0	882	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
Jonathan Austin	0:bc2961fa1ef0	883	__IO uint32_t INPTR; /!< Pointer to the input packet. /
Jonathan Austin	0:bc2961fa1ef0	884	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
Jonathan Austin	0:bc2961fa1ef0	885	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Jonathan Austin	0:bc2961fa1ef0	886	during resolution. A minimum of 43 bytes must be reserved. */
Jonathan Austin	0:bc2961fa1ef0	887	__I uint32_t RESERVED5[697];
Jonathan Austin	0:bc2961fa1ef0	888	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	889	} NRF_CCM_Type;
Jonathan Austin	0:bc2961fa1ef0	890
Jonathan Austin	0:bc2961fa1ef0	891
Jonathan Austin	0:bc2961fa1ef0	892	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	893	/* ================ WDT ================ */
Jonathan Austin	0:bc2961fa1ef0	894	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	895
Jonathan Austin	0:bc2961fa1ef0	896
Jonathan Austin	0:bc2961fa1ef0	897	/**
Jonathan Austin	0:bc2961fa1ef0	898	* @brief Watchdog Timer. (WDT)
Jonathan Austin	0:bc2961fa1ef0	899	*/
Jonathan Austin	0:bc2961fa1ef0	900
Jonathan Austin	0:bc2961fa1ef0	901	typedef struct { /!< WDT Structure /
Jonathan Austin	0:bc2961fa1ef0	902	__O uint32_t TASKS_START; /!< Start the watchdog. /
Jonathan Austin	0:bc2961fa1ef0	903	__I uint32_t RESERVED0[63];
Jonathan Austin	0:bc2961fa1ef0	904	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
Jonathan Austin	0:bc2961fa1ef0	905	__I uint32_t RESERVED1[128];
Jonathan Austin	0:bc2961fa1ef0	906	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	907	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	908	__I uint32_t RESERVED2[61];
Jonathan Austin	0:bc2961fa1ef0	909	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
Jonathan Austin	0:bc2961fa1ef0	910	__I uint32_t REQSTATUS; /!< Request status. /
Jonathan Austin	0:bc2961fa1ef0	911	__I uint32_t RESERVED3[63];
Jonathan Austin	0:bc2961fa1ef0	912	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
Jonathan Austin	0:bc2961fa1ef0	913	__IO uint32_t RREN; /!< Reload request enable. /
Jonathan Austin	0:bc2961fa1ef0	914	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	915	__I uint32_t RESERVED4[60];
Jonathan Austin	0:bc2961fa1ef0	916	__O uint32_t RR[8]; /!< Reload requests registers. /
Jonathan Austin	0:bc2961fa1ef0	917	__I uint32_t RESERVED5[631];
Jonathan Austin	0:bc2961fa1ef0	918	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	919	} NRF_WDT_Type;
Jonathan Austin	0:bc2961fa1ef0	920
Jonathan Austin	0:bc2961fa1ef0	921
Jonathan Austin	0:bc2961fa1ef0	922	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	923	/* ================ QDEC ================ */
Jonathan Austin	0:bc2961fa1ef0	924	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	925
Jonathan Austin	0:bc2961fa1ef0	926
Jonathan Austin	0:bc2961fa1ef0	927	/**
Jonathan Austin	0:bc2961fa1ef0	928	* @brief Rotary decoder. (QDEC)
Jonathan Austin	0:bc2961fa1ef0	929	*/
Jonathan Austin	0:bc2961fa1ef0	930
Jonathan Austin	0:bc2961fa1ef0	931	typedef struct { /!< QDEC Structure /
Jonathan Austin	0:bc2961fa1ef0	932	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
Jonathan Austin	0:bc2961fa1ef0	933	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
Jonathan Austin	0:bc2961fa1ef0	934	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Jonathan Austin	0:bc2961fa1ef0	935	and clears the ACC registers. */
Jonathan Austin	0:bc2961fa1ef0	936	__I uint32_t RESERVED0[61];
Jonathan Austin	0:bc2961fa1ef0	937	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
Jonathan Austin	0:bc2961fa1ef0	938	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Jonathan Austin	0:bc2961fa1ef0	939	ACC register different than zero. */
Jonathan Austin	0:bc2961fa1ef0	940	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
Jonathan Austin	0:bc2961fa1ef0	941	__I uint32_t RESERVED1[61];
Jonathan Austin	0:bc2961fa1ef0	942	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
Jonathan Austin	0:bc2961fa1ef0	943	__I uint32_t RESERVED2[64];
Jonathan Austin	0:bc2961fa1ef0	944	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	945	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	946	__I uint32_t RESERVED3[125];
Jonathan Austin	0:bc2961fa1ef0	947	__IO uint32_t ENABLE; /!< Enable the QDEC. /
Jonathan Austin	0:bc2961fa1ef0	948	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
Jonathan Austin	0:bc2961fa1ef0	949	__IO uint32_t SAMPLEPER; /!< Sample period. /
Jonathan Austin	0:bc2961fa1ef0	950	__I int32_t SAMPLE; /!< Motion sample value. /
Jonathan Austin	0:bc2961fa1ef0	951	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
Jonathan Austin	0:bc2961fa1ef0	952	__I int32_t ACC; /!< Accumulated valid transitions register. /
Jonathan Austin	0:bc2961fa1ef0	953	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Jonathan Austin	0:bc2961fa1ef0	954	task. */
Jonathan Austin	0:bc2961fa1ef0	955	__IO uint32_t PSELLED; /!< Pin select for LED output. /
Jonathan Austin	0:bc2961fa1ef0	956	__IO uint32_t PSELA; /!< Pin select for phase A input. /
Jonathan Austin	0:bc2961fa1ef0	957	__IO uint32_t PSELB; /!< Pin select for phase B input. /
Jonathan Austin	0:bc2961fa1ef0	958	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
Jonathan Austin	0:bc2961fa1ef0	959	__I uint32_t RESERVED4[5];
Jonathan Austin	0:bc2961fa1ef0	960	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
Jonathan Austin	0:bc2961fa1ef0	961	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
Jonathan Austin	0:bc2961fa1ef0	962	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Jonathan Austin	0:bc2961fa1ef0	963	task. */
Jonathan Austin	0:bc2961fa1ef0	964	__I uint32_t RESERVED5[684];
Jonathan Austin	0:bc2961fa1ef0	965	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	966	} NRF_QDEC_Type;
Jonathan Austin	0:bc2961fa1ef0	967
Jonathan Austin	0:bc2961fa1ef0	968
Jonathan Austin	0:bc2961fa1ef0	969	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	970	/* ================ LPCOMP ================ */
Jonathan Austin	0:bc2961fa1ef0	971	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	972
Jonathan Austin	0:bc2961fa1ef0	973
Jonathan Austin	0:bc2961fa1ef0	974	/**
Jonathan Austin	0:bc2961fa1ef0	975	* @brief Low power comparator. (LPCOMP)
Jonathan Austin	0:bc2961fa1ef0	976	*/
Jonathan Austin	0:bc2961fa1ef0	977
Jonathan Austin	0:bc2961fa1ef0	978	typedef struct { /!< LPCOMP Structure /
Jonathan Austin	0:bc2961fa1ef0	979	__O uint32_t TASKS_START; /!< Start the comparator. /
Jonathan Austin	0:bc2961fa1ef0	980	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
Jonathan Austin	0:bc2961fa1ef0	981	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
Jonathan Austin	0:bc2961fa1ef0	982	__I uint32_t RESERVED0[61];
Jonathan Austin	0:bc2961fa1ef0	983	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
Jonathan Austin	0:bc2961fa1ef0	984	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
Jonathan Austin	0:bc2961fa1ef0	985	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
Jonathan Austin	0:bc2961fa1ef0	986	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
Jonathan Austin	0:bc2961fa1ef0	987	__I uint32_t RESERVED1[60];
Jonathan Austin	0:bc2961fa1ef0	988	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
Jonathan Austin	0:bc2961fa1ef0	989	__I uint32_t RESERVED2[64];
Jonathan Austin	0:bc2961fa1ef0	990	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
Jonathan Austin	0:bc2961fa1ef0	991	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
Jonathan Austin	0:bc2961fa1ef0	992	__I uint32_t RESERVED3[61];
Jonathan Austin	0:bc2961fa1ef0	993	__I uint32_t RESULT; /!< Result of last compare. /
Jonathan Austin	0:bc2961fa1ef0	994	__I uint32_t RESERVED4[63];
Jonathan Austin	0:bc2961fa1ef0	995	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
Jonathan Austin	0:bc2961fa1ef0	996	__IO uint32_t PSEL; /!< Input pin select. /
Jonathan Austin	0:bc2961fa1ef0	997	__IO uint32_t REFSEL; /!< Reference select. /
Jonathan Austin	0:bc2961fa1ef0	998	__IO uint32_t EXTREFSEL; /!< External reference select. /
Jonathan Austin	0:bc2961fa1ef0	999	__I uint32_t RESERVED5[4];
Jonathan Austin	0:bc2961fa1ef0	1000	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
Jonathan Austin	0:bc2961fa1ef0	1001	__I uint32_t RESERVED6[694];
Jonathan Austin	0:bc2961fa1ef0	1002	__IO uint32_t POWER; /!< Peripheral power control. /
Jonathan Austin	0:bc2961fa1ef0	1003	} NRF_LPCOMP_Type;
Jonathan Austin	0:bc2961fa1ef0	1004
Jonathan Austin	0:bc2961fa1ef0	1005
Jonathan Austin	0:bc2961fa1ef0	1006	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1007	/* ================ SWI ================ */
Jonathan Austin	0:bc2961fa1ef0	1008	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1009
Jonathan Austin	0:bc2961fa1ef0	1010
Jonathan Austin	0:bc2961fa1ef0	1011	/**
Jonathan Austin	0:bc2961fa1ef0	1012	* @brief SW Interrupts. (SWI)
Jonathan Austin	0:bc2961fa1ef0	1013	*/
Jonathan Austin	0:bc2961fa1ef0	1014
Jonathan Austin	0:bc2961fa1ef0	1015	typedef struct { /!< SWI Structure /
Jonathan Austin	0:bc2961fa1ef0	1016	__I uint32_t UNUSED; /!< Unused. /
Jonathan Austin	0:bc2961fa1ef0	1017	} NRF_SWI_Type;
Jonathan Austin	0:bc2961fa1ef0	1018
Jonathan Austin	0:bc2961fa1ef0	1019
Jonathan Austin	0:bc2961fa1ef0	1020	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1021	/* ================ NVMC ================ */
Jonathan Austin	0:bc2961fa1ef0	1022	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1023
Jonathan Austin	0:bc2961fa1ef0	1024
Jonathan Austin	0:bc2961fa1ef0	1025	/**
Jonathan Austin	0:bc2961fa1ef0	1026	* @brief Non Volatile Memory Controller. (NVMC)
Jonathan Austin	0:bc2961fa1ef0	1027	*/
Jonathan Austin	0:bc2961fa1ef0	1028
Jonathan Austin	0:bc2961fa1ef0	1029	typedef struct { /!< NVMC Structure /
Jonathan Austin	0:bc2961fa1ef0	1030	__I uint32_t RESERVED0[256];
Jonathan Austin	0:bc2961fa1ef0	1031	__I uint32_t READY; /!< Ready flag. /
Jonathan Austin	0:bc2961fa1ef0	1032	__I uint32_t RESERVED1[64];
Jonathan Austin	0:bc2961fa1ef0	1033	__IO uint32_t CONFIG; /!< Configuration register. /
Jonathan Austin	0:bc2961fa1ef0	1034
Jonathan Austin	0:bc2961fa1ef0	1035	union {
Jonathan Austin	0:bc2961fa1ef0	1036	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
Jonathan Austin	0:bc2961fa1ef0	1037	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
Jonathan Austin	0:bc2961fa1ef0	1038	};
Jonathan Austin	0:bc2961fa1ef0	1039	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
Jonathan Austin	0:bc2961fa1ef0	1040	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
Jonathan Austin	0:bc2961fa1ef0	1041	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
Jonathan Austin	0:bc2961fa1ef0	1042	} NRF_NVMC_Type;
Jonathan Austin	0:bc2961fa1ef0	1043
Jonathan Austin	0:bc2961fa1ef0	1044
Jonathan Austin	0:bc2961fa1ef0	1045	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1046	/* ================ PPI ================ */
Jonathan Austin	0:bc2961fa1ef0	1047	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1048
Jonathan Austin	0:bc2961fa1ef0	1049
Jonathan Austin	0:bc2961fa1ef0	1050	/**
Jonathan Austin	0:bc2961fa1ef0	1051	* @brief PPI controller. (PPI)
Jonathan Austin	0:bc2961fa1ef0	1052	*/
Jonathan Austin	0:bc2961fa1ef0	1053
Jonathan Austin	0:bc2961fa1ef0	1054	typedef struct { /!< PPI Structure /
Jonathan Austin	0:bc2961fa1ef0	1055	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
Jonathan Austin	0:bc2961fa1ef0	1056	__I uint32_t RESERVED0[312];
Jonathan Austin	0:bc2961fa1ef0	1057	__IO uint32_t CHEN; /!< Channel enable. /
Jonathan Austin	0:bc2961fa1ef0	1058	__IO uint32_t CHENSET; /!< Channel enable set. /
Jonathan Austin	0:bc2961fa1ef0	1059	__IO uint32_t CHENCLR; /!< Channel enable clear. /
Jonathan Austin	0:bc2961fa1ef0	1060	__I uint32_t RESERVED1;
Jonathan Austin	0:bc2961fa1ef0	1061	PPI_CH_Type CH[16]; /!< PPI Channel. /
Jonathan Austin	0:bc2961fa1ef0	1062	__I uint32_t RESERVED2[156];
Jonathan Austin	0:bc2961fa1ef0	1063	__IO uint32_t CHG[4]; /!< Channel group configuration. /
Jonathan Austin	0:bc2961fa1ef0	1064	} NRF_PPI_Type;
Jonathan Austin	0:bc2961fa1ef0	1065
Jonathan Austin	0:bc2961fa1ef0	1066
Jonathan Austin	0:bc2961fa1ef0	1067	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1068	/* ================ FICR ================ */
Jonathan Austin	0:bc2961fa1ef0	1069	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1070
Jonathan Austin	0:bc2961fa1ef0	1071
Jonathan Austin	0:bc2961fa1ef0	1072	/**
Jonathan Austin	0:bc2961fa1ef0	1073	* @brief Factory Information Configuration. (FICR)
Jonathan Austin	0:bc2961fa1ef0	1074	*/
Jonathan Austin	0:bc2961fa1ef0	1075
Jonathan Austin	0:bc2961fa1ef0	1076	typedef struct { /!< FICR Structure /
Jonathan Austin	0:bc2961fa1ef0	1077	__I uint32_t RESERVED0[4];
Jonathan Austin	0:bc2961fa1ef0	1078	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
Jonathan Austin	0:bc2961fa1ef0	1079	__I uint32_t CODESIZE; /!< Code memory size in pages. /
Jonathan Austin	0:bc2961fa1ef0	1080	__I uint32_t RESERVED1[4];
Jonathan Austin	0:bc2961fa1ef0	1081	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
Jonathan Austin	0:bc2961fa1ef0	1082	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
Jonathan Austin	0:bc2961fa1ef0	1083	__I uint32_t RESERVED2;
Jonathan Austin	0:bc2961fa1ef0	1084	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
Jonathan Austin	0:bc2961fa1ef0	1085
Jonathan Austin	0:bc2961fa1ef0	1086	union {
Jonathan Austin	0:bc2961fa1ef0	1087	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Jonathan Austin	0:bc2961fa1ef0	1088	kept for backward compatinility purposes. Use SIZERAMBLOCKS
Jonathan Austin	0:bc2961fa1ef0	1089	instead. */
Jonathan Austin	0:bc2961fa1ef0	1090	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
Jonathan Austin	0:bc2961fa1ef0	1091	};
Jonathan Austin	0:bc2961fa1ef0	1092	__I uint32_t RESERVED3[5];
Jonathan Austin	0:bc2961fa1ef0	1093	__I uint32_t CONFIGID; /!< Configuration identifier. /
Jonathan Austin	0:bc2961fa1ef0	1094	__I uint32_t DEVICEID[2]; /!< Device identifier. /
Jonathan Austin	0:bc2961fa1ef0	1095	__I uint32_t RESERVED4[6];
Jonathan Austin	0:bc2961fa1ef0	1096	__I uint32_t ER[4]; /!< Encryption root. /
Jonathan Austin	0:bc2961fa1ef0	1097	__I uint32_t IR[4]; /!< Identity root. /
Jonathan Austin	0:bc2961fa1ef0	1098	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
Jonathan Austin	0:bc2961fa1ef0	1099	__I uint32_t DEVICEADDR[2]; /!< Device address. /
Jonathan Austin	0:bc2961fa1ef0	1100	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
Jonathan Austin	0:bc2961fa1ef0	1101	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Jonathan Austin	0:bc2961fa1ef0	1102	mode. */
Jonathan Austin	0:bc2961fa1ef0	1103	__I uint32_t RESERVED5[10];
Jonathan Austin	0:bc2961fa1ef0	1104	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Jonathan Austin	0:bc2961fa1ef0	1105	mode. */
Jonathan Austin	0:bc2961fa1ef0	1106	} NRF_FICR_Type;
Jonathan Austin	0:bc2961fa1ef0	1107
Jonathan Austin	0:bc2961fa1ef0	1108
Jonathan Austin	0:bc2961fa1ef0	1109	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1110	/* ================ UICR ================ */
Jonathan Austin	0:bc2961fa1ef0	1111	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1112
Jonathan Austin	0:bc2961fa1ef0	1113
Jonathan Austin	0:bc2961fa1ef0	1114	/**
Jonathan Austin	0:bc2961fa1ef0	1115	* @brief User Information Configuration. (UICR)
Jonathan Austin	0:bc2961fa1ef0	1116	*/
Jonathan Austin	0:bc2961fa1ef0	1117
Jonathan Austin	0:bc2961fa1ef0	1118	typedef struct { /!< UICR Structure /
Jonathan Austin	0:bc2961fa1ef0	1119	__IO uint32_t CLENR0; /!< Length of code region 0. /
Jonathan Austin	0:bc2961fa1ef0	1120	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
Jonathan Austin	0:bc2961fa1ef0	1121	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
Jonathan Austin	0:bc2961fa1ef0	1122	__I uint32_t RESERVED0;
Jonathan Austin	0:bc2961fa1ef0	1123	__I uint32_t FWID; /!< Firmware ID. /
Jonathan Austin	0:bc2961fa1ef0	1124
Jonathan Austin	0:bc2961fa1ef0	1125	union {
Jonathan Austin	0:bc2961fa1ef0	1126	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
Jonathan Austin	0:bc2961fa1ef0	1127	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
Jonathan Austin	0:bc2961fa1ef0	1128	};
Jonathan Austin	0:bc2961fa1ef0	1129	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
Jonathan Austin	0:bc2961fa1ef0	1130	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
Jonathan Austin	0:bc2961fa1ef0	1131	} NRF_UICR_Type;
Jonathan Austin	0:bc2961fa1ef0	1132
Jonathan Austin	0:bc2961fa1ef0	1133
Jonathan Austin	0:bc2961fa1ef0	1134	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1135	/* ================ GPIO ================ */
Jonathan Austin	0:bc2961fa1ef0	1136	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1137
Jonathan Austin	0:bc2961fa1ef0	1138
Jonathan Austin	0:bc2961fa1ef0	1139	/**
Jonathan Austin	0:bc2961fa1ef0	1140	* @brief General purpose input and output. (GPIO)
Jonathan Austin	0:bc2961fa1ef0	1141	*/
Jonathan Austin	0:bc2961fa1ef0	1142
Jonathan Austin	0:bc2961fa1ef0	1143	typedef struct { /!< GPIO Structure /
Jonathan Austin	0:bc2961fa1ef0	1144	__I uint32_t RESERVED0[321];
Jonathan Austin	0:bc2961fa1ef0	1145	__IO uint32_t OUT; /!< Write GPIO port. /
Jonathan Austin	0:bc2961fa1ef0	1146	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
Jonathan Austin	0:bc2961fa1ef0	1147	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
Jonathan Austin	0:bc2961fa1ef0	1148	__I uint32_t IN; /!< Read GPIO port. /
Jonathan Austin	0:bc2961fa1ef0	1149	__IO uint32_t DIR; /!< Direction of GPIO pins. /
Jonathan Austin	0:bc2961fa1ef0	1150	__IO uint32_t DIRSET; /!< DIR set register. /
Jonathan Austin	0:bc2961fa1ef0	1151	__IO uint32_t DIRCLR; /!< DIR clear register. /
Jonathan Austin	0:bc2961fa1ef0	1152	__I uint32_t RESERVED1[120];
Jonathan Austin	0:bc2961fa1ef0	1153	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
Jonathan Austin	0:bc2961fa1ef0	1154	} NRF_GPIO_Type;
Jonathan Austin	0:bc2961fa1ef0	1155
Jonathan Austin	0:bc2961fa1ef0	1156
Jonathan Austin	0:bc2961fa1ef0	1157	/* -------------------- End of section using anonymous unions ------------------- */
Jonathan Austin	0:bc2961fa1ef0	1158	#if defined(__CC_ARM)
Jonathan Austin	0:bc2961fa1ef0	1159	#pragma pop
Jonathan Austin	0:bc2961fa1ef0	1160	#elif defined(__ICCARM__)
Jonathan Austin	0:bc2961fa1ef0	1161	/* leave anonymous unions enabled */
Jonathan Austin	0:bc2961fa1ef0	1162	#elif defined(__GNUC__)
Jonathan Austin	0:bc2961fa1ef0	1163	/* anonymous unions are enabled by default */
Jonathan Austin	0:bc2961fa1ef0	1164	#elif defined(__TMS470__)
Jonathan Austin	0:bc2961fa1ef0	1165	/* anonymous unions are enabled by default */
Jonathan Austin	0:bc2961fa1ef0	1166	#elif defined(__TASKING__)
Jonathan Austin	0:bc2961fa1ef0	1167	#pragma warning restore
Jonathan Austin	0:bc2961fa1ef0	1168	#else
Jonathan Austin	0:bc2961fa1ef0	1169	#warning Not supported compiler type
Jonathan Austin	0:bc2961fa1ef0	1170	#endif
Jonathan Austin	0:bc2961fa1ef0	1171
Jonathan Austin	0:bc2961fa1ef0	1172
Jonathan Austin	0:bc2961fa1ef0	1173
Jonathan Austin	0:bc2961fa1ef0	1174
Jonathan Austin	0:bc2961fa1ef0	1175	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1176	/* ================ Peripheral memory map ================ */
Jonathan Austin	0:bc2961fa1ef0	1177	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1178
Jonathan Austin	0:bc2961fa1ef0	1179	#define NRF_POWER_BASE 0x40000000UL
Jonathan Austin	0:bc2961fa1ef0	1180	#define NRF_CLOCK_BASE 0x40000000UL
Jonathan Austin	0:bc2961fa1ef0	1181	#define NRF_MPU_BASE 0x40000000UL
Jonathan Austin	0:bc2961fa1ef0	1182	#define NRF_AMLI_BASE 0x40000000UL
Jonathan Austin	0:bc2961fa1ef0	1183	#define NRF_RADIO_BASE 0x40001000UL
Jonathan Austin	0:bc2961fa1ef0	1184	#define NRF_UART0_BASE 0x40002000UL
Jonathan Austin	0:bc2961fa1ef0	1185	#define NRF_SPI0_BASE 0x40003000UL
Jonathan Austin	0:bc2961fa1ef0	1186	#define NRF_TWI0_BASE 0x40003000UL
Jonathan Austin	0:bc2961fa1ef0	1187	#define NRF_SPI1_BASE 0x40004000UL
Jonathan Austin	0:bc2961fa1ef0	1188	#define NRF_TWI1_BASE 0x40004000UL
Jonathan Austin	0:bc2961fa1ef0	1189	#define NRF_SPIS1_BASE 0x40004000UL
Jonathan Austin	0:bc2961fa1ef0	1190	#define NRF_SPIM1_BASE 0x40004000UL
Jonathan Austin	0:bc2961fa1ef0	1191	#define NRF_GPIOTE_BASE 0x40006000UL
Jonathan Austin	0:bc2961fa1ef0	1192	#define NRF_ADC_BASE 0x40007000UL
Jonathan Austin	0:bc2961fa1ef0	1193	#define NRF_TIMER0_BASE 0x40008000UL
Jonathan Austin	0:bc2961fa1ef0	1194	#define NRF_TIMER1_BASE 0x40009000UL
Jonathan Austin	0:bc2961fa1ef0	1195	#define NRF_TIMER2_BASE 0x4000A000UL
Jonathan Austin	0:bc2961fa1ef0	1196	#define NRF_RTC0_BASE 0x4000B000UL
Jonathan Austin	0:bc2961fa1ef0	1197	#define NRF_TEMP_BASE 0x4000C000UL
Jonathan Austin	0:bc2961fa1ef0	1198	#define NRF_RNG_BASE 0x4000D000UL
Jonathan Austin	0:bc2961fa1ef0	1199	#define NRF_ECB_BASE 0x4000E000UL
Jonathan Austin	0:bc2961fa1ef0	1200	#define NRF_AAR_BASE 0x4000F000UL
Jonathan Austin	0:bc2961fa1ef0	1201	#define NRF_CCM_BASE 0x4000F000UL
Jonathan Austin	0:bc2961fa1ef0	1202	#define NRF_WDT_BASE 0x40010000UL
Jonathan Austin	0:bc2961fa1ef0	1203	#define NRF_RTC1_BASE 0x40011000UL
Jonathan Austin	0:bc2961fa1ef0	1204	#define NRF_QDEC_BASE 0x40012000UL
Jonathan Austin	0:bc2961fa1ef0	1205	#define NRF_LPCOMP_BASE 0x40013000UL
Jonathan Austin	0:bc2961fa1ef0	1206	#define NRF_SWI_BASE 0x40014000UL
Jonathan Austin	0:bc2961fa1ef0	1207	#define NRF_NVMC_BASE 0x4001E000UL
Jonathan Austin	0:bc2961fa1ef0	1208	#define NRF_PPI_BASE 0x4001F000UL
Jonathan Austin	0:bc2961fa1ef0	1209	#define NRF_FICR_BASE 0x10000000UL
Jonathan Austin	0:bc2961fa1ef0	1210	#define NRF_UICR_BASE 0x10001000UL
Jonathan Austin	0:bc2961fa1ef0	1211	#define NRF_GPIO_BASE 0x50000000UL
Jonathan Austin	0:bc2961fa1ef0	1212
Jonathan Austin	0:bc2961fa1ef0	1213
Jonathan Austin	0:bc2961fa1ef0	1214	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1215	/* ================ Peripheral declaration ================ */
Jonathan Austin	0:bc2961fa1ef0	1216	/* ================================================================================ */
Jonathan Austin	0:bc2961fa1ef0	1217
Jonathan Austin	0:bc2961fa1ef0	1218	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Jonathan Austin	0:bc2961fa1ef0	1219	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Jonathan Austin	0:bc2961fa1ef0	1220	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Jonathan Austin	0:bc2961fa1ef0	1221	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Jonathan Austin	0:bc2961fa1ef0	1222	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Jonathan Austin	0:bc2961fa1ef0	1223	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Jonathan Austin	0:bc2961fa1ef0	1224	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Jonathan Austin	0:bc2961fa1ef0	1225	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Jonathan Austin	0:bc2961fa1ef0	1226	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1227	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1228	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1229	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1230	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Jonathan Austin	0:bc2961fa1ef0	1231	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Jonathan Austin	0:bc2961fa1ef0	1232	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Jonathan Austin	0:bc2961fa1ef0	1233	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1234	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Jonathan Austin	0:bc2961fa1ef0	1235	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Jonathan Austin	0:bc2961fa1ef0	1236	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Jonathan Austin	0:bc2961fa1ef0	1237	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Jonathan Austin	0:bc2961fa1ef0	1238	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Jonathan Austin	0:bc2961fa1ef0	1239	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Jonathan Austin	0:bc2961fa1ef0	1240	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Jonathan Austin	0:bc2961fa1ef0	1241	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Jonathan Austin	0:bc2961fa1ef0	1242	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Jonathan Austin	0:bc2961fa1ef0	1243	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Jonathan Austin	0:bc2961fa1ef0	1244	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Jonathan Austin	0:bc2961fa1ef0	1245	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Jonathan Austin	0:bc2961fa1ef0	1246	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Jonathan Austin	0:bc2961fa1ef0	1247	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Jonathan Austin	0:bc2961fa1ef0	1248	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Jonathan Austin	0:bc2961fa1ef0	1249	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Jonathan Austin	0:bc2961fa1ef0	1250	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Jonathan Austin	0:bc2961fa1ef0	1251
Jonathan Austin	0:bc2961fa1ef0	1252
Jonathan Austin	0:bc2961fa1ef0	1253	/** @} / / End of group Device_Peripheral_Registers */
Jonathan Austin	0:bc2961fa1ef0	1254	/** @} / / End of group nrf51 */
Jonathan Austin	0:bc2961fa1ef0	1255	/** @} / / End of group Nordic Semiconductor */
Jonathan Austin	0:bc2961fa1ef0	1256
Jonathan Austin	0:bc2961fa1ef0	1257	#ifdef __cplusplus
Jonathan Austin	0:bc2961fa1ef0	1258	}
Jonathan Austin	0:bc2961fa1ef0	1259	#endif
Jonathan Austin	0:bc2961fa1ef0	1260
Jonathan Austin	0:bc2961fa1ef0	1261
Jonathan Austin	0:bc2961fa1ef0	1262	#endif /* nrf51_H */
Jonathan Austin	0:bc2961fa1ef0	1263

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Type:	Library
Created:	13 Jan 2017
Imports:	0
Forks:	0
Commits:	10
Dependents:	1
Dependencies:	0
Followers:	1

source/nordic_sdk/components/device/nrf51.h@9:118fd63123a5, 2017-01-13 (annotated)

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