Arthur Richard / ST7580

https://www.st.com/en/ecosystems/x-nucleo-plm01a1.html MBED driver for the ST7580 IC.

ST7580_codes.h@1:edbcde816013, 2019-04-20 (annotated)

Committer:
Arthrik
Date:
Sat Apr 20 20:18:49 2019 +0000
Revision:
1:edbcde816013
Parent:
0:e88514a784bb 
Data reception now works.; Updated the example code.; It still needs some work, but it's usable

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Arthrik 0:e88514a784bb 1
Arthrik 0:e88514a784bb 2 /***********************Uncomment the PLC Modem Operating mode*****************/
Arthrik 0:e88514a784bb 3 //#define USE_PHY_DATA
Arthrik 0:e88514a784bb 4 #define USE_DL_DATA
Arthrik 0:e88514a784bb 5 /******************************************************************************/
Arthrik 0:e88514a784bb 6
Arthrik 0:e88514a784bb 7 #define BPSK 0
Arthrik 0:e88514a784bb 8 #define QPSK 1
Arthrik 0:e88514a784bb 9 #define PSK8 2
Arthrik 0:e88514a784bb 10 #define BFSK 3
Arthrik 0:e88514a784bb 11 #define BPSKCOD 4
Arthrik 0:e88514a784bb 12 #define QPSKCOD 5
Arthrik 0:e88514a784bb 13 #define BPSKCODPEAKAV 7
Arthrik 0:e88514a784bb 14
Arthrik 0:e88514a784bb 15 /***********************Set configuration parameters **************************/
Arthrik 0:e88514a784bb 16 #define CUSTOM_MIB_FREQUENCY 0
Arthrik 0:e88514a784bb 17 #define FREQUENCY_OVERWRITE 0
Arthrik 0:e88514a784bb 18 #define FREQUENCY_SET 1
Arthrik 0:e88514a784bb 19 #define GAIN_SELECTOR 0
Arthrik 0:e88514a784bb 20
Arthrik 0:e88514a784bb 21 #define FRAME_MODULATION BPSKCOD
Arthrik 0:e88514a784bb 22 #define ZERO_CROSS_SYNC 0
Arthrik 0:e88514a784bb 23
Arthrik 0:e88514a784bb 24 #if CUSTOM_MIB_FREQUENCY
Arthrik 0:e88514a784bb 25 #define TXFREQ1 0
Arthrik 0:e88514a784bb 26 #define TXFREQ2 0
Arthrik 0:e88514a784bb 27 #define TXFREQ3 0
Arthrik 0:e88514a784bb 28 #endif
Arthrik 0:e88514a784bb 29
Arthrik 0:e88514a784bb 30 #if GAIN_SELECTOR
Arthrik 0:e88514a784bb 31 #define TXGAIN 0
Arthrik 0:e88514a784bb 32 #endif
Arthrik 0:e88514a784bb 33 /******************************************************************************/
Arthrik 0:e88514a784bb 34
Arthrik 0:e88514a784bb 35 //#define DATA_OPT 0x44
Arthrik 0:e88514a784bb 36 #define DATA_OPT ((CUSTOM_MIB_FREQUENCY) | \
Arthrik 0:e88514a784bb 37 (FREQUENCY_OVERWRITE << 1) | \
Arthrik 0:e88514a784bb 38 (FREQUENCY_SET << 2) | \
Arthrik 0:e88514a784bb 39 (GAIN_SELECTOR << 3) | \
Arthrik 0:e88514a784bb 40 (FRAME_MODULATION << 4) | \
Arthrik 0:e88514a784bb 41 (ZERO_CROSS_SYNC << 7))
Arthrik 0:e88514a784bb 42
Arthrik 0:e88514a784bb 43 #define IND_FRAMES_QUEUE_LEN 6 /* Indication Frames Queue length */
Arthrik 0:e88514a784bb 44 #define PHY_DATALEN_MAX 250
Arthrik 0:e88514a784bb 45 #define DL_DATALEN_MAX 242
Arthrik 0:e88514a784bb 46 #define SS_DATALEN_MAX 226
Arthrik 0:e88514a784bb 47
Arthrik 0:e88514a784bb 48 /**
Arthrik 0:e88514a784bb 49 * @brief Timeout parameters
Arthrik 0:e88514a784bb 50 */
Arthrik 0:e88514a784bb 51 #define IC_TMO 10 /* Intercharacter timeout msec */
Arthrik 0:e88514a784bb 52 #define ACK_TMO 40 /* ACK timeout msec */
Arthrik 0:e88514a784bb 53 #define STATUS_MSG_TMO 200 /* Status Message timeout msec */
Arthrik 0:e88514a784bb 54 #define CMD_TMO 4000 /* Comand timeout */
Arthrik 0:e88514a784bb 55 #define RESET_IND_TMO 4000 /* Reset Indication timeout */
Arthrik 0:e88514a784bb 56
Arthrik 0:e88514a784bb 57 #define N_TIMEOUTS 4 /* Three different kind of timeouts */
Arthrik 0:e88514a784bb 58 #define IC_TMO_IDX 0 /* Intercharacter timeout ID */
Arthrik 0:e88514a784bb 59 #define ACK_TMO_IDX 1 /* ACK timeout ID */
Arthrik 0:e88514a784bb 60 #define STATUS_MSG_TMO_IDX 2 /* Status Message timeout ID */
Arthrik 0:e88514a784bb 61 #define CMD_TMO_IDX 3 /* Comand timeout ID */
Arthrik 0:e88514a784bb 62
Arthrik 0:e88514a784bb 63 /**
Arthrik 0:e88514a784bb 64 * @brief Functions returns codes
Arthrik 0:e88514a784bb 65 */
Arthrik 0:e88514a784bb 66 #define ST7580_OK 0 /* Req/Res exchange ok */
Arthrik 0:e88514a784bb 67 #define ST7580_TX_IN_PROGRESS -1 /* Tx in course */
Arthrik 0:e88514a784bb 68 #define ST7580_ERR_CONFIRM -2 /* Wrong confirm code */
Arthrik 0:e88514a784bb 69 #define ST7580_ERR_BUF_LEN -3 /* Wrong received buffer length */
Arthrik 0:e88514a784bb 70 #define ST7580_ERR_TIMEOUT -4 /* Timeout on response */
Arthrik 0:e88514a784bb 71 #define ST7580_ERR_PING -5 /* Pong data doesn't match Ping data */
Arthrik 0:e88514a784bb 72 #define ST7580_ERR_ARGS -6 /* Wrong function's argument */
Arthrik 0:e88514a784bb 73 #define ST7580_UNEXPECTED_FRAME -7 /* Unexpected local frame received */
Arthrik 0:e88514a784bb 74 #define ST7580_RCV_BUF_TOO_SMALL -8 /* Receive buffer too small */
Arthrik 0:e88514a784bb 75
Arthrik 0:e88514a784bb 76 #define ST7580_TXERR_NAK -10 /* NAK received */
Arthrik 0:e88514a784bb 77 #define ST7580_TXERR_NO_STATUS -11 /* No status received */
Arthrik 0:e88514a784bb 78 #define ST7580_TXERR_ACK_TMO -12 /* No ack received */
Arthrik 0:e88514a784bb 79 #define ST7580_TXERR_BUSY -13 /* ST7580 busy */
Arthrik 0:e88514a784bb 80
Arthrik 0:e88514a784bb 81 /**
Arthrik 0:e88514a784bb 82 * @brief Acknoledgement codes
Arthrik 0:e88514a784bb 83 */
Arthrik 0:e88514a784bb 84 #define ST7580_ACK 0x06 /* ST7580 ACK */
Arthrik 0:e88514a784bb 85 #define ST7580_NAK 0x15 /* ST7580 NACK */
Arthrik 0:e88514a784bb 86 #define BUSY_MASK 0x06
Arthrik 0:e88514a784bb 87
Arthrik 0:e88514a784bb 88 /**
Arthrik 0:e88514a784bb 89 * @brief Start of frames codes
Arthrik 0:e88514a784bb 90 */
Arthrik 0:e88514a784bb 91 #define ST7580_STX_02 0x02
Arthrik 0:e88514a784bb 92 #define ST7580_STX_03 0x03
Arthrik 0:e88514a784bb 93 #define ST7580_STX_STATUS 0x3F
Arthrik 0:e88514a784bb 94
Arthrik 0:e88514a784bb 95 /**
Arthrik 0:e88514a784bb 96 * @brief Command codes
Arthrik 0:e88514a784bb 97 */
Arthrik 0:e88514a784bb 98 #define CMD_RESET_REQ 0x3C /* Reset request command */
Arthrik 0:e88514a784bb 99 #define CMD_RESET_CNF 0x3D /* Reset confirmation command */
Arthrik 0:e88514a784bb 100 #define CMD_RESET_IND 0x3E /* Reset indication command */
Arthrik 0:e88514a784bb 101 #define CMD_RESET_ERR 0x3F /* Reset error command code */
Arthrik 0:e88514a784bb 102
Arthrik 0:e88514a784bb 103 #define CMD_MIB_WRITE_REQ 0x08 /* MIB Write request command */
Arthrik 0:e88514a784bb 104 #define CMD_MIB_WRITE_CNF 0x09 /* MIB Write confirmation command */
Arthrik 0:e88514a784bb 105 #define CMD_MIB_WRITE_ERR 0x0B /* MIB Write error command */
Arthrik 0:e88514a784bb 106
Arthrik 0:e88514a784bb 107 #define CMD_MIB_READ_REQ 0x0C /* MIB Read request command */
Arthrik 0:e88514a784bb 108 #define CMD_MIB_READ_CNF 0x0D /* MIB Read confirmation command */
Arthrik 0:e88514a784bb 109 #define CMD_MIB_READ_ERR 0x0F /* MIB Read error command */
Arthrik 0:e88514a784bb 110
Arthrik 0:e88514a784bb 111 #define CMD_MIB_ERASE_REQ 0x10 /* MIB Erase request command */
Arthrik 0:e88514a784bb 112 #define CMD_MIB_ERASE_CNF 0x11 /* MIB Erase confirmation command */
Arthrik 0:e88514a784bb 113 #define CMD_MIB_ERASE_ERR 0x13 /* MIB Erase error command */
Arthrik 0:e88514a784bb 114
Arthrik 0:e88514a784bb 115 #define CMD_PING_REQ 0x2C /* PING request command */
Arthrik 0:e88514a784bb 116 #define CMD_PING_CNF 0x2D /* PING confirmation command */
Arthrik 0:e88514a784bb 117
Arthrik 0:e88514a784bb 118 #define CMD_PHY_DATA_REQ 0x24 /* PHY Data request command */
Arthrik 0:e88514a784bb 119 #define CMD_PHY_DATA_CNF 0x25 /* PHY Data confirmation command */
Arthrik 0:e88514a784bb 120 #define CMD_PHY_DATA_IND 0x26 /* PHY Data indication command */
Arthrik 0:e88514a784bb 121 #define CMD_PHY_DATA_ERR 0x27 /* PHY Data error command */
Arthrik 0:e88514a784bb 122
Arthrik 0:e88514a784bb 123 #define CMD_DL_DATA_REQ 0x50 /* DL Data request command */
Arthrik 0:e88514a784bb 124 #define CMD_DL_DATA_CNF 0x51 /* DL Data confirmation command */
Arthrik 0:e88514a784bb 125 #define CMD_DL_DATA_IND 0x52 /* DL Data indication command */
Arthrik 0:e88514a784bb 126 #define CMD_DL_DATA_ERR 0x53 /* DL Data error command */
Arthrik 0:e88514a784bb 127 #define CMD_DL_SNIFFER_IND 0x5A /* DL Sniffer indication command */
Arthrik 0:e88514a784bb 128
Arthrik 0:e88514a784bb 129 #define CMD_SS_DATA_REQ 0x54 /* SS Data request command */
Arthrik 0:e88514a784bb 130 #define CMD_SS_DATA_CNF 0x55 /* SS Data confirmation command */
Arthrik 0:e88514a784bb 131 #define CMD_SS_DATA_IND 0x56 /* SS Data indication command */
Arthrik 0:e88514a784bb 132 #define CMD_SS_DATA_ERR 0x57 /* SS Data error command */
Arthrik 0:e88514a784bb 133 #define CMD_SS_SNIFFER_IND 0x5E /* SS Sniffer indication command */
Arthrik 0:e88514a784bb 134
Arthrik 0:e88514a784bb 135 #define CMD_SYNTAX_ERR 0x36 /* Syntax error command code */
Arthrik 0:e88514a784bb 136
Arthrik 0:e88514a784bb 137 /*
Arthrik 0:e88514a784bb 138 * Returns true of the given command code is an indication, false otherwise
Arthrik 0:e88514a784bb 139 */
Arthrik 0:e88514a784bb 140 #define IS_INDICATION(CMD) ((CMD == CMD_RESET_IND) || \
Arthrik 0:e88514a784bb 141 (CMD == CMD_PHY_DATA_IND) || \
Arthrik 0:e88514a784bb 142 (CMD == CMD_DL_DATA_IND) || \
Arthrik 0:e88514a784bb 143 (CMD == CMD_DL_SNIFFER_IND) || \
Arthrik 0:e88514a784bb 144 (CMD == CMD_SS_DATA_IND) || \
Arthrik 0:e88514a784bb 145 (CMD == CMD_SS_SNIFFER_IND))
Arthrik 0:e88514a784bb 146
Arthrik 0:e88514a784bb 147 /**
Arthrik 0:e88514a784bb 148 * @brief Indexes
Arthrik 0:e88514a784bb 149 */
Arthrik 0:e88514a784bb 150 #define IND_FRAME_PAYLOAD_IDX 0x04 /* Payload offset inside packet */
Arthrik 0:e88514a784bb 151
Arthrik 0:e88514a784bb 152
Arthrik 0:e88514a784bb 153 /**
Arthrik 0:e88514a784bb 154 * @brief MIBs Objects
Arthrik 0:e88514a784bb 155 */
Arthrik 0:e88514a784bb 156 #define MIB_MODEM_CONF 0x00 /* Modem configuration MIB */
Arthrik 0:e88514a784bb 157 #define MIB_PHY_CONF 0x01 /* PHY configuration MIB */
Arthrik 0:e88514a784bb 158 #define MIB_SS_KEY 0x02 /* SS key MIB */
Arthrik 0:e88514a784bb 159 #define MIB_LAST_DATA_IND 0x04 /* Last data indication MIB */
Arthrik 0:e88514a784bb 160 #define MIB_LAST_TX_CNF 0x05 /* Last TX confirm MIB */
Arthrik 0:e88514a784bb 161 #define MIB_PHY_DATA 0x06 /* PHY Data MIB */
Arthrik 0:e88514a784bb 162 #define MIB_DL_DATA 0x07 /* DL Data MIB */
Arthrik 0:e88514a784bb 163 #define MIB_SS_DATA 0x08 /* SS Data MIB */
Arthrik 0:e88514a784bb 164 #define MIB_HOST_IF_TOUT 0x09 /* Host interface timeout MIB */
Arthrik 0:e88514a784bb 165 #define MIB_FW_VERSION 0x0A /* Firmware version MIB */
Arthrik 0:e88514a784bb 166
Arthrik 0:e88514a784bb 167 #define ST7580_MOD_BPSK (0 << 4) /* B-PSK modulation */
Arthrik 0:e88514a784bb 168 #define ST7580_MOD_QPSK (1 << 4) /* Q-PSK modulation */
Arthrik 0:e88514a784bb 169 #define ST7580_MOD_8PSK (2 << 4) /* 8-PSK modulation */
Arthrik 0:e88514a784bb 170 #define ST7580_MOD_BFSK (3 << 4) /* B-FSK modulation */
Arthrik 0:e88514a784bb 171 #define ST7580_MOD_BPSK_COD (4 << 4) /* B-PSK coded modulation */
Arthrik 0:e88514a784bb 172 #define ST7580_MOD_QPSK_COD (5 << 4) /* Q-PSK coded modulation */
Arthrik 0:e88514a784bb 173 #define ST7580_MOD_BPSK_COD_PNA (7 << 4) /* B-PSK coded with Peak \
Arthrik 0:e88514a784bb 174 Noise Avoidance modulation */
Arthrik 1:edbcde816013 175 #define ST7580_ZC (1 << 7) /* Zero crossing synchronization */