pn512_registers.h

00001 /*
00002   pn512_registers.h
00003   Copyright (c) Donatien Garnier 2012
00004   donatien.garnier@appnearme.com
00005   http://www.appnearme.com/
00006 */
00007 
00008 #ifndef PN512_REGISTERS_H_
00009 #define PN512_REGISTERS_H_
00010 
00011 #ifdef __cplusplus
00012 extern "C" {
00013 #endif
00014 
00015 //Page 0 - Command and Status
00016 #define PN512_REG_PAGE 0x00 //Selects the register page
00017 #define PN512_REG_COMMAND 0x01 //Starts and stops command execution
00018 #define PN512_REG_COMIEN 0x02 //Controls bits to enable and disable the passing of Interrupt Requests
00019 #define PN512_REG_DIVIEN 0x03 //Controls bits to enable and disable the passing of Interrupt Requests
00020 #define PN512_REG_COMIRQ 0x04 //Contains Interrupt Request bits
00021 #define PN512_REG_DIVIRQ 0x05 //Contains Interrupt Request bits
00022 #define PN512_REG_ERROR 0x06 //Error bits showing the error status of the last command executed
00023 #define PN512_REG_STATUS1 0x07 //Contains status bits for communication
00024 #define PN512_REG_STATUS2 0x08 //Contains status bits of the receiver and transmitter
00025 #define PN512_REG_FIFODATA 0x09 //In- and output of 64 byte FIFO-buffer
00026 #define PN512_REG_FIFOLEVEL 0x0A //Indicates the number of bytes stored in the FIFO
00027 #define PN512_REG_WATERLEVEL 0x0B //Defines the level for FIFO under- and overflow warning
00028 #define PN512_REG_CONTROL 0x0C //Contains miscellaneous Control Registers
00029 #define PN512_REG_BITFRAMING 0x0D //Adjustments for bit oriented frames
00030 #define PN512_REG_COLL 0x0E //Bit position of the first bit collision detected on the RF-interface
00031 
00032 //Page 1 - Command
00033 //#define PN512_REG_PAGE 0x10 //Selects the register page
00034 #define PN512_REG_MODE 0x11 //Defines general modes for transmitting and receiving
00035 #define PN512_REG_TXMODE 0x12 //Defines the data rate and framing during transmission
00036 #define PN512_REG_RXMODE 0x13 //Defines the data rate and framing during receiving
00037 #define PN512_REG_TXCONTROL 0x14 //Controls the logical behavior of the antenna driver pins TX1 and TX2
00038 #define PN512_REG_TXAUTO 0x15 //Controls the setting of the antenna drivers
00039 #define PN512_REG_TXSEL 0x16 //Selects the internal sources for the antenna driver
00040 #define PN512_REG_RXSEL 0x17 //Selects internal receiver settings
00041 #define PN512_REG_RXTHRESHOLD 0x18 //Selects thresholds for the bit decoder
00042 #define PN512_REG_DEMOD 0x19 //Defines demodulator settings
00043 #define PN512_REG_FELNFC1 0x1A //Defines the length of the valid range for the receive package
00044 #define PN512_REG_FELNFC2 0x1B //Defines the length of the valid range for the receive package
00045 #define PN512_REG_MIFNFC 0x1C //Controls the communication in ISO/IEC 14443/MIFARE and NFC target mode at 106 kbit
00046 #define PN512_REG_MANUALRCV 0x1D //Allows manual fine tuning of the internal receiver
00047 #define PN512_REG_TYPEB 0x1E //Configure the ISO/IEC 14443 type B
00048 #define PN512_REG_SERIALSPEED 0x1F //Selects the speed of the serial UART interface
00049 
00050 //Page 2 - CFG
00051 //#define PN512_REG_PAGE 0x20 //Selects the register page
00052 #define PN512_REG_CRCRESULT 0x21 //Shows the actual MSB and LSB values of the CRC calculation
00053 #define PN512_REG_GSNOFF 0x23 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation, when the driver is switched off
00054 #define PN512_REG_MODWIDTH 0x24 //Controls the setting of the ModWidth
00055 #define PN512_REG_TXBITPHASE 0x25 //Adjust the TX bit phase at 106 kbit
00056 #define PN512_REG_RFCFG 0x26 //Configures the receiver gain and RF level
00057 #define PN512_REG_GSNON 0x27 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation when the drivers are switched on
00058 #define PN512_REG_CWGSP 0x28 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during times of no modulation
00059 #define PN512_REG_MODGSP 0x29 //Selects the conductance of the antenna driver pins TX1 and TX2 for modulation during modulation
00060 #define PN512_REG_TMODE_TPRESCALERHIGH 0x2A //Defines settings for the internal timer
00061 #define PN512_REG_TPRESCALERLOW 0x2B //Defines settings for the internal timer
00062 #define PN512_REG_TRELOADHIGH 0x2C //Describes the 16-bit timer reload value
00063 #define PN512_REG_TRELOADLOW 0x2D //Describes the 16-bit timer reload value
00064 #define PN512_REG_TCOUNTERVALHIGH 0x2E //Shows the 16-bit actual timer value
00065 #define PN512_REG_TCOUNTERVALLOW 0x2F //Shows the 16-bit actual timer value
00066 
00067 //Page 3 - TestRegister
00068 //#define PN512_REG_PAGE 0x30 //Selects the register page
00069 #define PN512_REG_TESTSEL1 0x31 //General test signal configuration
00070 #define PN512_REG_TESTSEL2 0x32 //General test signal configuration and PRBS control
00071 #define PN512_REG_TESTPINEN 0x33 //Enables pin output driver on 8-bit parallel bus (Note: For serial interfaces only)
00072 #define PN512_REG_TESTPINVALUE 0x34 //Defines the values for the 8-bit parallel bus when it is used as I/O bus
00073 #define PN512_REG_TESTBUS 0x35 //Shows the status of the internal testbus
00074 #define PN512_REG_AUTOTEST 0x36 //Controls the digital selftest
00075 #define PN512_REG_VERSION 0x37 //Shows the version
00076 #define PN512_REG_ANALOGTEST 0x38 //Controls the pins AUX1 and AUX2
00077 #define PN512_REG_TESTDAC1 0x39 //Defines the test value for the TestDAC1
00078 #define PN512_REG_TESTDAC2 0x3A //Defines the test value for the TestDAC2
00079 #define PN512_REG_TESTADC 0x3B //Shows the actual value of ADC I and Q
00080 
00081 
00082 void pn512_registers_init(void);
00083 
00084 void pn512_register_write(uint8_t address, uint8_t data);
00085 uint8_t pn512_register_read(uint8_t address);
00086 
00087 #ifdef __cplusplus
00088 }
00089 #endif
00090 
00091 #endif /* PN512_REGISTERS_H_ */