Robert Bolling / FXOS8700CQ

minor changes to support mobile life IoT project

Fork of FXOS8700CQ by Thomas Murphy

FXOS8700CQ.cpp@5:fb4cef1399b8, 2017-02-09 (annotated)

Committer:
Anubus
Date:
Thu Feb 09 00:42:50 2017 +0000
Revision:
5:fb4cef1399b8
Parent:
3:2ce85aa45d7d 
changes to the AVNET_ATT_Cellular_IOT project to support GPS, Si7021, and voltage monitoring.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anubus 5:fb4cef1399b8 1 // Accelerometer on the mbed board
trm 0:cf6299acfe98 2 #include "FXOS8700CQ.h"
trm 0:cf6299acfe98 3
trm 0:cf6299acfe98 4 uint8_t status_reg; // Status register contents
trm 0:cf6299acfe98 5 uint8_t raw[FXOS8700CQ_READ_LEN]; // Buffer for reading out stored data
trm 0:cf6299acfe98 6
trm 0:cf6299acfe98 7 // Construct class and its contents
trm 0:cf6299acfe98 8 FXOS8700CQ::FXOS8700CQ(PinName sda, PinName scl, int addr) : dev_i2c(sda, scl), dev_addr(addr)
trm 0:cf6299acfe98 9 {
trm 0:cf6299acfe98 10 // Initialization of the FXOS8700CQ
trm 0:cf6299acfe98 11 dev_i2c.frequency(I2C_400K); // Use maximum I2C frequency
trm 3:2ce85aa45d7d 12 uint8_t data[6] = {0, 0, 0, 0, 0, 0}; // to write over I2C: device register, up to 5 bytes data
trm 0:cf6299acfe98 13
trm 0:cf6299acfe98 14 // TODO: verify WHOAMI?
trm 2:4c2f8a3549a9 15
trm 0:cf6299acfe98 16 // Place peripheral in standby for configuration, resetting CTRL_REG1
trm 0:cf6299acfe98 17 data[0] = FXOS8700CQ_CTRL_REG1;
trm 2:4c2f8a3549a9 18 data[1] = 0x00; // this will unset CTRL_REG1:active
trm 0:cf6299acfe98 19 write_regs(data, 2);
trm 0:cf6299acfe98 20
trm 3:2ce85aa45d7d 21 // Now that the device is in standby, configure registers at will
trm 0:cf6299acfe98 22
trm 0:cf6299acfe98 23 // Setup for write-though for CTRL_REG series
trm 0:cf6299acfe98 24 // Keep data[0] as FXOS8700CQ_CTRL_REG1
trm 2:4c2f8a3549a9 25 data[1] =
trm 2:4c2f8a3549a9 26 FXOS8700CQ_CTRL_REG1_ASLP_RATE2(1) | // 0b01 gives sleep rate of 12.5Hz
trm 2:4c2f8a3549a9 27 FXOS8700CQ_CTRL_REG1_DR3(1); // 0x001 gives ODR of 400Hz/200Hz hybrid
trm 0:cf6299acfe98 28
trm 0:cf6299acfe98 29 // FXOS8700CQ_CTRL_REG2;
trm 2:4c2f8a3549a9 30 data[2] =
trm 2:4c2f8a3549a9 31 FXOS8700CQ_CTRL_REG2_SMODS2(3) | // 0b11 gives low power sleep oversampling mode
trm 2:4c2f8a3549a9 32 FXOS8700CQ_CTRL_REG2_MODS2(1); // 0b01 gives low noise, low power oversampling mode
trm 0:cf6299acfe98 33
trm 0:cf6299acfe98 34 // No configuration changes from default 0x00 in CTRL_REG3
trm 3:2ce85aa45d7d 35 // Interrupts will be active low, their outputs in push-pull mode
trm 0:cf6299acfe98 36 data[3] = 0x00;
trm 0:cf6299acfe98 37
trm 0:cf6299acfe98 38 // FXOS8700CQ_CTRL_REG4;
trm 2:4c2f8a3549a9 39 data[4] =
trm 3:2ce85aa45d7d 40 FXOS8700CQ_CTRL_REG4_INT_EN_DRDY; // Enable the Data-Ready interrupt
trm 0:cf6299acfe98 41
trm 0:cf6299acfe98 42 // No configuration changes from default 0x00 in CTRL_REG5
trm 3:2ce85aa45d7d 43 // Data-Ready interrupt will appear on INT2
trm 0:cf6299acfe98 44 data[5] = 0x00;
trm 0:cf6299acfe98 45
trm 0:cf6299acfe98 46 // Write to the 5 CTRL_REG registers
trm 0:cf6299acfe98 47 write_regs(data, 6);
trm 0:cf6299acfe98 48
trm 2:4c2f8a3549a9 49 // FXOS8700CQ_XYZ_DATA_CFG
trm 2:4c2f8a3549a9 50 data[0] = FXOS8700CQ_XYZ_DATA_CFG;
trm 2:4c2f8a3549a9 51 data[1] =
trm 2:4c2f8a3549a9 52 FXOS8700CQ_XYZ_DATA_CFG_FS2(1); // 0x01 gives 4g full range, 0.488mg/LSB
trm 2:4c2f8a3549a9 53 write_regs(data, 2);
trm 0:cf6299acfe98 54
trm 0:cf6299acfe98 55 // Setup for write-through for M_CTRL_REG series
trm 0:cf6299acfe98 56 data[0] = FXOS8700CQ_M_CTRL_REG1;
trm 2:4c2f8a3549a9 57 data[1] =
trm 2:4c2f8a3549a9 58 FXOS8700CQ_M_CTRL_REG1_M_ACAL | // set automatic calibration
trm 2:4c2f8a3549a9 59 FXOS8700CQ_M_CTRL_REG1_MO_OS3(7) | // use maximum magnetic oversampling
trm 2:4c2f8a3549a9 60 FXOS8700CQ_M_CTRL_REG1_M_HMS2(3); // enable hybrid sampling (both sensors)
trm 0:cf6299acfe98 61
trm 0:cf6299acfe98 62 // FXOS8700CQ_M_CTRL_REG2
trm 2:4c2f8a3549a9 63 data[2] =
trm 2:4c2f8a3549a9 64 FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE;
trm 0:cf6299acfe98 65
trm 0:cf6299acfe98 66 // FXOS8700CQ_M_CTRL_REG3
trm 2:4c2f8a3549a9 67 data[3] =
trm 2:4c2f8a3549a9 68 FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(7); // maximum sleep magnetic oversampling
trm 0:cf6299acfe98 69
trm 0:cf6299acfe98 70 // Write to the 3 M_CTRL_REG registers
trm 0:cf6299acfe98 71 write_regs(data, 4);
trm 0:cf6299acfe98 72
trm 0:cf6299acfe98 73 // Peripheral is configured, but disabled
trm 2:4c2f8a3549a9 74 enabled = false;
trm 0:cf6299acfe98 75 }
trm 0:cf6299acfe98 76
trm 0:cf6299acfe98 77 // Destruct class
trm 0:cf6299acfe98 78 FXOS8700CQ::~FXOS8700CQ(void) {}
trm 0:cf6299acfe98 79
trm 0:cf6299acfe98 80
trm 0:cf6299acfe98 81 void FXOS8700CQ::enable(void)
trm 0:cf6299acfe98 82 {
trm 0:cf6299acfe98 83 uint8_t data[2];
trm 0:cf6299acfe98 84 read_regs( FXOS8700CQ_CTRL_REG1, &data[1], 1);
trm 2:4c2f8a3549a9 85 data[1] |= FXOS8700CQ_CTRL_REG1_ACTIVE;
trm 0:cf6299acfe98 86 data[0] = FXOS8700CQ_CTRL_REG1;
trm 0:cf6299acfe98 87 write_regs(data, 2); // write back
trm 2:4c2f8a3549a9 88
trm 2:4c2f8a3549a9 89 enabled = true;
trm 0:cf6299acfe98 90 }
trm 0:cf6299acfe98 91
trm 0:cf6299acfe98 92 void FXOS8700CQ::disable(void)
trm 0:cf6299acfe98 93 {
trm 0:cf6299acfe98 94 uint8_t data[2];
trm 0:cf6299acfe98 95 read_regs( FXOS8700CQ_CTRL_REG1, &data[1], 1);
trm 0:cf6299acfe98 96 data[0] = FXOS8700CQ_CTRL_REG1;
trm 2:4c2f8a3549a9 97 data[1] &= ~FXOS8700CQ_CTRL_REG1_ACTIVE;
trm 0:cf6299acfe98 98 write_regs(data, 2); // write back
trm 2:4c2f8a3549a9 99
trm 2:4c2f8a3549a9 100 enabled = false;
trm 0:cf6299acfe98 101 }
trm 0:cf6299acfe98 102
trm 0:cf6299acfe98 103
trm 0:cf6299acfe98 104 uint8_t FXOS8700CQ::status(void)
trm 0:cf6299acfe98 105 {
trm 0:cf6299acfe98 106 read_regs(FXOS8700CQ_STATUS, &status_reg, 1);
trm 0:cf6299acfe98 107 return status_reg;
trm 0:cf6299acfe98 108 }
trm 0:cf6299acfe98 109
trm 0:cf6299acfe98 110 uint8_t FXOS8700CQ::get_whoami(void)
trm 0:cf6299acfe98 111 {
trm 0:cf6299acfe98 112 uint8_t databyte = 0x00;
trm 0:cf6299acfe98 113 read_regs(FXOS8700CQ_WHOAMI, &databyte, 1);
trm 0:cf6299acfe98 114 return databyte;
trm 0:cf6299acfe98 115 }
trm 0:cf6299acfe98 116
trm 2:4c2f8a3549a9 117 uint8_t FXOS8700CQ::get_data(SRAWDATA *accel_data, SRAWDATA *magn_data)
trm 0:cf6299acfe98 118 {
trm 2:4c2f8a3549a9 119 if(!enabled) {
trm 2:4c2f8a3549a9 120 return 1;
trm 2:4c2f8a3549a9 121 }
trm 2:4c2f8a3549a9 122
trm 2:4c2f8a3549a9 123 read_regs(FXOS8700CQ_M_OUT_X_MSB, raw, FXOS8700CQ_READ_LEN);
trm 0:cf6299acfe98 124
trm 0:cf6299acfe98 125 // Pull out 16-bit, 2's complement magnetometer data
trm 0:cf6299acfe98 126 magn_data->x = (raw[0] << 8) | raw[1];
trm 0:cf6299acfe98 127 magn_data->y = (raw[2] << 8) | raw[3];
trm 0:cf6299acfe98 128 magn_data->z = (raw[4] << 8) | raw[5];
trm 0:cf6299acfe98 129
trm 0:cf6299acfe98 130 // Pull out 14-bit, 2's complement, right-justified accelerometer data
trm 0:cf6299acfe98 131 accel_data->x = (raw[6] << 8) | raw[7];
trm 0:cf6299acfe98 132 accel_data->y = (raw[8] << 8) | raw[9];
trm 0:cf6299acfe98 133 accel_data->z = (raw[10] << 8) | raw[11];
trm 2:4c2f8a3549a9 134
trm 2:4c2f8a3549a9 135 // Have to apply corrections to make the int16_t correct
trm 2:4c2f8a3549a9 136 if(accel_data->x > UINT14_MAX/2) {
trm 2:4c2f8a3549a9 137 accel_data->x -= UINT14_MAX;
trm 2:4c2f8a3549a9 138 }
trm 2:4c2f8a3549a9 139 if(accel_data->y > UINT14_MAX/2) {
trm 2:4c2f8a3549a9 140 accel_data->y -= UINT14_MAX;
trm 2:4c2f8a3549a9 141 }
trm 2:4c2f8a3549a9 142 if(accel_data->z > UINT14_MAX/2) {
trm 2:4c2f8a3549a9 143 accel_data->z -= UINT14_MAX;
trm 2:4c2f8a3549a9 144 }
trm 2:4c2f8a3549a9 145
trm 2:4c2f8a3549a9 146 return 0;
trm 0:cf6299acfe98 147 }
trm 0:cf6299acfe98 148
trm 2:4c2f8a3549a9 149 uint8_t FXOS8700CQ::get_accel_scale(void)
trm 2:4c2f8a3549a9 150 {
trm 2:4c2f8a3549a9 151 uint8_t data = 0x00;
trm 2:4c2f8a3549a9 152 read_regs(FXOS8700CQ_XYZ_DATA_CFG, &data, 1);
trm 2:4c2f8a3549a9 153 data &= FXOS8700CQ_XYZ_DATA_CFG_FS2(3); // mask with 0b11
trm 2:4c2f8a3549a9 154
trm 3:2ce85aa45d7d 155 // Choose output value based on masked data
trm 2:4c2f8a3549a9 156 switch(data) {
trm 2:4c2f8a3549a9 157 case FXOS8700CQ_XYZ_DATA_CFG_FS2(0):
trm 2:4c2f8a3549a9 158 return 2;
trm 2:4c2f8a3549a9 159 case FXOS8700CQ_XYZ_DATA_CFG_FS2(1):
trm 2:4c2f8a3549a9 160 return 4;
trm 2:4c2f8a3549a9 161 case FXOS8700CQ_XYZ_DATA_CFG_FS2(2):
trm 2:4c2f8a3549a9 162 return 8;
trm 2:4c2f8a3549a9 163 default:
trm 2:4c2f8a3549a9 164 return 0;
trm 2:4c2f8a3549a9 165 }
trm 2:4c2f8a3549a9 166 }
trm 0:cf6299acfe98 167
trm 0:cf6299acfe98 168 // Private methods
trm 0:cf6299acfe98 169
trm 3:2ce85aa45d7d 170 // Excepting the call to dev_i2c.frequency() in the constructor,
trm 3:2ce85aa45d7d 171 // the use of the mbed I2C class is restricted to these methods
trm 0:cf6299acfe98 172 void FXOS8700CQ::read_regs(int reg_addr, uint8_t* data, int len)
trm 0:cf6299acfe98 173 {
trm 0:cf6299acfe98 174 char t[1] = {reg_addr};
trm 0:cf6299acfe98 175 dev_i2c.write(dev_addr, t, 1, true);
trm 0:cf6299acfe98 176 dev_i2c.read(dev_addr, (char *)data, len);
trm 0:cf6299acfe98 177 }
trm 0:cf6299acfe98 178
trm 0:cf6299acfe98 179 void FXOS8700CQ::write_regs(uint8_t* data, int len)
trm 0:cf6299acfe98 180 {
trm 0:cf6299acfe98 181 dev_i2c.write(dev_addr, (char*)data, len);
trm 0:cf6299acfe98 182 }