Revision 18:6c2ce1749d4a, committed 2017-11-13
- Comitter:
- AndyA
- Date:
- Mon Nov 13 14:29:41 2017 +0000
- Parent:
- 17:1fb08dfef237
- Commit message:
- Auto apply crystal trim on startup
Changed in this revision
diff -r 1fb08dfef237 -r 6c2ce1749d4a DW1000.cpp
--- a/DW1000.cpp Wed Nov 08 11:15:47 2017 +0000
+++ b/DW1000.cpp Mon Nov 13 14:29:41 2017 +0000
@@ -19,29 +19,31 @@
}
-void DW1000::setSPISpeed(uint32_t speed) {
+void DW1000::setSPISpeed(uint32_t speed)
+{
spi.frequency(speed);
- }
+}
-void DW1000::enterRFTestMode() {
- writeRegister32(DW1000_RF_CONF,0,0x0009A000);
- wait_ms(1);
- writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL1,0x0000);
- wait_ms(1);
- writeRegister32(DW1000_TX_POWER,0,0x1f1f1f1f);
- wait_ms(1);
- uint32_t config = readRegister32(DW1000_SYS_CFG,0);
- config |= 1<<18;
- writeRegister32(DW1000_SYS_CFG,0,config);
- wait_ms(1);
- writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL0,0x0222);
- wait_ms(1);
- writeRegister32(DW1000_PMSC,DWPMSC_PMSC_TXFSEQ,0x00000000);
- wait_ms(1);
- writeRegister32(DW1000_RF_CONF,0,0x005fff00);
- wait_ms(1);
- writeRegister8(DW1000_TX_CAL,DWTXCAL_TC_PGTEST,0x13);
+void DW1000::enterRFTestMode()
+{
+ writeRegister32(DW1000_RF_CONF,0,0x0009A000);
+ wait_ms(1);
+ writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL1,0x0000);
+ wait_ms(1);
+ writeRegister32(DW1000_TX_POWER,0,0x1f1f1f1f);
+ wait_ms(1);
+ uint32_t config = readRegister32(DW1000_SYS_CFG,0);
+ config |= 1<<18;
+ writeRegister32(DW1000_SYS_CFG,0,config);
+ wait_ms(1);
+ writeRegister16(DW1000_PMSC,DWPMSC_PMSC_CTRL0,0x0222);
+ wait_ms(1);
+ writeRegister32(DW1000_PMSC,DWPMSC_PMSC_TXFSEQ,0x00000000);
+ wait_ms(1);
+ writeRegister32(DW1000_RF_CONF,0,0x005fff00);
+ wait_ms(1);
+ writeRegister8(DW1000_TX_CAL,DWTXCAL_TC_PGTEST,0x13);
}
@@ -68,6 +70,7 @@
stopTRX();
resetAll(); // we do a soft reset of the DW1000 to get to a known state. Without this we lose comms.
+ setupXtalTrim();
setupAGC();
setupRxConfig();
setupLDE();
@@ -83,6 +86,14 @@
irq.rise(this, &DW1000::ISR); // attach interrupt handler to rising edge of interrupt pin from DW1000
}
+void DW1000::setupXtalTrim()
+{
+ uint32_t xtal = readOTP(0x1E) & 0x0ff;
+ if (xtal == 0)
+ xtal=0x0f; // assume that crystal trim value hasn't been set rather than being right on the limit.
+ setXTALTune(xtal);
+}
+
void DW1000::setupGPIO()
{
@@ -359,15 +370,17 @@
writeRegister32(DW1000_CHAN_CTRL, 0, registerValue);
}
-uint8_t DW1000::readXTALTune() {
- return readRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT);
- }
+uint8_t DW1000::readXTALTune()
+{
+ return readRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT);
+}
-void DW1000::setXTALTune(uint8_t value) {
- value &= 0x1f; // mask reserved bits
- value |= 0x60; // set reserved bits
- writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT,value);
- }
+void DW1000::setXTALTune(uint8_t value)
+{
+ value &= 0x1f; // mask reserved bits
+ value |= 0x60; // set reserved bits
+ writeRegister8 (DW1000_FS_CTRL, DWFSCTRL_FS_XTALT,value);
+}
uint8_t DW1000::powerToRegValue(float powerdB)
{
@@ -1089,7 +1102,7 @@
*delta = data >> 24 & 0x0ff;
int32_t RXTofs = data &0x07ffff;
if (RXTofs & 0x040000)
- RXTofs |= 0xfff80000;
+ RXTofs |= 0xfff80000;
*offset = RXTofs;
// uint32_t RXTTCKI = 0x01FC0000;
diff -r 1fb08dfef237 -r 6c2ce1749d4a DW1000.h
--- a/DW1000.h Wed Nov 08 11:15:47 2017 +0000
+++ b/DW1000.h Mon Nov 13 14:29:41 2017 +0000
@@ -390,7 +390,8 @@
void setupTxCalibration();
void setupSystemConfig();
void setupPower();
-
+ void setupXtalTrim();
+
void loadLDE(); // load the leading edge detection algorithm to RAM, [IMPORTANT because receiving malfunction may occur] see User Manual LDELOAD on p22 & p158
void loadLDOTUNE(); // load the LDO tuning as set in the factory
diff -r 1fb08dfef237 -r 6c2ce1749d4a DW1000Setup.h
--- a/DW1000Setup.h Wed Nov 08 11:15:47 2017 +0000
+++ b/DW1000Setup.h Mon Nov 13 14:29:41 2017 +0000
@@ -18,7 +18,7 @@
* enum for preset mode combinations
*/
typedef enum {fastLocationC5, ///< maximum data speed, short range. Channel 5
- fastLocationC4, ///< maximum data speed, short range. Channel 5
+ fastLocationC4, ///< maximum data speed, short range. Channel 4
tunedDefault, ///< The power up default config with the recomended changes
user110k, ///< 110kb/s settings used by Matthias Grob & Manuel Stalder
rangeRateCompromise ///< 850kb/s settings aimed to give a short packet but with far greater range than the fastLocation options