Simple mbed library with macros
Dependents: SimpleTimer SimpleUART SimpleTimer Stoppuhr1
mbed_globals.h@1:1033948951f0, 2010-11-08 (annotated)
- Committer:
- Alkorin
- Date:
- Mon Nov 08 10:32:34 2010 +0000
- Revision:
- 1:1033948951f0
- Parent:
- 0:aa3c3d1a5918
- Child:
- 2:e6b2d22fbf75
Added Peripheral memory map
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Alkorin | 0:aa3c3d1a5918 | 1 | #ifndef __MBED_GLOBALS_H__ |
Alkorin | 0:aa3c3d1a5918 | 2 | #define __MBED_GLOBALS_H__ |
Alkorin | 0:aa3c3d1a5918 | 3 | |
Alkorin | 0:aa3c3d1a5918 | 4 | /* GLOBALS MACRO */ |
Alkorin | 0:aa3c3d1a5918 | 5 | #define GET_REGISTER8(reg) *(volatile uint8_t *)(reg) |
Alkorin | 0:aa3c3d1a5918 | 6 | #define GET_REGISTER16(reg) *(volatile uint16_t *)(reg) |
Alkorin | 0:aa3c3d1a5918 | 7 | #define GET_REGISTER32(reg) *(volatile uint32_t *)(reg) |
Alkorin | 0:aa3c3d1a5918 | 8 | |
Alkorin | 0:aa3c3d1a5918 | 9 | #define SET_REGISTER8(reg, val) *(uint8_t *)(reg)=(val) |
Alkorin | 0:aa3c3d1a5918 | 10 | #define SET_REGISTER16(reg, val) *(uint16_t *)(reg)=(val) |
Alkorin | 0:aa3c3d1a5918 | 11 | #define SET_REGISTER32(reg, val) *(uint32_t *)(reg)=(val) |
Alkorin | 0:aa3c3d1a5918 | 12 | |
Alkorin | 0:aa3c3d1a5918 | 13 | // See 34.3.2.5 p740 |
Alkorin | 0:aa3c3d1a5918 | 14 | #define BIT_BANDING_ADDRESS(reg, bit) (((reg) & 0xF0000000) | (0x02000000) | (((reg) & 0x000FFFFF) << 5) | ((bit) << 2)) |
Alkorin | 0:aa3c3d1a5918 | 15 | #define GET_BIT_VALUE(reg, bit) GET_REGISTER32(BIT_BANDING_ADDRESS(reg, bit)) |
Alkorin | 0:aa3c3d1a5918 | 16 | |
Alkorin | 1:1033948951f0 | 17 | |
Alkorin | 1:1033948951f0 | 18 | /******************************************************************************/ |
Alkorin | 1:1033948951f0 | 19 | /* Peripheral memory map */ |
Alkorin | 1:1033948951f0 | 20 | /******************************************************************************/ |
Alkorin | 1:1033948951f0 | 21 | /* Base addresses */ |
Alkorin | 1:1033948951f0 | 22 | #define LPC_FLASH_BASE (0x00000000UL) |
Alkorin | 1:1033948951f0 | 23 | #define LPC_RAM_BASE (0x10000000UL) |
Alkorin | 1:1033948951f0 | 24 | #define LPC_GPIO_BASE (0x2009C000UL) |
Alkorin | 1:1033948951f0 | 25 | #define LPC_APB0_BASE (0x40000000UL) |
Alkorin | 1:1033948951f0 | 26 | #define LPC_APB1_BASE (0x40080000UL) |
Alkorin | 1:1033948951f0 | 27 | #define LPC_AHB_BASE (0x50000000UL) |
Alkorin | 1:1033948951f0 | 28 | #define LPC_CM3_BASE (0xE0000000UL) |
Alkorin | 1:1033948951f0 | 29 | |
Alkorin | 1:1033948951f0 | 30 | /* APB0 peripherals */ |
Alkorin | 1:1033948951f0 | 31 | #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) |
Alkorin | 1:1033948951f0 | 32 | #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) |
Alkorin | 1:1033948951f0 | 33 | #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) |
Alkorin | 1:1033948951f0 | 34 | #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) |
Alkorin | 1:1033948951f0 | 35 | #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) |
Alkorin | 1:1033948951f0 | 36 | #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) |
Alkorin | 1:1033948951f0 | 37 | #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) |
Alkorin | 1:1033948951f0 | 38 | #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) |
Alkorin | 1:1033948951f0 | 39 | #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) |
Alkorin | 1:1033948951f0 | 40 | #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) |
Alkorin | 1:1033948951f0 | 41 | #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) |
Alkorin | 1:1033948951f0 | 42 | #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) |
Alkorin | 1:1033948951f0 | 43 | #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) |
Alkorin | 1:1033948951f0 | 44 | #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) |
Alkorin | 1:1033948951f0 | 45 | #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) |
Alkorin | 1:1033948951f0 | 46 | #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) |
Alkorin | 1:1033948951f0 | 47 | #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) |
Alkorin | 1:1033948951f0 | 48 | #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) |
Alkorin | 1:1033948951f0 | 49 | #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) |
Alkorin | 1:1033948951f0 | 50 | |
Alkorin | 1:1033948951f0 | 51 | /* APB1 peripherals */ |
Alkorin | 1:1033948951f0 | 52 | #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) |
Alkorin | 1:1033948951f0 | 53 | #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) |
Alkorin | 1:1033948951f0 | 54 | #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) |
Alkorin | 1:1033948951f0 | 55 | #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) |
Alkorin | 1:1033948951f0 | 56 | #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) |
Alkorin | 1:1033948951f0 | 57 | #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) |
Alkorin | 1:1033948951f0 | 58 | #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) |
Alkorin | 1:1033948951f0 | 59 | #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) |
Alkorin | 1:1033948951f0 | 60 | #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) |
Alkorin | 1:1033948951f0 | 61 | #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) |
Alkorin | 1:1033948951f0 | 62 | #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) |
Alkorin | 1:1033948951f0 | 63 | #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) |
Alkorin | 1:1033948951f0 | 64 | |
Alkorin | 1:1033948951f0 | 65 | /* AHB peripherals */ |
Alkorin | 1:1033948951f0 | 66 | #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) |
Alkorin | 1:1033948951f0 | 67 | #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) |
Alkorin | 1:1033948951f0 | 68 | #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) |
Alkorin | 1:1033948951f0 | 69 | #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) |
Alkorin | 1:1033948951f0 | 70 | #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) |
Alkorin | 1:1033948951f0 | 71 | #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) |
Alkorin | 1:1033948951f0 | 72 | #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) |
Alkorin | 1:1033948951f0 | 73 | #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) |
Alkorin | 1:1033948951f0 | 74 | #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) |
Alkorin | 1:1033948951f0 | 75 | #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) |
Alkorin | 1:1033948951f0 | 76 | #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) |
Alkorin | 1:1033948951f0 | 77 | |
Alkorin | 1:1033948951f0 | 78 | /* GPIOs */ |
Alkorin | 1:1033948951f0 | 79 | #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) |
Alkorin | 1:1033948951f0 | 80 | #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) |
Alkorin | 1:1033948951f0 | 81 | #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) |
Alkorin | 1:1033948951f0 | 82 | #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) |
Alkorin | 1:1033948951f0 | 83 | #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) |
Alkorin | 1:1033948951f0 | 84 | |
Alkorin | 0:aa3c3d1a5918 | 85 | #endif |