Diff: kl25z_clock.cpp

Revision:

1:1097467b4352

Parent:

0:218e465e76b6

Child:

3:99e9aaefc9f6

--- a/kl25z_clock.cpp	Thu Aug 14 23:34:18 2014 +0000
+++ b/kl25z_clock.cpp	Tue Sep 02 23:54:32 2014 +0000
@@ -2,6 +2,7 @@
 #include "MKL25Z4.h"
 
 #include "kl25z_clock.h"
+#include "board.h"
 
 void switchFEItoPEE( void )
 {
@@ -49,13 +50,63 @@
  
 void switchPEEtoBLPI( void )
 {
-    MCG->C1 = (uint8_t)0x90U;
+    
+    
+    // Move to PBE
+    MCG->C1 = (uint8_t)0x90U;                       /* Switch the system clock source to the external reference clock */
+    while((MCG->S & MCG_S_CLKST_MASK) != 0x2U<<MCG_S_CLKST_SHIFT) {   /* Wait until external reference clock is selected as MCG output */
+    }
+    
+    
+    // Move to FBE
+    MCG->C6 = (uint8_t)0x00U;                       /* Select FLL */
+    while((MCG->S & MCG_S_PLLST_MASK) != 0x00U) {   /* Wait until the current source for the PLLS clock is the FLL */
+    }
+    
+    // Ok till here
+    
+    // Move to FBI
+    MCG->C1 = (uint8_t)0x54U;                       /* Switch the system clock to the internal reference clock */
+    while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {   /* Wait until the current source for the PLLS clock is the FLL */
+    }
+    while((MCG->S & MCG_S_CLKST_MASK) != 0x1U << MCG_S_CLKST_SHIFT) {   /* Wait until the the internal reference clock is selected to feed MCGOUTCLK */
+    }
+    
+    // Move to BLPI
+    MCG->C2 = (uint8_t)0x02;                     /* LP is 1 */
+    MCG->C1 |= MCG_C1_IRCLKEN_MASK;              /* Clock is always active */
+    
+    /* Run this to get the new system frequency */
+    //SystemCoreClockUpdate();
+    
+}
+
+void switchBLPItoFEI( void )
+{
+    // Move to FBI
+    /* LP is 0 */
+    MCG->C2 = (uint8_t) 0x00;                     
+    
+    // Move to FEI
+    /* Update system prescalers */
+    SIM->CLKDIV1 = (uint32_t)0x00020000UL;          
+    /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+    MCG->C1 = (uint8_t)0x06U;
+    /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+    MCG->C2 = (uint8_t)0x00U;
+    /* MCG->C4: DMX32=0,DRST_DRS=1 */
+    MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+    /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+    OSC0->CR = (uint8_t)0x80U;
+    /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+    MCG->C5 = (uint8_t)0x00U;
+    /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+    MCG->C6 = (uint8_t)0x00U;
+    while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+    }
+    while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
+    } 
     
     /* Run this to get the new system frequency */
     SystemCoreClockUpdate();
-}
- 
-void switchBLPItoPEE( void )
-{
-    
 }
\ No newline at end of file