Alfredo Espinoza Rhoton / KL25Z_ClockControl

Library to control the KL25z Clock Module.

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kl25z_clock.cpp@1:1097467b4352, 2014-09-02 (annotated)

Committer:
AlfredoER
Date:
Tue Sep 02 23:54:32 2014 +0000
Revision:
1:1097467b4352
Parent:
0:218e465e76b6
Child:
3:99e9aaefc9f6
-Completed FEI to PEE, PEE to BLPI and BLPI to FEI transitions. Tested on FRDM KL25z working.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AlfredoER 0:218e465e76b6 1 #include <stdint.h>
AlfredoER 0:218e465e76b6 2 #include "MKL25Z4.h"
AlfredoER 0:218e465e76b6 3
AlfredoER 0:218e465e76b6 4 #include "kl25z_clock.h"
AlfredoER 1:1097467b4352 5 #include "board.h"
AlfredoER 0:218e465e76b6 6
AlfredoER 0:218e465e76b6 7 void switchFEItoPEE( void )
AlfredoER 0:218e465e76b6 8 {
AlfredoER 0:218e465e76b6 9 /* SIM->SCGC5: PORTA=1 */
AlfredoER 0:218e465e76b6 10 SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
AlfredoER 0:218e465e76b6 11 /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
AlfredoER 0:218e465e76b6 12 SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
AlfredoER 0:218e465e76b6 13 /* PORTA->PCR18: ISF=0,MUX=0 */
AlfredoER 0:218e465e76b6 14 PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
AlfredoER 0:218e465e76b6 15 /* PORTA->PCR19: ISF=0,MUX=0 */
AlfredoER 0:218e465e76b6 16 PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
AlfredoER 0:218e465e76b6 17 /* Switch to FBE Mode */
AlfredoER 0:218e465e76b6 18 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
AlfredoER 0:218e465e76b6 19 OSC0->CR = (uint8_t)0x89U;
AlfredoER 0:218e465e76b6 20 /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
AlfredoER 0:218e465e76b6 21 MCG->C2 = (uint8_t)0x24U;
AlfredoER 0:218e465e76b6 22 /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
AlfredoER 0:218e465e76b6 23 MCG->C1 = (uint8_t)0x9AU;
AlfredoER 0:218e465e76b6 24 /* MCG->C4: DMX32=0,DRST_DRS=0 */
AlfredoER 0:218e465e76b6 25 MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
AlfredoER 0:218e465e76b6 26 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
AlfredoER 0:218e465e76b6 27 MCG->C5 = (uint8_t)0x01U;
AlfredoER 0:218e465e76b6 28 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
AlfredoER 0:218e465e76b6 29 MCG->C6 = (uint8_t)0x00U;
AlfredoER 0:218e465e76b6 30 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
AlfredoER 0:218e465e76b6 31 }
AlfredoER 0:218e465e76b6 32 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
AlfredoER 0:218e465e76b6 33 }
AlfredoER 0:218e465e76b6 34 /* Switch to PBE Mode */
AlfredoER 0:218e465e76b6 35 /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
AlfredoER 0:218e465e76b6 36 MCG->C6 = (uint8_t)0x40U;
AlfredoER 0:218e465e76b6 37 while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
AlfredoER 0:218e465e76b6 38 }
AlfredoER 0:218e465e76b6 39 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
AlfredoER 0:218e465e76b6 40 }
AlfredoER 0:218e465e76b6 41 /* Switch to PEE Mode */
AlfredoER 0:218e465e76b6 42 /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
AlfredoER 0:218e465e76b6 43 MCG->C1 = (uint8_t)0x1AU;
AlfredoER 0:218e465e76b6 44 while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
AlfredoER 0:218e465e76b6 45 }
AlfredoER 0:218e465e76b6 46
AlfredoER 0:218e465e76b6 47 /* Run this to get the new system frequency */
AlfredoER 0:218e465e76b6 48 SystemCoreClockUpdate();
AlfredoER 0:218e465e76b6 49 }
AlfredoER 0:218e465e76b6 50
AlfredoER 0:218e465e76b6 51 void switchPEEtoBLPI( void )
AlfredoER 0:218e465e76b6 52 {
AlfredoER 1:1097467b4352 53
AlfredoER 1:1097467b4352 54
AlfredoER 1:1097467b4352 55 // Move to PBE
AlfredoER 1:1097467b4352 56 MCG->C1 = (uint8_t)0x90U; /* Switch the system clock source to the external reference clock */
AlfredoER 1:1097467b4352 57 while((MCG->S & MCG_S_CLKST_MASK) != 0x2U<<MCG_S_CLKST_SHIFT) { /* Wait until external reference clock is selected as MCG output */
AlfredoER 1:1097467b4352 58 }
AlfredoER 1:1097467b4352 59
AlfredoER 1:1097467b4352 60
AlfredoER 1:1097467b4352 61 // Move to FBE
AlfredoER 1:1097467b4352 62 MCG->C6 = (uint8_t)0x00U; /* Select FLL */
AlfredoER 1:1097467b4352 63 while((MCG->S & MCG_S_PLLST_MASK) != 0x00U) { /* Wait until the current source for the PLLS clock is the FLL */
AlfredoER 1:1097467b4352 64 }
AlfredoER 1:1097467b4352 65
AlfredoER 1:1097467b4352 66 // Ok till here
AlfredoER 1:1097467b4352 67
AlfredoER 1:1097467b4352 68 // Move to FBI
AlfredoER 1:1097467b4352 69 MCG->C1 = (uint8_t)0x54U; /* Switch the system clock to the internal reference clock */
AlfredoER 1:1097467b4352 70 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Wait until the current source for the PLLS clock is the FLL */
AlfredoER 1:1097467b4352 71 }
AlfredoER 1:1097467b4352 72 while((MCG->S & MCG_S_CLKST_MASK) != 0x1U << MCG_S_CLKST_SHIFT) { /* Wait until the the internal reference clock is selected to feed MCGOUTCLK */
AlfredoER 1:1097467b4352 73 }
AlfredoER 1:1097467b4352 74
AlfredoER 1:1097467b4352 75 // Move to BLPI
AlfredoER 1:1097467b4352 76 MCG->C2 = (uint8_t)0x02; /* LP is 1 */
AlfredoER 1:1097467b4352 77 MCG->C1 |= MCG_C1_IRCLKEN_MASK; /* Clock is always active */
AlfredoER 1:1097467b4352 78
AlfredoER 1:1097467b4352 79 /* Run this to get the new system frequency */
AlfredoER 1:1097467b4352 80 //SystemCoreClockUpdate();
AlfredoER 1:1097467b4352 81
AlfredoER 1:1097467b4352 82 }
AlfredoER 1:1097467b4352 83
AlfredoER 1:1097467b4352 84 void switchBLPItoFEI( void )
AlfredoER 1:1097467b4352 85 {
AlfredoER 1:1097467b4352 86 // Move to FBI
AlfredoER 1:1097467b4352 87 /* LP is 0 */
AlfredoER 1:1097467b4352 88 MCG->C2 = (uint8_t) 0x00;
AlfredoER 1:1097467b4352 89
AlfredoER 1:1097467b4352 90 // Move to FEI
AlfredoER 1:1097467b4352 91 /* Update system prescalers */
AlfredoER 1:1097467b4352 92 SIM->CLKDIV1 = (uint32_t)0x00020000UL;
AlfredoER 1:1097467b4352 93 /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
AlfredoER 1:1097467b4352 94 MCG->C1 = (uint8_t)0x06U;
AlfredoER 1:1097467b4352 95 /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
AlfredoER 1:1097467b4352 96 MCG->C2 = (uint8_t)0x00U;
AlfredoER 1:1097467b4352 97 /* MCG->C4: DMX32=0,DRST_DRS=1 */
AlfredoER 1:1097467b4352 98 MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
AlfredoER 1:1097467b4352 99 /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
AlfredoER 1:1097467b4352 100 OSC0->CR = (uint8_t)0x80U;
AlfredoER 1:1097467b4352 101 /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
AlfredoER 1:1097467b4352 102 MCG->C5 = (uint8_t)0x00U;
AlfredoER 1:1097467b4352 103 /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
AlfredoER 1:1097467b4352 104 MCG->C6 = (uint8_t)0x00U;
AlfredoER 1:1097467b4352 105 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
AlfredoER 1:1097467b4352 106 }
AlfredoER 1:1097467b4352 107 while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
AlfredoER 1:1097467b4352 108 }
AlfredoER 0:218e465e76b6 109
AlfredoER 0:218e465e76b6 110 /* Run this to get the new system frequency */
AlfredoER 0:218e465e76b6 111 SystemCoreClockUpdate();
AlfredoER 0:218e465e76b6 112 }