system_MK64F12.h

00001 /*
00002 ** ###################################################################
00003 **     Processor:           MK64FN1M0VMD12
00004 **     Compilers:           Keil ARM C/C++ Compiler
00005 **                          Freescale C/C++ for Embedded ARM
00006 **                          GNU C Compiler
00007 **                          GNU C Compiler - CodeSourcery Sourcery G++
00008 **                          IAR ANSI C/C++ Compiler for ARM
00009 **
00010 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00011 **     Version:             rev. 2.5, 2014-02-10
00012 **     Build:               b140611
00013 **
00014 **     Abstract:
00015 **         Provides a system configuration function and a global variable that
00016 **         contains the system frequency. It configures the device and initializes
00017 **         the oscillator (PLL) that is part of the microcontroller device.
00018 **
00019 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00020 **     All rights reserved.
00021 **
00022 **     Redistribution and use in source and binary forms, with or without modification,
00023 **     are permitted provided that the following conditions are met:
00024 **
00025 **     o Redistributions of source code must retain the above copyright notice, this list
00026 **       of conditions and the following disclaimer.
00027 **
00028 **     o Redistributions in binary form must reproduce the above copyright notice, this
00029 **       list of conditions and the following disclaimer in the documentation and/or
00030 **       other materials provided with the distribution.
00031 **
00032 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00033 **       contributors may be used to endorse or promote products derived from this
00034 **       software without specific prior written permission.
00035 **
00036 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00037 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00038 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00040 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00041 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00042 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00043 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00044 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00045 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046 **
00047 **     http:                 www.freescale.com
00048 **     mail:                 support@freescale.com
00049 **
00050 **     Revisions:
00051 **     - rev. 1.0 (2013-08-12)
00052 **         Initial version.
00053 **     - rev. 2.0 (2013-10-29)
00054 **         Register accessor macros added to the memory map.
00055 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00056 **         Startup file for gcc has been updated according to CMSIS 3.2.
00057 **         System initialization updated.
00058 **         MCG - registers updated.
00059 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00060 **     - rev. 2.1 (2013-10-30)
00061 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00062 **     - rev. 2.2 (2013-12-09)
00063 **         DMA - EARS register removed.
00064 **         AIPS0, AIPS1 - MPRA register updated.
00065 **     - rev. 2.3 (2014-01-24)
00066 **         Update according to reference manual rev. 2
00067 **         ENET, MCG, MCM, SIM, USB - registers updated
00068 **     - rev. 2.4 (2014-02-10)
00069 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00070 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00071 **     - rev. 2.5 (2014-02-10)
00072 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00073 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00074 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00075 **
00076 ** ###################################################################
00077 */
00078 
00079 /*!
00080  * @file MK64F12
00081  * @version 2.5
00082  * @date 2014-02-10
00083  * @brief Device specific configuration file for MK64F12 (header file)
00084  *
00085  * Provides a system configuration function and a global variable that contains
00086  * the system frequency. It configures the device and initializes the oscillator
00087  * (PLL) that is part of the microcontroller device.
00088  */
00089 
00090 #ifndef SYSTEM_MK64F12_H_
00091 #define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
00092 
00093 #ifdef __cplusplus
00094 extern "C" {
00095 #endif
00096 
00097 #include <stdint.h>
00098 
00099 
00100 #define DISABLE_WDOG                   1
00101 
00102 #ifndef CLOCK_SETUP
00103   #define CLOCK_SETUP                  4
00104 #endif
00105 
00106 /* MCG mode constants */
00107 
00108 #define MCG_MODE_FEI                   0U
00109 #define MCG_MODE_FBI                   1U
00110 #define MCG_MODE_BLPI                  2U
00111 #define MCG_MODE_FEE                   3U
00112 #define MCG_MODE_FBE                   4U
00113 #define MCG_MODE_BLPE                  5U
00114 #define MCG_MODE_PBE                   6U
00115 #define MCG_MODE_PEE                   7U
00116 
00117 /* Predefined clock setups
00118    0 ... Default  part configuration
00119          Multipurpose Clock Generator (MCG) in FEI mode.
00120          Reference clock source for MCG module: Slow internal reference clock
00121          Core clock = 20.97152MHz
00122          Bus clock  = 20.97152MHz
00123    1 ... Maximum achievable clock frequency configuration
00124          Multipurpose Clock Generator (MCG) in PEE mode.
00125          Reference clock source for MCG module: System oscillator 0 reference clock
00126          Core clock = 120MHz
00127          Bus clock  = 60MHz
00128    2 ... Chip internaly clocked, ready for Very Low Power Run mode.
00129          Multipurpose Clock Generator (MCG) in BLPI mode.
00130          Reference clock source for MCG module: Fast internal reference clock
00131          Core clock = 4MHz
00132          Bus clock  = 4MHz
00133    3 ... Chip externally clocked, ready for Very Low Power Run mode.
00134          Multipurpose Clock Generator (MCG) in BLPE mode.
00135          Reference clock source for MCG module: RTC oscillator reference clock
00136          Core clock = 0.032768MHz
00137          Bus clock  = 0.032768MHz
00138    4 ... USB clock setup
00139          Multipurpose Clock Generator (MCG) in PEE mode.
00140          Reference clock source for MCG module: System oscillator 0 reference clock
00141          Core clock = 120MHz
00142          Bus clock  = 60MHz
00143  */
00144 
00145 /* Define clock source values */
00146 
00147 #define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
00148 #define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
00149 #define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
00150 #define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
00151 #define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
00152 
00153 /* RTC oscillator setting */
00154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
00155 #define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
00156 
00157 /* Low power mode enable */
00158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
00159 #define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
00160 
00161 /* Internal reference clock trim */
00162 /* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
00163 /* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
00164 /* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
00165 /* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
00166 
00167 #if (CLOCK_SETUP == 0)
00168   #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
00169   #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
00170   /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00171   #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
00172   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
00173   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
00174   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
00175   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
00176   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
00177   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
00178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00179   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
00180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00181   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
00182 /* MCG_C7: OSCSEL=0 */
00183   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
00184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00185   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
00186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
00187   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
00188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
00189   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
00190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
00191   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
00192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
00193   #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
00194 #elif (CLOCK_SETUP == 1)
00195   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
00196   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
00197   /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00198   #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
00199   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
00200   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
00201   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
00202   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
00203   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
00204   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
00205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
00206   #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
00207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
00208   #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
00209 /* MCG_C7: OSCSEL=0 */
00210   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
00211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00212   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
00213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
00214   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
00215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
00216   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
00217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
00218   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
00219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
00220   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
00221 #elif (CLOCK_SETUP == 2)
00222   #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
00223   #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
00224   /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00225   #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
00226   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
00227   #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
00228   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
00229   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
00230   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
00231   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
00232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00233   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
00234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00235   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
00236 /* MCG_C7: OSCSEL=0 */
00237   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
00238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00239   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
00240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
00241   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
00242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
00243   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
00244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
00245   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
00246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
00247   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
00248 #elif (CLOCK_SETUP == 3)
00249   #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
00250   #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
00251   /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00252   #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
00253   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
00254   #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
00255   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
00256   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
00257   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
00258   #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
00259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00260   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
00261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00262   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
00263 /* MCG_C7: OSCSEL=1 */
00264   #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
00265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00266   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
00267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
00268   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
00269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
00270   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
00271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
00272   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
00273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
00274   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
00275 #elif (CLOCK_SETUP == 4)
00276   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
00277   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
00278   /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00279   #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
00280   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
00281   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
00282   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
00283   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
00284   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
00285   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
00286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
00287   #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
00288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
00289   #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
00290 /* MCG_C7: OSCSEL=0 */
00291   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
00292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00293   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
00294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
00295   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
00296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
00297   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
00298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
00299   #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
00300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
00301   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
00302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
00303   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
00304 #endif
00305 
00306 /**
00307  * @brief System clock frequency (core clock)
00308  *
00309  * The system clock frequency supplied to the SysTick timer and the processor
00310  * core clock. This variable can be used by the user application to setup the
00311  * SysTick timer or configure other parameters. It may also be used by debugger to
00312  * query the frequency of the debug timer or configure the trace clock speed
00313  * SystemCoreClock is initialized with a correct predefined value.
00314  */
00315 extern uint32_t SystemCoreClock;
00316 
00317 /**
00318  * @brief Setup the microcontroller system.
00319  *
00320  * Typically this function configures the oscillator (PLL) that is part of the
00321  * microcontroller device. For systems with variable clock speed it also updates
00322  * the variable SystemCoreClock. SystemInit is called from startup_device file.
00323  */
00324 void SystemInit (void);
00325 
00326 /**
00327  * @brief Updates the SystemCoreClock variable.
00328  *
00329  * It must be called whenever the core clock is changed during program
00330  * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
00331  * the current core clock.
00332  */
00333 void SystemCoreClockUpdate (void);
00334 
00335 #ifdef __cplusplus
00336 }
00337 #endif
00338 
00339 #endif  /* #if !defined(SYSTEM_MK64F12_H_) */