system_MK64F12.c

00001 /*
00002 ** ###################################################################
00003 **     Processor:           MK64FN1M0VMD12
00004 **     Compilers:           Keil ARM C/C++ Compiler
00005 **                          Freescale C/C++ for Embedded ARM
00006 **                          GNU C Compiler
00007 **                          GNU C Compiler - CodeSourcery Sourcery G++
00008 **                          IAR ANSI C/C++ Compiler for ARM
00009 **
00010 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00011 **     Version:             rev. 2.5, 2014-02-10
00012 **     Build:               b140611
00013 **
00014 **     Abstract:
00015 **         Provides a system configuration function and a global variable that
00016 **         contains the system frequency. It configures the device and initializes
00017 **         the oscillator (PLL) that is part of the microcontroller device.
00018 **
00019 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00020 **     All rights reserved.
00021 **
00022 **     Redistribution and use in source and binary forms, with or without modification,
00023 **     are permitted provided that the following conditions are met:
00024 **
00025 **     o Redistributions of source code must retain the above copyright notice, this list
00026 **       of conditions and the following disclaimer.
00027 **
00028 **     o Redistributions in binary form must reproduce the above copyright notice, this
00029 **       list of conditions and the following disclaimer in the documentation and/or
00030 **       other materials provided with the distribution.
00031 **
00032 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00033 **       contributors may be used to endorse or promote products derived from this
00034 **       software without specific prior written permission.
00035 **
00036 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00037 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00038 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00039 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00040 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00041 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00042 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00043 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00044 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00045 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00046 **
00047 **     http:                 www.freescale.com
00048 **     mail:                 support@freescale.com
00049 **
00050 **     Revisions:
00051 **     - rev. 1.0 (2013-08-12)
00052 **         Initial version.
00053 **     - rev. 2.0 (2013-10-29)
00054 **         Register accessor macros added to the memory map.
00055 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00056 **         Startup file for gcc has been updated according to CMSIS 3.2.
00057 **         System initialization updated.
00058 **         MCG - registers updated.
00059 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00060 **     - rev. 2.1 (2013-10-30)
00061 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00062 **     - rev. 2.2 (2013-12-09)
00063 **         DMA - EARS register removed.
00064 **         AIPS0, AIPS1 - MPRA register updated.
00065 **     - rev. 2.3 (2014-01-24)
00066 **         Update according to reference manual rev. 2
00067 **         ENET, MCG, MCM, SIM, USB - registers updated
00068 **     - rev. 2.4 (2014-02-10)
00069 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00070 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00071 **     - rev. 2.5 (2014-02-10)
00072 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00073 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00074 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00075 **
00076 ** ###################################################################
00077 */
00078 
00079 /*!
00080  * @file MK64F12
00081  * @version 2.5
00082  * @date 2014-02-10
00083  * @brief Device specific configuration file for MK64F12 (implementation file)
00084  *
00085  * Provides a system configuration function and a global variable that contains
00086  * the system frequency. It configures the device and initializes the oscillator
00087  * (PLL) that is part of the microcontroller device.
00088  */
00089 
00090 #include <stdint.h>
00091 #include "cmsis.h"
00092 
00093 
00094 
00095 /* ----------------------------------------------------------------------------
00096    -- Core clock
00097    ---------------------------------------------------------------------------- */
00098 
00099 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00100 
00101 /* ----------------------------------------------------------------------------
00102    -- SystemInit()
00103    ---------------------------------------------------------------------------- */
00104 
00105 void SystemInit (void) {
00106 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
00107   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
00108 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
00109 #if (DISABLE_WDOG)
00110   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
00111   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
00112   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
00113   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
00114   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
00115   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
00116                  WDOG_STCTRLH_WAITEN_MASK |
00117                  WDOG_STCTRLH_STOPEN_MASK |
00118                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
00119                  WDOG_STCTRLH_CLKSRC_MASK |
00120                  0x0100U;
00121 #endif /* (DISABLE_WDOG) */
00122   if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
00123   {
00124     if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
00125     {
00126        PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
00127     }
00128   } else {
00129 #ifdef SYSTEM_RTC_CR_VALUE
00130     SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
00131     if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
00132       RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
00133       RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
00134       RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
00135     }
00136 #endif
00137   }
00138 
00139   /* Power mode protection initialization */
00140 #ifdef SYSTEM_SMC_PMPROT_VALUE
00141   SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
00142 #endif
00143 
00144   /* System clock initialization */
00145   /* Internal reference clock trim initialization */
00146 #if defined(SLOW_TRIM_ADDRESS)
00147   if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
00148     MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
00149   #endif /* defined(SLOW_TRIM_ADDRESS) */
00150   #if defined(SLOW_FINE_TRIM_ADDRESS)
00151     MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
00152   #endif
00153   #if defined(FAST_TRIM_ADDRESS)
00154     MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
00155   #endif
00156   #if defined(FAST_FINE_TRIM_ADDRESS)
00157     MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
00158   #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
00159 #if defined(SLOW_TRIM_ADDRESS)
00160   }
00161   #endif /* defined(SLOW_TRIM_ADDRESS) */
00162 
00163   /* Set system prescalers and clock sources */
00164   SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
00165   SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
00166   SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
00167 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
00168   /* Set MCG and OSC */
00169 #if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
00170   /* SIM_SCGC5: PORTA=1 */
00171   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
00172   /* PORTA_PCR18: ISF=0,MUX=0 */
00173   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00174   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
00175   /* PORTA_PCR19: ISF=0,MUX=0 */
00176   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00177   }
00178 #endif
00179   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
00180   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
00181   /* Check that the source of the FLL reference clock is the requested one. */
00182   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
00183     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
00184     }
00185   } else {
00186     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
00187     }
00188   }
00189   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
00190   MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
00191   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
00192   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
00193   #if (MCG_MODE == MCG_MODE_BLPI)
00194   /* BLPI specific */
00195   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
00196   #endif
00197 
00198 #else /* MCG_MODE */
00199   /* Set MCG and OSC */
00200 #if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
00201   /* SIM_SCGC5: PORTA=1 */
00202   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
00203   /* PORTA_PCR18: ISF=0,MUX=0 */
00204   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00205   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
00206   /* PORTA_PCR19: ISF=0,MUX=0 */
00207   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
00208   }
00209 #endif
00210   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
00211   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
00212   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
00213   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
00214   #if (MCG_MODE == MCG_MODE_PEE)
00215   MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
00216   #else
00217   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
00218   #endif
00219   if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
00220     while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
00221     }
00222   }
00223   /* Check that the source of the FLL reference clock is the requested one. */
00224   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
00225     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
00226     }
00227   } else {
00228     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
00229     }
00230   }
00231   MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
00232 #endif /* MCG_MODE */
00233 
00234   /* Common for all MCG modes */
00235 
00236   /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
00237   MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
00238   MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
00239   if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
00240     MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
00241   }
00242   /* BLPE, PEE and PBE MCG mode specific */
00243 
00244 #if (MCG_MODE == MCG_MODE_BLPE)
00245   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
00246 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
00247   MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
00248   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
00249   }
00250   #if (MCG_MODE == MCG_MODE_PEE)
00251   MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
00252   #endif
00253 #endif
00254 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
00255   while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
00256   }
00257 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
00258   while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
00259   }
00260 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
00261   while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
00262   }
00263 #elif (MCG_MODE == MCG_MODE_PEE)
00264   while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
00265   }
00266 #endif
00267 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
00268   SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
00269   while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
00270   }
00271 #endif
00272 
00273 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
00274   SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
00275 #endif
00276 
00277   /* PLL loss of lock interrupt request initialization */
00278   if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
00279     NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
00280   }
00281 }
00282 
00283 /* ----------------------------------------------------------------------------
00284    -- SystemCoreClockUpdate()
00285    ---------------------------------------------------------------------------- */
00286 
00287 void SystemCoreClockUpdate (void) {
00288   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
00289   uint16_t Divider;
00290 
00291   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
00292     /* Output of FLL or PLL is selected */
00293     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
00294       /* FLL is selected */
00295       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
00296         /* External reference clock is selected */
00297         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
00298         case 0x00U:
00299           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
00300           break;
00301         case 0x01U:
00302           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
00303           break;
00304         case 0x02U:
00305         default:
00306           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
00307           break;
00308         }
00309         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
00310           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
00311           case 0x38U:
00312             Divider = 1536U;
00313             break;
00314           case 0x30U:
00315             Divider = 1280U;
00316             break;
00317           default:
00318             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00319             break;
00320           }
00321         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
00322           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00323         }
00324         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
00325       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
00326         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
00327       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
00328       /* Select correct multiplier to calculate the MCG output clock  */
00329       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
00330         case 0x00U:
00331           MCGOUTClock *= 640U;
00332           break;
00333         case 0x20U:
00334           MCGOUTClock *= 1280U;
00335           break;
00336         case 0x40U:
00337           MCGOUTClock *= 1920U;
00338           break;
00339         case 0x60U:
00340           MCGOUTClock *= 2560U;
00341           break;
00342         case 0x80U:
00343           MCGOUTClock *= 732U;
00344           break;
00345         case 0xA0U:
00346           MCGOUTClock *= 1464U;
00347           break;
00348         case 0xC0U:
00349           MCGOUTClock *= 2197U;
00350           break;
00351         case 0xE0U:
00352           MCGOUTClock *= 2929U;
00353           break;
00354         default:
00355           break;
00356       }
00357     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
00358       /* PLL is selected */
00359       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
00360       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
00361       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
00362       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
00363     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
00364   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
00365     /* Internal reference clock is selected */
00366     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
00367       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
00368     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
00369       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
00370       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
00371     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
00372   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
00373     /* External reference clock is selected */
00374     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
00375     case 0x00U:
00376       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
00377       break;
00378     case 0x01U:
00379       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
00380       break;
00381     case 0x02U:
00382     default:
00383       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
00384       break;
00385     }
00386   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
00387     /* Reserved value */
00388     return;
00389   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
00390   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
00391 }