Alessandro Angelino
/
target-mcu-k64f
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Fork of
target-mcu-k64f
by 
Morpheus
Embed:
(wiki syntax)
Show/hide line numbers
fsl_bitaccess.h
00001 /* 00002 ** ################################################################### 00003 ** Version: rev. 2.5, 2014-02-10 00004 ** Build: b140604 00005 ** 00006 ** Abstract: 00007 ** Register bit field access macros. 00008 ** 00009 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00010 ** All rights reserved. 00011 ** 00012 ** (C) COPYRIGHT 2015-2015 ARM Limited 00013 ** ALL RIGHTS RESERVED 00014 ** 00015 ** Redistribution and use in source and binary forms, with or without modification, 00016 ** are permitted provided that the following conditions are met: 00017 ** 00018 ** o Redistributions of source code must retain the above copyright notice, this list 00019 ** of conditions and the following disclaimer. 00020 ** 00021 ** o Redistributions in binary form must reproduce the above copyright notice, this 00022 ** list of conditions and the following disclaimer in the documentation and/or 00023 ** other materials provided with the distribution. 00024 ** 00025 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00026 ** contributors may be used to endorse or promote products derived from this 00027 ** software without specific prior written permission. 00028 ** 00029 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00030 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00031 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00032 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00033 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00034 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00035 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00036 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00037 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00038 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00039 ** 00040 ** http: www.freescale.com 00041 ** mail: support@freescale.com 00042 ** 00043 ** Revisions: 00044 ** - rev. 1.0 (2013-08-12) 00045 ** Initial version. 00046 ** - rev. 2.0 (2013-10-29) 00047 ** Register accessor macros added to the memory map. 00048 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00049 ** Startup file for gcc has been updated according to CMSIS 3.2. 00050 ** System initialization updated. 00051 ** MCG - registers updated. 00052 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00053 ** - rev. 2.1 (2013-10-30) 00054 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00055 ** - rev. 2.2 (2013-12-09) 00056 ** DMA - EARS register removed. 00057 ** AIPS0, AIPS1 - MPRA register updated. 00058 ** - rev. 2.3 (2014-01-24) 00059 ** Update according to reference manual rev. 2 00060 ** ENET, MCG, MCM, SIM, USB - registers updated 00061 ** - rev. 2.4 (2014-02-10) 00062 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00063 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00064 ** - rev. 2.5 (2014-02-10) 00065 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00066 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00067 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00068 ** - rev. 2.6 (2015-07-30) (ARM) 00069 ** Macros for bitband address calculation have been decoupled from the 00070 ** actual address de-referencing in BITBAND_ACCESSxx macros; 00071 ** Added fallback macros for default read/write operations 00072 ** 00073 ** ################################################################### 00074 */ 00075 00076 00077 #ifndef _FSL_BITACCESS_H 00078 #define _FSL_BITACCESS_H 1 00079 00080 #include <stdint.h> 00081 #include <stdlib.h> 00082 #include "uvisor-lib/uvisor-lib.h" 00083 00084 /* 00085 * Fallback macros for write/read operations 00086 */ 00087 #ifndef ADDRESS_READ 00088 /* the conditional statement will be optimised away since the compiler already 00089 * knows the sizeof(type) */ 00090 #define ADDRESS_READ(type, addr) \ 00091 (sizeof(type) == 4 ? *((volatile uint32_t *) (addr)) : \ 00092 sizeof(type) == 2 ? *((volatile uint16_t *) (addr)) : \ 00093 sizeof(type) == 1 ? *((volatile uint8_t *) (addr)) : 0) 00094 #endif 00095 00096 #ifndef ADDRESS_WRITE 00097 /* the switch statement will be optimised away since the compiler already knows 00098 * the sizeof(type) */ 00099 #define ADDRESS_WRITE(type, addr, val) \ 00100 { \ 00101 switch(sizeof(type)) \ 00102 { \ 00103 case 4: \ 00104 *((volatile uint32_t *) (addr)) = (uint32_t) (val); \ 00105 break; \ 00106 case 2: \ 00107 *((volatile uint16_t *) (addr)) = (uint16_t) (val); \ 00108 break; \ 00109 case 1: \ 00110 *((volatile uint8_t *) (addr)) = (uint8_t ) (val); \ 00111 break; \ 00112 } \ 00113 } 00114 #endif 00115 00116 #ifndef UNION_READ 00117 #define UNION_READ(type, addr, fieldU, fieldB) ((*((volatile type *) (addr))).fieldB) 00118 #endif 00119 00120 /* 00121 * Macros to translate a pair of regular address and bit to their bit band alias 00122 */ 00123 #define BITBAND_ADDRESS(Reg,Bit) (0x42000000u + (32u*((uint32_t)(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) 00124 #define BITBAND_ADDRESS32(Reg,Bit) ((uint32_t volatile*)BITBAND_ADDRESS(Reg,Bit)) 00125 #define BITBAND_ADDRESS16(Reg,Bit) ((uint16_t volatile*)BITBAND_ADDRESS(Reg,Bit)) 00126 #define BITBAND_ADDRESS8(Reg,Bit) ((uint8_t volatile*)BITBAND_ADDRESS(Reg,Bit)) 00127 00128 /** 00129 * @brief Macro to access a single bit of a 32-bit peripheral register (bit band region 00130 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. 00131 * @param Reg Register to access. 00132 * @param Bit Bit number to access. 00133 * @return Value of the targeted bit in the bit band region. 00134 */ 00135 #define BITBAND_ACCESS32(Reg,Bit) (*BITBAND_ADDRESS32(Reg,Bit)) 00136 00137 /** 00138 * @brief Macro to access a single bit of a 16-bit peripheral register (bit band region 00139 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. 00140 * @param Reg Register to access. 00141 * @param Bit Bit number to access. 00142 * @return Value of the targeted bit in the bit band region. 00143 */ 00144 #define BITBAND_ACCESS16(Reg,Bit) (*BITBAND_ADDRESS16(Reg,Bit)) 00145 00146 /** 00147 * @brief Macro to access a single bit of an 8-bit peripheral register (bit band region 00148 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. 00149 * @param Reg Register to access. 00150 * @param Bit Bit number to access. 00151 * @return Value of the targeted bit in the bit band region. 00152 */ 00153 #define BITBAND_ACCESS8(Reg,Bit) (*BITBAND_ADDRESS8(Reg,Bit)) 00154 00155 /* 00156 * Macros for single instance registers 00157 */ 00158 00159 #define BF_SET(reg, field) HW_##reg##_SET(BM_##reg##_##field) 00160 #define BF_CLR(reg, field) HW_##reg##_CLR(BM_##reg##_##field) 00161 #define BF_TOG(reg, field) HW_##reg##_TOG(BM_##reg##_##field) 00162 00163 #define BF_SETV(reg, field, v) HW_##reg##_SET(BF_##reg##_##field(v)) 00164 #define BF_CLRV(reg, field, v) HW_##reg##_CLR(BF_##reg##_##field(v)) 00165 #define BF_TOGV(reg, field, v) HW_##reg##_TOG(BF_##reg##_##field(v)) 00166 00167 #define BV_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) 00168 #define BV_VAL(reg, field, sym) BV_##reg##_##field##__##sym 00169 00170 #define BF_RD(reg, field) HW_##reg.B.field 00171 #define BF_WR(reg, field, v) BW_##reg##_##field(v) 00172 00173 #define BF_CS1(reg, f1, v1) \ 00174 (HW_##reg##_CLR(BM_##reg##_##f1), \ 00175 HW_##reg##_SET(BF_##reg##_##f1(v1))) 00176 00177 #define BF_CS2(reg, f1, v1, f2, v2) \ 00178 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00179 BM_##reg##_##f2), \ 00180 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00181 BF_##reg##_##f2(v2))) 00182 00183 #define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \ 00184 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00185 BM_##reg##_##f2 | \ 00186 BM_##reg##_##f3), \ 00187 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00188 BF_##reg##_##f2(v2) | \ 00189 BF_##reg##_##f3(v3))) 00190 00191 #define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ 00192 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00193 BM_##reg##_##f2 | \ 00194 BM_##reg##_##f3 | \ 00195 BM_##reg##_##f4), \ 00196 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00197 BF_##reg##_##f2(v2) | \ 00198 BF_##reg##_##f3(v3) | \ 00199 BF_##reg##_##f4(v4))) 00200 00201 #define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ 00202 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00203 BM_##reg##_##f2 | \ 00204 BM_##reg##_##f3 | \ 00205 BM_##reg##_##f4 | \ 00206 BM_##reg##_##f5), \ 00207 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00208 BF_##reg##_##f2(v2) | \ 00209 BF_##reg##_##f3(v3) | \ 00210 BF_##reg##_##f4(v4) | \ 00211 BF_##reg##_##f5(v5))) 00212 00213 #define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ 00214 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00215 BM_##reg##_##f2 | \ 00216 BM_##reg##_##f3 | \ 00217 BM_##reg##_##f4 | \ 00218 BM_##reg##_##f5 | \ 00219 BM_##reg##_##f6), \ 00220 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00221 BF_##reg##_##f2(v2) | \ 00222 BF_##reg##_##f3(v3) | \ 00223 BF_##reg##_##f4(v4) | \ 00224 BF_##reg##_##f5(v5) | \ 00225 BF_##reg##_##f6(v6))) 00226 00227 #define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ 00228 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00229 BM_##reg##_##f2 | \ 00230 BM_##reg##_##f3 | \ 00231 BM_##reg##_##f4 | \ 00232 BM_##reg##_##f5 | \ 00233 BM_##reg##_##f6 | \ 00234 BM_##reg##_##f7), \ 00235 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00236 BF_##reg##_##f2(v2) | \ 00237 BF_##reg##_##f3(v3) | \ 00238 BF_##reg##_##f4(v4) | \ 00239 BF_##reg##_##f5(v5) | \ 00240 BF_##reg##_##f6(v6) | \ 00241 BF_##reg##_##f7(v7))) 00242 00243 #define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ 00244 (HW_##reg##_CLR(BM_##reg##_##f1 | \ 00245 BM_##reg##_##f2 | \ 00246 BM_##reg##_##f3 | \ 00247 BM_##reg##_##f4 | \ 00248 BM_##reg##_##f5 | \ 00249 BM_##reg##_##f6 | \ 00250 BM_##reg##_##f7 | \ 00251 BM_##reg##_##f8), \ 00252 HW_##reg##_SET(BF_##reg##_##f1(v1) | \ 00253 BF_##reg##_##f2(v2) | \ 00254 BF_##reg##_##f3(v3) | \ 00255 BF_##reg##_##f4(v4) | \ 00256 BF_##reg##_##f5(v5) | \ 00257 BF_##reg##_##f6(v6) | \ 00258 BF_##reg##_##f7(v7) | \ 00259 BF_##reg##_##f8(v8))) 00260 00261 /* 00262 * Macros for multiple instance registers 00263 */ 00264 00265 #define BF_SETn(reg, n, field) HW_##reg##_SET(n, BM_##reg##_##field) 00266 #define BF_CLRn(reg, n, field) HW_##reg##_CLR(n, BM_##reg##_##field) 00267 #define BF_TOGn(reg, n, field) HW_##reg##_TOG(n, BM_##reg##_##field) 00268 00269 #define BF_SETVn(reg, n, field, v) HW_##reg##_SET(n, BF_##reg##_##field(v)) 00270 #define BF_CLRVn(reg, n, field, v) HW_##reg##_CLR(n, BF_##reg##_##field(v)) 00271 #define BF_TOGVn(reg, n, field, v) HW_##reg##_TOG(n, BF_##reg##_##field(v)) 00272 00273 #define BV_FLDn(reg, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) 00274 #define BV_VALn(reg, n, field, sym) BV_##reg##_##field##__##sym 00275 00276 #define BF_RDn(reg, n, field) HW_##reg(n).B.field 00277 #define BF_WRn(reg, n, field, v) BW_##reg##_##field(n, v) 00278 00279 #define BF_CS1n(reg, n, f1, v1) \ 00280 (HW_##reg##_CLR(n, (BM_##reg##_##f1)), \ 00281 HW_##reg##_SET(n, (BF_##reg##_##f1(v1)))) 00282 00283 #define BF_CS2n(reg, n, f1, v1, f2, v2) \ 00284 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00285 BM_##reg##_##f2)), \ 00286 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00287 BF_##reg##_##f2(v2)))) 00288 00289 #define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \ 00290 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00291 BM_##reg##_##f2 | \ 00292 BM_##reg##_##f3)), \ 00293 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00294 BF_##reg##_##f2(v2) | \ 00295 BF_##reg##_##f3(v3)))) 00296 00297 #define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \ 00298 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00299 BM_##reg##_##f2 | \ 00300 BM_##reg##_##f3 | \ 00301 BM_##reg##_##f4)), \ 00302 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00303 BF_##reg##_##f2(v2) | \ 00304 BF_##reg##_##f3(v3) | \ 00305 BF_##reg##_##f4(v4)))) 00306 00307 #define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ 00308 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00309 BM_##reg##_##f2 | \ 00310 BM_##reg##_##f3 | \ 00311 BM_##reg##_##f4 | \ 00312 BM_##reg##_##f5)), \ 00313 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00314 BF_##reg##_##f2(v2) | \ 00315 BF_##reg##_##f3(v3) | \ 00316 BF_##reg##_##f4(v4) | \ 00317 BF_##reg##_##f5(v5)))) 00318 00319 #define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ 00320 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00321 BM_##reg##_##f2 | \ 00322 BM_##reg##_##f3 | \ 00323 BM_##reg##_##f4 | \ 00324 BM_##reg##_##f5 | \ 00325 BM_##reg##_##f6)), \ 00326 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00327 BF_##reg##_##f2(v2) | \ 00328 BF_##reg##_##f3(v3) | \ 00329 BF_##reg##_##f4(v4) | \ 00330 BF_##reg##_##f5(v5) | \ 00331 BF_##reg##_##f6(v6)))) 00332 00333 #define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ 00334 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00335 BM_##reg##_##f2 | \ 00336 BM_##reg##_##f3 | \ 00337 BM_##reg##_##f4 | \ 00338 BM_##reg##_##f5 | \ 00339 BM_##reg##_##f6 | \ 00340 BM_##reg##_##f7)), \ 00341 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00342 BF_##reg##_##f2(v2) | \ 00343 BF_##reg##_##f3(v3) | \ 00344 BF_##reg##_##f4(v4) | \ 00345 BF_##reg##_##f5(v5) | \ 00346 BF_##reg##_##f6(v6) | \ 00347 BF_##reg##_##f7(v7)))) 00348 00349 #define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ 00350 (HW_##reg##_CLR(n, (BM_##reg##_##f1 | \ 00351 BM_##reg##_##f2 | \ 00352 BM_##reg##_##f3 | \ 00353 BM_##reg##_##f4 | \ 00354 BM_##reg##_##f5 | \ 00355 BM_##reg##_##f6 | \ 00356 BM_##reg##_##f7 | \ 00357 BM_##reg##_##f8)), \ 00358 HW_##reg##_SET(n, (BF_##reg##_##f1(v1) | \ 00359 BF_##reg##_##f2(v2) | \ 00360 BF_##reg##_##f3(v3) | \ 00361 BF_##reg##_##f4(v4) | \ 00362 BF_##reg##_##f5(v5) | \ 00363 BF_##reg##_##f6(v6) | \ 00364 BF_##reg##_##f7(v7) | \ 00365 BF_##reg##_##f8(v8)))) 00366 00367 /* 00368 * Macros for single instance MULTI-BLOCK registers 00369 */ 00370 00371 #define BFn_SET(reg, blk, field) HW_##reg##_SET(blk, BM_##reg##_##field) 00372 #define BFn_CLR(reg, blk, field) HW_##reg##_CLR(blk, BM_##reg##_##field) 00373 #define BFn_TOG(reg, blk, field) HW_##reg##_TOG(blk, BM_##reg##_##field) 00374 00375 #define BFn_SETV(reg, blk, field, v) HW_##reg##_SET(blk, BF_##reg##_##field(v)) 00376 #define BFn_CLRV(reg, blk, field, v) HW_##reg##_CLR(blk, BF_##reg##_##field(v)) 00377 #define BFn_TOGV(reg, blk, field, v) HW_##reg##_TOG(blk, BF_##reg##_##field(v)) 00378 00379 #define BVn_FLD(reg, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) 00380 #define BVn_VAL(reg, field, sym) BV_##reg##_##field##__##sym 00381 00382 #define BFn_RD(reg, blk, field) HW_##reg(blk).B.field 00383 #define BFn_WR(reg, blk, field, v) BW_##reg##_##field(blk, v) 00384 00385 #define BFn_CS1(reg, blk, f1, v1) \ 00386 (HW_##reg##_CLR(blk, BM_##reg##_##f1), \ 00387 HW_##reg##_SET(blk, BF_##reg##_##f1(v1))) 00388 00389 #define BFn_CS2(reg, blk, f1, v1, f2, v2) \ 00390 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00391 BM_##reg##_##f2), \ 00392 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00393 BF_##reg##_##f2(v2))) 00394 00395 #define BFn_CS3(reg, blk, f1, v1, f2, v2, f3, v3) \ 00396 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00397 BM_##reg##_##f2 | \ 00398 BM_##reg##_##f3), \ 00399 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00400 BF_##reg##_##f2(v2) | \ 00401 BF_##reg##_##f3(v3))) 00402 00403 #define BFn_CS4(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4) \ 00404 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00405 BM_##reg##_##f2 | \ 00406 BM_##reg##_##f3 | \ 00407 BM_##reg##_##f4), \ 00408 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00409 BF_##reg##_##f2(v2) | \ 00410 BF_##reg##_##f3(v3) | \ 00411 BF_##reg##_##f4(v4))) 00412 00413 #define BFn_CS5(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ 00414 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00415 BM_##reg##_##f2 | \ 00416 BM_##reg##_##f3 | \ 00417 BM_##reg##_##f4 | \ 00418 BM_##reg##_##f5), \ 00419 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00420 BF_##reg##_##f2(v2) | \ 00421 BF_##reg##_##f3(v3) | \ 00422 BF_##reg##_##f4(v4) | \ 00423 BF_##reg##_##f5(v5))) 00424 00425 #define BFn_CS6(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ 00426 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00427 BM_##reg##_##f2 | \ 00428 BM_##reg##_##f3 | \ 00429 BM_##reg##_##f4 | \ 00430 BM_##reg##_##f5 | \ 00431 BM_##reg##_##f6), \ 00432 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00433 BF_##reg##_##f2(v2) | \ 00434 BF_##reg##_##f3(v3) | \ 00435 BF_##reg##_##f4(v4) | \ 00436 BF_##reg##_##f5(v5) | \ 00437 BF_##reg##_##f6(v6))) 00438 00439 #define BFn_CS7(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ 00440 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00441 BM_##reg##_##f2 | \ 00442 BM_##reg##_##f3 | \ 00443 BM_##reg##_##f4 | \ 00444 BM_##reg##_##f5 | \ 00445 BM_##reg##_##f6 | \ 00446 BM_##reg##_##f7), \ 00447 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00448 BF_##reg##_##f2(v2) | \ 00449 BF_##reg##_##f3(v3) | \ 00450 BF_##reg##_##f4(v4) | \ 00451 BF_##reg##_##f5(v5) | \ 00452 BF_##reg##_##f6(v6) | \ 00453 BF_##reg##_##f7(v7))) 00454 00455 #define BFn_CS8(reg, blk, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ 00456 (HW_##reg##_CLR(blk, BM_##reg##_##f1 | \ 00457 BM_##reg##_##f2 | \ 00458 BM_##reg##_##f3 | \ 00459 BM_##reg##_##f4 | \ 00460 BM_##reg##_##f5 | \ 00461 BM_##reg##_##f6 | \ 00462 BM_##reg##_##f7 | \ 00463 BM_##reg##_##f8), \ 00464 HW_##reg##_SET(blk, BF_##reg##_##f1(v1) | \ 00465 BF_##reg##_##f2(v2) | \ 00466 BF_##reg##_##f3(v3) | \ 00467 BF_##reg##_##f4(v4) | \ 00468 BF_##reg##_##f5(v5) | \ 00469 BF_##reg##_##f6(v6) | \ 00470 BF_##reg##_##f7(v7) | \ 00471 BF_##reg##_##f8(v8))) 00472 00473 /* 00474 * Macros for MULTI-BLOCK multiple instance registers 00475 */ 00476 00477 #define BFn_SETn(reg, blk, n, field) HW_##reg##_SET(blk, n, BM_##reg##_##field) 00478 #define BFn_CLRn(reg, blk, n, field) HW_##reg##_CLR(blk, n, BM_##reg##_##field) 00479 #define BFn_TOGn(reg, blk, n, field) HW_##reg##_TOG(blk, n, BM_##reg##_##field) 00480 00481 #define BFn_SETVn(reg, blk, n, field, v) HW_##reg##_SET(blk, n, BF_##reg##_##field(v)) 00482 #define BFn_CLRVn(reg, blk, n, field, v) HW_##reg##_CLR(blk, n, BF_##reg##_##field(v)) 00483 #define BFn_TOGVn(reg, blk, n, field, v) HW_##reg##_TOG(blk, n, BF_##reg##_##field(v)) 00484 00485 #define BVn_FLDn(reg, blk, n, field, sym) BF_##reg##_##field(BV_##reg##_##field##__##sym) 00486 #define BVn_VALn(reg, blk, n, field, sym) BV_##reg##_##field##__##sym 00487 00488 #define BFn_RDn(reg, blk, n, field) HW_##reg(n).B.field 00489 #define BFn_WRn(reg, blk, n, field, v) BW_##reg##_##field(n, v) 00490 00491 #define BFn_CS1n(reg, blk, n, f1, v1) \ 00492 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1)), \ 00493 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1)))) 00494 00495 #define BFn_CS2n(reg, blk, n, f1, v1, f2, v2) \ 00496 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00497 BM_##reg##_##f2)), \ 00498 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00499 BF_##reg##_##f2(v2)))) 00500 00501 #define BFn_CS3n(reg, blk, n, f1, v1, f2, v2, f3, v3) \ 00502 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00503 BM_##reg##_##f2 | \ 00504 BM_##reg##_##f3)), \ 00505 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00506 BF_##reg##_##f2(v2) | \ 00507 BF_##reg##_##f3(v3)))) 00508 00509 #define BFn_CS4n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4) \ 00510 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00511 BM_##reg##_##f2 | \ 00512 BM_##reg##_##f3 | \ 00513 BM_##reg##_##f4)), \ 00514 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00515 BF_##reg##_##f2(v2) | \ 00516 BF_##reg##_##f3(v3) | \ 00517 BF_##reg##_##f4(v4)))) 00518 00519 #define BFn_CS5n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \ 00520 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00521 BM_##reg##_##f2 | \ 00522 BM_##reg##_##f3 | \ 00523 BM_##reg##_##f4 | \ 00524 BM_##reg##_##f5)), \ 00525 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00526 BF_##reg##_##f2(v2) | \ 00527 BF_##reg##_##f3(v3) | \ 00528 BF_##reg##_##f4(v4) | \ 00529 BF_##reg##_##f5(v5)))) 00530 00531 #define BFn_CS6n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \ 00532 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00533 BM_##reg##_##f2 | \ 00534 BM_##reg##_##f3 | \ 00535 BM_##reg##_##f4 | \ 00536 BM_##reg##_##f5 | \ 00537 BM_##reg##_##f6)), \ 00538 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00539 BF_##reg##_##f2(v2) | \ 00540 BF_##reg##_##f3(v3) | \ 00541 BF_##reg##_##f4(v4) | \ 00542 BF_##reg##_##f5(v5) | \ 00543 BF_##reg##_##f6(v6)))) 00544 00545 #define BFn_CS7n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \ 00546 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00547 BM_##reg##_##f2 | \ 00548 BM_##reg##_##f3 | \ 00549 BM_##reg##_##f4 | \ 00550 BM_##reg##_##f5 | \ 00551 BM_##reg##_##f6 | \ 00552 BM_##reg##_##f7)), \ 00553 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00554 BF_##reg##_##f2(v2) | \ 00555 BF_##reg##_##f3(v3) | \ 00556 BF_##reg##_##f4(v4) | \ 00557 BF_##reg##_##f5(v5) | \ 00558 BF_##reg##_##f6(v6) | \ 00559 BF_##reg##_##f7(v7)))) 00560 00561 #define BFn_CS8n(reg, blk, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \ 00562 (HW_##reg##_CLR(blk, n, (BM_##reg##_##f1 | \ 00563 BM_##reg##_##f2 | \ 00564 BM_##reg##_##f3 | \ 00565 BM_##reg##_##f4 | \ 00566 BM_##reg##_##f5 | \ 00567 BM_##reg##_##f6 | \ 00568 BM_##reg##_##f7 | \ 00569 BM_##reg##_##f8)), \ 00570 HW_##reg##_SET(blk, n, (BF_##reg##_##f1(v1) | \ 00571 BF_##reg##_##f2(v2) | \ 00572 BF_##reg##_##f3(v3) | \ 00573 BF_##reg##_##f4(v4) | \ 00574 BF_##reg##_##f5(v5) | \ 00575 BF_##reg##_##f6(v6) | \ 00576 BF_##reg##_##f7(v7) | \ 00577 BF_##reg##_##f8(v8)))) 00578 00579 #endif /* _FSL_BITACCESS_H */ 00580 00581 /******************************************************************************/
Generated on Sat Aug 27 2022 17:08:59 by
1.7.2