MK64F12_wdog.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_WDOG_REGISTERS_H__
00088 #define __HW_WDOG_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 WDOG
00095  *
00096  * Generation 2008 Watchdog Timer
00097  *
00098  * Registers defined in this header file:
00099  * - HW_WDOG_STCTRLH - Watchdog Status and Control Register High
00100  * - HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
00101  * - HW_WDOG_TOVALH - Watchdog Time-out Value Register High
00102  * - HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
00103  * - HW_WDOG_WINH - Watchdog Window Register High
00104  * - HW_WDOG_WINL - Watchdog Window Register Low
00105  * - HW_WDOG_REFRESH - Watchdog Refresh register
00106  * - HW_WDOG_UNLOCK - Watchdog Unlock register
00107  * - HW_WDOG_TMROUTH - Watchdog Timer Output Register High
00108  * - HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
00109  * - HW_WDOG_RSTCNT - Watchdog Reset Count register
00110  * - HW_WDOG_PRESC - Watchdog Prescaler register
00111  *
00112  * - hw_wdog_t - Struct containing all module registers.
00113  */
00114 
00115 #define HW_WDOG_INSTANCE_COUNT (1U) /*!< Number of instances of the WDOG module. */
00116 
00117 /*******************************************************************************
00118  * HW_WDOG_STCTRLH - Watchdog Status and Control Register High
00119  ******************************************************************************/
00120 
00121 /*!
00122  * @brief HW_WDOG_STCTRLH - Watchdog Status and Control Register High (RW)
00123  *
00124  * Reset value: 0x01D3U
00125  */
00126 typedef union _hw_wdog_stctrlh
00127 {
00128     uint16_t U;
00129     struct _hw_wdog_stctrlh_bitfields
00130     {
00131         uint16_t WDOGEN : 1;           /*!< [0]  */
00132         uint16_t CLKSRC : 1;           /*!< [1]  */
00133         uint16_t IRQRSTEN : 1;         /*!< [2]  */
00134         uint16_t WINEN : 1;            /*!< [3]  */
00135         uint16_t ALLOWUPDATE : 1;      /*!< [4]  */
00136         uint16_t DBGEN : 1;            /*!< [5]  */
00137         uint16_t STOPEN : 1;           /*!< [6]  */
00138         uint16_t WAITEN : 1;           /*!< [7]  */
00139         uint16_t RESERVED0 : 2;        /*!< [9:8]  */
00140         uint16_t TESTWDOG : 1;         /*!< [10]  */
00141         uint16_t TESTSEL : 1;          /*!< [11]  */
00142         uint16_t BYTESEL : 2;          /*!< [13:12]  */
00143         uint16_t DISTESTWDOG : 1;      /*!< [14]  */
00144         uint16_t RESERVED1 : 1;        /*!< [15]  */
00145     } B;
00146 } hw_wdog_stctrlh_t;
00147 
00148 /*!
00149  * @name Constants and macros for entire WDOG_STCTRLH register
00150  */
00151 /*@{*/
00152 #define HW_WDOG_STCTRLH_ADDR(x)  ((x) + 0x0U)
00153 
00154 #define HW_WDOG_STCTRLH(x)       (*(__IO hw_wdog_stctrlh_t *) HW_WDOG_STCTRLH_ADDR(x))
00155 #define HW_WDOG_STCTRLH_RD(x)    (ADDRESS_READ(hw_wdog_stctrlh_t, HW_WDOG_STCTRLH_ADDR(x)))
00156 #define HW_WDOG_STCTRLH_WR(x, v) (ADDRESS_WRITE(hw_wdog_stctrlh_t, HW_WDOG_STCTRLH_ADDR(x), v))
00157 #define HW_WDOG_STCTRLH_SET(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) |  (v)))
00158 #define HW_WDOG_STCTRLH_CLR(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) & ~(v)))
00159 #define HW_WDOG_STCTRLH_TOG(x, v) (HW_WDOG_STCTRLH_WR(x, HW_WDOG_STCTRLH_RD(x) ^  (v)))
00160 /*@}*/
00161 
00162 /*
00163  * Constants & macros for individual WDOG_STCTRLH bitfields
00164  */
00165 
00166 /*!
00167  * @name Register WDOG_STCTRLH, field WDOGEN[0] (RW)
00168  *
00169  * Enables or disables the WDOG's operation. In the disabled state, the watchdog
00170  * timer is kept in the reset state, but the other exception conditions can
00171  * still trigger a reset/interrupt. A change in the value of this bit must be held
00172  * for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
00173  *
00174  * Values:
00175  * - 0 - WDOG is disabled.
00176  * - 1 - WDOG is enabled.
00177  */
00178 /*@{*/
00179 #define BP_WDOG_STCTRLH_WDOGEN (0U)        /*!< Bit position for WDOG_STCTRLH_WDOGEN. */
00180 #define BM_WDOG_STCTRLH_WDOGEN (0x0001U)   /*!< Bit mask for WDOG_STCTRLH_WDOGEN. */
00181 #define BS_WDOG_STCTRLH_WDOGEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WDOGEN. */
00182 
00183 /*! @brief Read current value of the WDOG_STCTRLH_WDOGEN field. */
00184 #define BR_WDOG_STCTRLH_WDOGEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN)))
00185 
00186 /*! @brief Format value for bitfield WDOG_STCTRLH_WDOGEN. */
00187 #define BF_WDOG_STCTRLH_WDOGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WDOGEN) & BM_WDOG_STCTRLH_WDOGEN)
00188 
00189 /*! @brief Set the WDOGEN field to a new value. */
00190 #define BW_WDOG_STCTRLH_WDOGEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WDOGEN), v))
00191 /*@}*/
00192 
00193 /*!
00194  * @name Register WDOG_STCTRLH, field CLKSRC[1] (RW)
00195  *
00196  * Selects clock source for the WDOG timer and other internal timing operations.
00197  *
00198  * Values:
00199  * - 0 - WDOG clock sourced from LPO .
00200  * - 1 - WDOG clock sourced from alternate clock source.
00201  */
00202 /*@{*/
00203 #define BP_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit position for WDOG_STCTRLH_CLKSRC. */
00204 #define BM_WDOG_STCTRLH_CLKSRC (0x0002U)   /*!< Bit mask for WDOG_STCTRLH_CLKSRC. */
00205 #define BS_WDOG_STCTRLH_CLKSRC (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_CLKSRC. */
00206 
00207 /*! @brief Read current value of the WDOG_STCTRLH_CLKSRC field. */
00208 #define BR_WDOG_STCTRLH_CLKSRC(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC)))
00209 
00210 /*! @brief Format value for bitfield WDOG_STCTRLH_CLKSRC. */
00211 #define BF_WDOG_STCTRLH_CLKSRC(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_CLKSRC) & BM_WDOG_STCTRLH_CLKSRC)
00212 
00213 /*! @brief Set the CLKSRC field to a new value. */
00214 #define BW_WDOG_STCTRLH_CLKSRC(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_CLKSRC), v))
00215 /*@}*/
00216 
00217 /*!
00218  * @name Register WDOG_STCTRLH, field IRQRSTEN[2] (RW)
00219  *
00220  * Used to enable the debug breadcrumbs feature. A change in this bit is updated
00221  * immediately, as opposed to updating after WCT.
00222  *
00223  * Values:
00224  * - 0 - WDOG time-out generates reset only.
00225  * - 1 - WDOG time-out initially generates an interrupt. After WCT, it generates
00226  *     a reset.
00227  */
00228 /*@{*/
00229 #define BP_WDOG_STCTRLH_IRQRSTEN (2U)      /*!< Bit position for WDOG_STCTRLH_IRQRSTEN. */
00230 #define BM_WDOG_STCTRLH_IRQRSTEN (0x0004U) /*!< Bit mask for WDOG_STCTRLH_IRQRSTEN. */
00231 #define BS_WDOG_STCTRLH_IRQRSTEN (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_IRQRSTEN. */
00232 
00233 /*! @brief Read current value of the WDOG_STCTRLH_IRQRSTEN field. */
00234 #define BR_WDOG_STCTRLH_IRQRSTEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN)))
00235 
00236 /*! @brief Format value for bitfield WDOG_STCTRLH_IRQRSTEN. */
00237 #define BF_WDOG_STCTRLH_IRQRSTEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_IRQRSTEN) & BM_WDOG_STCTRLH_IRQRSTEN)
00238 
00239 /*! @brief Set the IRQRSTEN field to a new value. */
00240 #define BW_WDOG_STCTRLH_IRQRSTEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_IRQRSTEN), v))
00241 /*@}*/
00242 
00243 /*!
00244  * @name Register WDOG_STCTRLH, field WINEN[3] (RW)
00245  *
00246  * Enables Windowing mode.
00247  *
00248  * Values:
00249  * - 0 - Windowing mode is disabled.
00250  * - 1 - Windowing mode is enabled.
00251  */
00252 /*@{*/
00253 #define BP_WDOG_STCTRLH_WINEN (3U)         /*!< Bit position for WDOG_STCTRLH_WINEN. */
00254 #define BM_WDOG_STCTRLH_WINEN (0x0008U)    /*!< Bit mask for WDOG_STCTRLH_WINEN. */
00255 #define BS_WDOG_STCTRLH_WINEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_WINEN. */
00256 
00257 /*! @brief Read current value of the WDOG_STCTRLH_WINEN field. */
00258 #define BR_WDOG_STCTRLH_WINEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN)))
00259 
00260 /*! @brief Format value for bitfield WDOG_STCTRLH_WINEN. */
00261 #define BF_WDOG_STCTRLH_WINEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WINEN) & BM_WDOG_STCTRLH_WINEN)
00262 
00263 /*! @brief Set the WINEN field to a new value. */
00264 #define BW_WDOG_STCTRLH_WINEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WINEN), v))
00265 /*@}*/
00266 
00267 /*!
00268  * @name Register WDOG_STCTRLH, field ALLOWUPDATE[4] (RW)
00269  *
00270  * Enables updates to watchdog write-once registers, after the reset-triggered
00271  * initial configuration window (WCT) closes, through unlock sequence.
00272  *
00273  * Values:
00274  * - 0 - No further updates allowed to WDOG write-once registers.
00275  * - 1 - WDOG write-once registers can be unlocked for updating.
00276  */
00277 /*@{*/
00278 #define BP_WDOG_STCTRLH_ALLOWUPDATE (4U)   /*!< Bit position for WDOG_STCTRLH_ALLOWUPDATE. */
00279 #define BM_WDOG_STCTRLH_ALLOWUPDATE (0x0010U) /*!< Bit mask for WDOG_STCTRLH_ALLOWUPDATE. */
00280 #define BS_WDOG_STCTRLH_ALLOWUPDATE (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_ALLOWUPDATE. */
00281 
00282 /*! @brief Read current value of the WDOG_STCTRLH_ALLOWUPDATE field. */
00283 #define BR_WDOG_STCTRLH_ALLOWUPDATE(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE)))
00284 
00285 /*! @brief Format value for bitfield WDOG_STCTRLH_ALLOWUPDATE. */
00286 #define BF_WDOG_STCTRLH_ALLOWUPDATE(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_ALLOWUPDATE) & BM_WDOG_STCTRLH_ALLOWUPDATE)
00287 
00288 /*! @brief Set the ALLOWUPDATE field to a new value. */
00289 #define BW_WDOG_STCTRLH_ALLOWUPDATE(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_ALLOWUPDATE), v))
00290 /*@}*/
00291 
00292 /*!
00293  * @name Register WDOG_STCTRLH, field DBGEN[5] (RW)
00294  *
00295  * Enables or disables WDOG in Debug mode.
00296  *
00297  * Values:
00298  * - 0 - WDOG is disabled in CPU Debug mode.
00299  * - 1 - WDOG is enabled in CPU Debug mode.
00300  */
00301 /*@{*/
00302 #define BP_WDOG_STCTRLH_DBGEN (5U)         /*!< Bit position for WDOG_STCTRLH_DBGEN. */
00303 #define BM_WDOG_STCTRLH_DBGEN (0x0020U)    /*!< Bit mask for WDOG_STCTRLH_DBGEN. */
00304 #define BS_WDOG_STCTRLH_DBGEN (1U)         /*!< Bit field size in bits for WDOG_STCTRLH_DBGEN. */
00305 
00306 /*! @brief Read current value of the WDOG_STCTRLH_DBGEN field. */
00307 #define BR_WDOG_STCTRLH_DBGEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN)))
00308 
00309 /*! @brief Format value for bitfield WDOG_STCTRLH_DBGEN. */
00310 #define BF_WDOG_STCTRLH_DBGEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DBGEN) & BM_WDOG_STCTRLH_DBGEN)
00311 
00312 /*! @brief Set the DBGEN field to a new value. */
00313 #define BW_WDOG_STCTRLH_DBGEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DBGEN), v))
00314 /*@}*/
00315 
00316 /*!
00317  * @name Register WDOG_STCTRLH, field STOPEN[6] (RW)
00318  *
00319  * Enables or disables WDOG in Stop mode.
00320  *
00321  * Values:
00322  * - 0 - WDOG is disabled in CPU Stop mode.
00323  * - 1 - WDOG is enabled in CPU Stop mode.
00324  */
00325 /*@{*/
00326 #define BP_WDOG_STCTRLH_STOPEN (6U)        /*!< Bit position for WDOG_STCTRLH_STOPEN. */
00327 #define BM_WDOG_STCTRLH_STOPEN (0x0040U)   /*!< Bit mask for WDOG_STCTRLH_STOPEN. */
00328 #define BS_WDOG_STCTRLH_STOPEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_STOPEN. */
00329 
00330 /*! @brief Read current value of the WDOG_STCTRLH_STOPEN field. */
00331 #define BR_WDOG_STCTRLH_STOPEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN)))
00332 
00333 /*! @brief Format value for bitfield WDOG_STCTRLH_STOPEN. */
00334 #define BF_WDOG_STCTRLH_STOPEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_STOPEN) & BM_WDOG_STCTRLH_STOPEN)
00335 
00336 /*! @brief Set the STOPEN field to a new value. */
00337 #define BW_WDOG_STCTRLH_STOPEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_STOPEN), v))
00338 /*@}*/
00339 
00340 /*!
00341  * @name Register WDOG_STCTRLH, field WAITEN[7] (RW)
00342  *
00343  * Enables or disables WDOG in Wait mode.
00344  *
00345  * Values:
00346  * - 0 - WDOG is disabled in CPU Wait mode.
00347  * - 1 - WDOG is enabled in CPU Wait mode.
00348  */
00349 /*@{*/
00350 #define BP_WDOG_STCTRLH_WAITEN (7U)        /*!< Bit position for WDOG_STCTRLH_WAITEN. */
00351 #define BM_WDOG_STCTRLH_WAITEN (0x0080U)   /*!< Bit mask for WDOG_STCTRLH_WAITEN. */
00352 #define BS_WDOG_STCTRLH_WAITEN (1U)        /*!< Bit field size in bits for WDOG_STCTRLH_WAITEN. */
00353 
00354 /*! @brief Read current value of the WDOG_STCTRLH_WAITEN field. */
00355 #define BR_WDOG_STCTRLH_WAITEN(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN)))
00356 
00357 /*! @brief Format value for bitfield WDOG_STCTRLH_WAITEN. */
00358 #define BF_WDOG_STCTRLH_WAITEN(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_WAITEN) & BM_WDOG_STCTRLH_WAITEN)
00359 
00360 /*! @brief Set the WAITEN field to a new value. */
00361 #define BW_WDOG_STCTRLH_WAITEN(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_WAITEN), v))
00362 /*@}*/
00363 
00364 /*!
00365  * @name Register WDOG_STCTRLH, field TESTWDOG[10] (RW)
00366  *
00367  * Puts the watchdog in the functional test mode. In this mode, the watchdog
00368  * timer and the associated compare and reset generation logic is tested for correct
00369  * operation. The clock for the timer is switched from the main watchdog clock
00370  * to the fast clock input for watchdog functional test. The TESTSEL bit selects
00371  * the test to be run.
00372  */
00373 /*@{*/
00374 #define BP_WDOG_STCTRLH_TESTWDOG (10U)     /*!< Bit position for WDOG_STCTRLH_TESTWDOG. */
00375 #define BM_WDOG_STCTRLH_TESTWDOG (0x0400U) /*!< Bit mask for WDOG_STCTRLH_TESTWDOG. */
00376 #define BS_WDOG_STCTRLH_TESTWDOG (1U)      /*!< Bit field size in bits for WDOG_STCTRLH_TESTWDOG. */
00377 
00378 /*! @brief Read current value of the WDOG_STCTRLH_TESTWDOG field. */
00379 #define BR_WDOG_STCTRLH_TESTWDOG(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG)))
00380 
00381 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTWDOG. */
00382 #define BF_WDOG_STCTRLH_TESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTWDOG) & BM_WDOG_STCTRLH_TESTWDOG)
00383 
00384 /*! @brief Set the TESTWDOG field to a new value. */
00385 #define BW_WDOG_STCTRLH_TESTWDOG(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTWDOG), v))
00386 /*@}*/
00387 
00388 /*!
00389  * @name Register WDOG_STCTRLH, field TESTSEL[11] (RW)
00390  *
00391  * Effective only if TESTWDOG is set. Selects the test to be run on the watchdog
00392  * timer.
00393  *
00394  * Values:
00395  * - 0 - Quick test. The timer runs in normal operation. You can load a small
00396  *     time-out value to do a quick test.
00397  * - 1 - Byte test. Puts the timer in the byte test mode where individual bytes
00398  *     of the timer are enabled for operation and are compared for time-out
00399  *     against the corresponding byte of the programmed time-out value. Select the
00400  *     byte through BYTESEL[1:0] for testing.
00401  */
00402 /*@{*/
00403 #define BP_WDOG_STCTRLH_TESTSEL (11U)      /*!< Bit position for WDOG_STCTRLH_TESTSEL. */
00404 #define BM_WDOG_STCTRLH_TESTSEL (0x0800U)  /*!< Bit mask for WDOG_STCTRLH_TESTSEL. */
00405 #define BS_WDOG_STCTRLH_TESTSEL (1U)       /*!< Bit field size in bits for WDOG_STCTRLH_TESTSEL. */
00406 
00407 /*! @brief Read current value of the WDOG_STCTRLH_TESTSEL field. */
00408 #define BR_WDOG_STCTRLH_TESTSEL(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL)))
00409 
00410 /*! @brief Format value for bitfield WDOG_STCTRLH_TESTSEL. */
00411 #define BF_WDOG_STCTRLH_TESTSEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_TESTSEL) & BM_WDOG_STCTRLH_TESTSEL)
00412 
00413 /*! @brief Set the TESTSEL field to a new value. */
00414 #define BW_WDOG_STCTRLH_TESTSEL(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_TESTSEL), v))
00415 /*@}*/
00416 
00417 /*!
00418  * @name Register WDOG_STCTRLH, field BYTESEL[13:12] (RW)
00419  *
00420  * This 2-bit field selects the byte to be tested when the watchdog is in the
00421  * byte test mode.
00422  *
00423  * Values:
00424  * - 00 - Byte 0 selected
00425  * - 01 - Byte 1 selected
00426  * - 10 - Byte 2 selected
00427  * - 11 - Byte 3 selected
00428  */
00429 /*@{*/
00430 #define BP_WDOG_STCTRLH_BYTESEL (12U)      /*!< Bit position for WDOG_STCTRLH_BYTESEL. */
00431 #define BM_WDOG_STCTRLH_BYTESEL (0x3000U)  /*!< Bit mask for WDOG_STCTRLH_BYTESEL. */
00432 #define BS_WDOG_STCTRLH_BYTESEL (2U)       /*!< Bit field size in bits for WDOG_STCTRLH_BYTESEL. */
00433 
00434 /*! @brief Read current value of the WDOG_STCTRLH_BYTESEL field. */
00435 #define BR_WDOG_STCTRLH_BYTESEL(x) (UNION_READ(hw_wdog_stctrlh_t, HW_WDOG_STCTRLH_ADDR(x), U, B.BYTESEL))
00436 
00437 /*! @brief Format value for bitfield WDOG_STCTRLH_BYTESEL. */
00438 #define BF_WDOG_STCTRLH_BYTESEL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_BYTESEL) & BM_WDOG_STCTRLH_BYTESEL)
00439 
00440 /*! @brief Set the BYTESEL field to a new value. */
00441 #define BW_WDOG_STCTRLH_BYTESEL(x, v) (HW_WDOG_STCTRLH_WR(x, (HW_WDOG_STCTRLH_RD(x) & ~BM_WDOG_STCTRLH_BYTESEL) | BF_WDOG_STCTRLH_BYTESEL(v)))
00442 /*@}*/
00443 
00444 /*!
00445  * @name Register WDOG_STCTRLH, field DISTESTWDOG[14] (RW)
00446  *
00447  * Allows the WDOG's functional test mode to be disabled permanently. After it
00448  * is set, it can only be cleared by a reset. It cannot be unlocked for editing
00449  * after it is set.
00450  *
00451  * Values:
00452  * - 0 - WDOG functional test mode is not disabled.
00453  * - 1 - WDOG functional test mode is disabled permanently until reset.
00454  */
00455 /*@{*/
00456 #define BP_WDOG_STCTRLH_DISTESTWDOG (14U)  /*!< Bit position for WDOG_STCTRLH_DISTESTWDOG. */
00457 #define BM_WDOG_STCTRLH_DISTESTWDOG (0x4000U) /*!< Bit mask for WDOG_STCTRLH_DISTESTWDOG. */
00458 #define BS_WDOG_STCTRLH_DISTESTWDOG (1U)   /*!< Bit field size in bits for WDOG_STCTRLH_DISTESTWDOG. */
00459 
00460 /*! @brief Read current value of the WDOG_STCTRLH_DISTESTWDOG field. */
00461 #define BR_WDOG_STCTRLH_DISTESTWDOG(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG)))
00462 
00463 /*! @brief Format value for bitfield WDOG_STCTRLH_DISTESTWDOG. */
00464 #define BF_WDOG_STCTRLH_DISTESTWDOG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLH_DISTESTWDOG) & BM_WDOG_STCTRLH_DISTESTWDOG)
00465 
00466 /*! @brief Set the DISTESTWDOG field to a new value. */
00467 #define BW_WDOG_STCTRLH_DISTESTWDOG(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLH_ADDR(x), BP_WDOG_STCTRLH_DISTESTWDOG), v))
00468 /*@}*/
00469 
00470 /*******************************************************************************
00471  * HW_WDOG_STCTRLL - Watchdog Status and Control Register Low
00472  ******************************************************************************/
00473 
00474 /*!
00475  * @brief HW_WDOG_STCTRLL - Watchdog Status and Control Register Low (RW)
00476  *
00477  * Reset value: 0x0001U
00478  */
00479 typedef union _hw_wdog_stctrll
00480 {
00481     uint16_t U;
00482     struct _hw_wdog_stctrll_bitfields
00483     {
00484         uint16_t RESERVED0 : 15;       /*!< [14:0]  */
00485         uint16_t INTFLG : 1;           /*!< [15]  */
00486     } B;
00487 } hw_wdog_stctrll_t;
00488 
00489 /*!
00490  * @name Constants and macros for entire WDOG_STCTRLL register
00491  */
00492 /*@{*/
00493 #define HW_WDOG_STCTRLL_ADDR(x)  ((x) + 0x2U)
00494 
00495 #define HW_WDOG_STCTRLL(x)       (*(__IO hw_wdog_stctrll_t *) HW_WDOG_STCTRLL_ADDR(x))
00496 #define HW_WDOG_STCTRLL_RD(x)    (ADDRESS_READ(hw_wdog_stctrll_t, HW_WDOG_STCTRLL_ADDR(x)))
00497 #define HW_WDOG_STCTRLL_WR(x, v) (ADDRESS_WRITE(hw_wdog_stctrll_t, HW_WDOG_STCTRLL_ADDR(x), v))
00498 #define HW_WDOG_STCTRLL_SET(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) |  (v)))
00499 #define HW_WDOG_STCTRLL_CLR(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) & ~(v)))
00500 #define HW_WDOG_STCTRLL_TOG(x, v) (HW_WDOG_STCTRLL_WR(x, HW_WDOG_STCTRLL_RD(x) ^  (v)))
00501 /*@}*/
00502 
00503 /*
00504  * Constants & macros for individual WDOG_STCTRLL bitfields
00505  */
00506 
00507 /*!
00508  * @name Register WDOG_STCTRLL, field INTFLG[15] (RW)
00509  *
00510  * Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a
00511  * precondition to set this flag. INTFLG = 1 results in an interrupt being issued
00512  * followed by a reset, WCT later. The interrupt can be cleared by writing 1 to this
00513  * bit. It also gets cleared on a system reset.
00514  */
00515 /*@{*/
00516 #define BP_WDOG_STCTRLL_INTFLG (15U)       /*!< Bit position for WDOG_STCTRLL_INTFLG. */
00517 #define BM_WDOG_STCTRLL_INTFLG (0x8000U)   /*!< Bit mask for WDOG_STCTRLL_INTFLG. */
00518 #define BS_WDOG_STCTRLL_INTFLG (1U)        /*!< Bit field size in bits for WDOG_STCTRLL_INTFLG. */
00519 
00520 /*! @brief Read current value of the WDOG_STCTRLL_INTFLG field. */
00521 #define BR_WDOG_STCTRLL_INTFLG(x) (ADDRESS_READ(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG)))
00522 
00523 /*! @brief Format value for bitfield WDOG_STCTRLL_INTFLG. */
00524 #define BF_WDOG_STCTRLL_INTFLG(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_STCTRLL_INTFLG) & BM_WDOG_STCTRLL_INTFLG)
00525 
00526 /*! @brief Set the INTFLG field to a new value. */
00527 #define BW_WDOG_STCTRLL_INTFLG(x, v) (ADDRESS_WRITE(uint16_t, BITBAND_ADDRESS16(HW_WDOG_STCTRLL_ADDR(x), BP_WDOG_STCTRLL_INTFLG), v))
00528 /*@}*/
00529 
00530 /*******************************************************************************
00531  * HW_WDOG_TOVALH - Watchdog Time-out Value Register High
00532  ******************************************************************************/
00533 
00534 /*!
00535  * @brief HW_WDOG_TOVALH - Watchdog Time-out Value Register High (RW)
00536  *
00537  * Reset value: 0x004CU
00538  */
00539 typedef union _hw_wdog_tovalh
00540 {
00541     uint16_t U;
00542     struct _hw_wdog_tovalh_bitfields
00543     {
00544         uint16_t TOVALHIGH : 16;       /*!< [15:0]  */
00545     } B;
00546 } hw_wdog_tovalh_t;
00547 
00548 /*!
00549  * @name Constants and macros for entire WDOG_TOVALH register
00550  */
00551 /*@{*/
00552 #define HW_WDOG_TOVALH_ADDR(x)   ((x) + 0x4U)
00553 
00554 #define HW_WDOG_TOVALH(x)        (*(__IO hw_wdog_tovalh_t *) HW_WDOG_TOVALH_ADDR(x))
00555 #define HW_WDOG_TOVALH_RD(x)     (ADDRESS_READ(hw_wdog_tovalh_t, HW_WDOG_TOVALH_ADDR(x)))
00556 #define HW_WDOG_TOVALH_WR(x, v)  (ADDRESS_WRITE(hw_wdog_tovalh_t, HW_WDOG_TOVALH_ADDR(x), v))
00557 #define HW_WDOG_TOVALH_SET(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) |  (v)))
00558 #define HW_WDOG_TOVALH_CLR(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) & ~(v)))
00559 #define HW_WDOG_TOVALH_TOG(x, v) (HW_WDOG_TOVALH_WR(x, HW_WDOG_TOVALH_RD(x) ^  (v)))
00560 /*@}*/
00561 
00562 /*
00563  * Constants & macros for individual WDOG_TOVALH bitfields
00564  */
00565 
00566 /*!
00567  * @name Register WDOG_TOVALH, field TOVALHIGH[15:0] (RW)
00568  *
00569  * Defines the upper 16 bits of the 32-bit time-out value for the watchdog
00570  * timer. It is defined in terms of cycles of the watchdog clock.
00571  */
00572 /*@{*/
00573 #define BP_WDOG_TOVALH_TOVALHIGH (0U)      /*!< Bit position for WDOG_TOVALH_TOVALHIGH. */
00574 #define BM_WDOG_TOVALH_TOVALHIGH (0xFFFFU) /*!< Bit mask for WDOG_TOVALH_TOVALHIGH. */
00575 #define BS_WDOG_TOVALH_TOVALHIGH (16U)     /*!< Bit field size in bits for WDOG_TOVALH_TOVALHIGH. */
00576 
00577 /*! @brief Read current value of the WDOG_TOVALH_TOVALHIGH field. */
00578 #define BR_WDOG_TOVALH_TOVALHIGH(x) (HW_WDOG_TOVALH(x).U)
00579 
00580 /*! @brief Format value for bitfield WDOG_TOVALH_TOVALHIGH. */
00581 #define BF_WDOG_TOVALH_TOVALHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALH_TOVALHIGH) & BM_WDOG_TOVALH_TOVALHIGH)
00582 
00583 /*! @brief Set the TOVALHIGH field to a new value. */
00584 #define BW_WDOG_TOVALH_TOVALHIGH(x, v) (HW_WDOG_TOVALH_WR(x, v))
00585 /*@}*/
00586 
00587 /*******************************************************************************
00588  * HW_WDOG_TOVALL - Watchdog Time-out Value Register Low
00589  ******************************************************************************/
00590 
00591 /*!
00592  * @brief HW_WDOG_TOVALL - Watchdog Time-out Value Register Low (RW)
00593  *
00594  * Reset value: 0x4B4CU
00595  *
00596  * The time-out value of the watchdog must be set to a minimum of four watchdog
00597  * clock cycles. This is to take into account the delay in new settings taking
00598  * effect in the watchdog clock domain.
00599  */
00600 typedef union _hw_wdog_tovall
00601 {
00602     uint16_t U;
00603     struct _hw_wdog_tovall_bitfields
00604     {
00605         uint16_t TOVALLOW : 16;        /*!< [15:0]  */
00606     } B;
00607 } hw_wdog_tovall_t;
00608 
00609 /*!
00610  * @name Constants and macros for entire WDOG_TOVALL register
00611  */
00612 /*@{*/
00613 #define HW_WDOG_TOVALL_ADDR(x)   ((x) + 0x6U)
00614 
00615 #define HW_WDOG_TOVALL(x)        (*(__IO hw_wdog_tovall_t *) HW_WDOG_TOVALL_ADDR(x))
00616 #define HW_WDOG_TOVALL_RD(x)     (ADDRESS_READ(hw_wdog_tovall_t, HW_WDOG_TOVALL_ADDR(x)))
00617 #define HW_WDOG_TOVALL_WR(x, v)  (ADDRESS_WRITE(hw_wdog_tovall_t, HW_WDOG_TOVALL_ADDR(x), v))
00618 #define HW_WDOG_TOVALL_SET(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) |  (v)))
00619 #define HW_WDOG_TOVALL_CLR(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) & ~(v)))
00620 #define HW_WDOG_TOVALL_TOG(x, v) (HW_WDOG_TOVALL_WR(x, HW_WDOG_TOVALL_RD(x) ^  (v)))
00621 /*@}*/
00622 
00623 /*
00624  * Constants & macros for individual WDOG_TOVALL bitfields
00625  */
00626 
00627 /*!
00628  * @name Register WDOG_TOVALL, field TOVALLOW[15:0] (RW)
00629  *
00630  * Defines the lower 16 bits of the 32-bit time-out value for the watchdog
00631  * timer. It is defined in terms of cycles of the watchdog clock.
00632  */
00633 /*@{*/
00634 #define BP_WDOG_TOVALL_TOVALLOW (0U)       /*!< Bit position for WDOG_TOVALL_TOVALLOW. */
00635 #define BM_WDOG_TOVALL_TOVALLOW (0xFFFFU)  /*!< Bit mask for WDOG_TOVALL_TOVALLOW. */
00636 #define BS_WDOG_TOVALL_TOVALLOW (16U)      /*!< Bit field size in bits for WDOG_TOVALL_TOVALLOW. */
00637 
00638 /*! @brief Read current value of the WDOG_TOVALL_TOVALLOW field. */
00639 #define BR_WDOG_TOVALL_TOVALLOW(x) (HW_WDOG_TOVALL(x).U)
00640 
00641 /*! @brief Format value for bitfield WDOG_TOVALL_TOVALLOW. */
00642 #define BF_WDOG_TOVALL_TOVALLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TOVALL_TOVALLOW) & BM_WDOG_TOVALL_TOVALLOW)
00643 
00644 /*! @brief Set the TOVALLOW field to a new value. */
00645 #define BW_WDOG_TOVALL_TOVALLOW(x, v) (HW_WDOG_TOVALL_WR(x, v))
00646 /*@}*/
00647 
00648 /*******************************************************************************
00649  * HW_WDOG_WINH - Watchdog Window Register High
00650  ******************************************************************************/
00651 
00652 /*!
00653  * @brief HW_WDOG_WINH - Watchdog Window Register High (RW)
00654  *
00655  * Reset value: 0x0000U
00656  *
00657  * You must set the Window Register value lower than the Time-out Value Register.
00658  */
00659 typedef union _hw_wdog_winh
00660 {
00661     uint16_t U;
00662     struct _hw_wdog_winh_bitfields
00663     {
00664         uint16_t WINHIGH : 16;         /*!< [15:0]  */
00665     } B;
00666 } hw_wdog_winh_t;
00667 
00668 /*!
00669  * @name Constants and macros for entire WDOG_WINH register
00670  */
00671 /*@{*/
00672 #define HW_WDOG_WINH_ADDR(x)     ((x) + 0x8U)
00673 
00674 #define HW_WDOG_WINH(x)          (*(__IO hw_wdog_winh_t *) HW_WDOG_WINH_ADDR(x))
00675 #define HW_WDOG_WINH_RD(x)       (ADDRESS_READ(hw_wdog_winh_t, HW_WDOG_WINH_ADDR(x)))
00676 #define HW_WDOG_WINH_WR(x, v)    (ADDRESS_WRITE(hw_wdog_winh_t, HW_WDOG_WINH_ADDR(x), v))
00677 #define HW_WDOG_WINH_SET(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) |  (v)))
00678 #define HW_WDOG_WINH_CLR(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) & ~(v)))
00679 #define HW_WDOG_WINH_TOG(x, v)   (HW_WDOG_WINH_WR(x, HW_WDOG_WINH_RD(x) ^  (v)))
00680 /*@}*/
00681 
00682 /*
00683  * Constants & macros for individual WDOG_WINH bitfields
00684  */
00685 
00686 /*!
00687  * @name Register WDOG_WINH, field WINHIGH[15:0] (RW)
00688  *
00689  * Defines the upper 16 bits of the 32-bit window for the windowed mode of
00690  * operation of the watchdog. It is defined in terms of cycles of the watchdog clock.
00691  * In this mode, the watchdog can be refreshed only when the timer has reached a
00692  * value greater than or equal to this window length. A refresh outside this
00693  * window resets the system or if IRQRSTEN is set, it interrupts and then resets the
00694  * system.
00695  */
00696 /*@{*/
00697 #define BP_WDOG_WINH_WINHIGH (0U)          /*!< Bit position for WDOG_WINH_WINHIGH. */
00698 #define BM_WDOG_WINH_WINHIGH (0xFFFFU)     /*!< Bit mask for WDOG_WINH_WINHIGH. */
00699 #define BS_WDOG_WINH_WINHIGH (16U)         /*!< Bit field size in bits for WDOG_WINH_WINHIGH. */
00700 
00701 /*! @brief Read current value of the WDOG_WINH_WINHIGH field. */
00702 #define BR_WDOG_WINH_WINHIGH(x) (HW_WDOG_WINH(x).U)
00703 
00704 /*! @brief Format value for bitfield WDOG_WINH_WINHIGH. */
00705 #define BF_WDOG_WINH_WINHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINH_WINHIGH) & BM_WDOG_WINH_WINHIGH)
00706 
00707 /*! @brief Set the WINHIGH field to a new value. */
00708 #define BW_WDOG_WINH_WINHIGH(x, v) (HW_WDOG_WINH_WR(x, v))
00709 /*@}*/
00710 
00711 /*******************************************************************************
00712  * HW_WDOG_WINL - Watchdog Window Register Low
00713  ******************************************************************************/
00714 
00715 /*!
00716  * @brief HW_WDOG_WINL - Watchdog Window Register Low (RW)
00717  *
00718  * Reset value: 0x0010U
00719  *
00720  * You must set the Window Register value lower than the Time-out Value Register.
00721  */
00722 typedef union _hw_wdog_winl
00723 {
00724     uint16_t U;
00725     struct _hw_wdog_winl_bitfields
00726     {
00727         uint16_t WINLOW : 16;          /*!< [15:0]  */
00728     } B;
00729 } hw_wdog_winl_t;
00730 
00731 /*!
00732  * @name Constants and macros for entire WDOG_WINL register
00733  */
00734 /*@{*/
00735 #define HW_WDOG_WINL_ADDR(x)     ((x) + 0xAU)
00736 
00737 #define HW_WDOG_WINL(x)          (*(__IO hw_wdog_winl_t *) HW_WDOG_WINL_ADDR(x))
00738 #define HW_WDOG_WINL_RD(x)       (ADDRESS_READ(hw_wdog_winl_t, HW_WDOG_WINL_ADDR(x)))
00739 #define HW_WDOG_WINL_WR(x, v)    (ADDRESS_WRITE(hw_wdog_winl_t, HW_WDOG_WINL_ADDR(x), v))
00740 #define HW_WDOG_WINL_SET(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) |  (v)))
00741 #define HW_WDOG_WINL_CLR(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) & ~(v)))
00742 #define HW_WDOG_WINL_TOG(x, v)   (HW_WDOG_WINL_WR(x, HW_WDOG_WINL_RD(x) ^  (v)))
00743 /*@}*/
00744 
00745 /*
00746  * Constants & macros for individual WDOG_WINL bitfields
00747  */
00748 
00749 /*!
00750  * @name Register WDOG_WINL, field WINLOW[15:0] (RW)
00751  *
00752  * Defines the lower 16 bits of the 32-bit window for the windowed mode of
00753  * operation of the watchdog. It is defined in terms of cycles of the pre-scaled
00754  * watchdog clock. In this mode, the watchdog can be refreshed only when the timer
00755  * reaches a value greater than or equal to this window length value. A refresh
00756  * outside of this window resets the system or if IRQRSTEN is set, it interrupts and
00757  * then resets the system.
00758  */
00759 /*@{*/
00760 #define BP_WDOG_WINL_WINLOW  (0U)          /*!< Bit position for WDOG_WINL_WINLOW. */
00761 #define BM_WDOG_WINL_WINLOW  (0xFFFFU)     /*!< Bit mask for WDOG_WINL_WINLOW. */
00762 #define BS_WDOG_WINL_WINLOW  (16U)         /*!< Bit field size in bits for WDOG_WINL_WINLOW. */
00763 
00764 /*! @brief Read current value of the WDOG_WINL_WINLOW field. */
00765 #define BR_WDOG_WINL_WINLOW(x) (HW_WDOG_WINL(x).U)
00766 
00767 /*! @brief Format value for bitfield WDOG_WINL_WINLOW. */
00768 #define BF_WDOG_WINL_WINLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_WINL_WINLOW) & BM_WDOG_WINL_WINLOW)
00769 
00770 /*! @brief Set the WINLOW field to a new value. */
00771 #define BW_WDOG_WINL_WINLOW(x, v) (HW_WDOG_WINL_WR(x, v))
00772 /*@}*/
00773 
00774 /*******************************************************************************
00775  * HW_WDOG_REFRESH - Watchdog Refresh register
00776  ******************************************************************************/
00777 
00778 /*!
00779  * @brief HW_WDOG_REFRESH - Watchdog Refresh register (RW)
00780  *
00781  * Reset value: 0xB480U
00782  */
00783 typedef union _hw_wdog_refresh
00784 {
00785     uint16_t U;
00786     struct _hw_wdog_refresh_bitfields
00787     {
00788         uint16_t WDOGREFRESH : 16;     /*!< [15:0]  */
00789     } B;
00790 } hw_wdog_refresh_t;
00791 
00792 /*!
00793  * @name Constants and macros for entire WDOG_REFRESH register
00794  */
00795 /*@{*/
00796 #define HW_WDOG_REFRESH_ADDR(x)  ((x) + 0xCU)
00797 
00798 #define HW_WDOG_REFRESH(x)       (*(__IO hw_wdog_refresh_t *) HW_WDOG_REFRESH_ADDR(x))
00799 #define HW_WDOG_REFRESH_RD(x)    (ADDRESS_READ(hw_wdog_refresh_t, HW_WDOG_REFRESH_ADDR(x)))
00800 #define HW_WDOG_REFRESH_WR(x, v) (ADDRESS_WRITE(hw_wdog_refresh_t, HW_WDOG_REFRESH_ADDR(x), v))
00801 #define HW_WDOG_REFRESH_SET(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) |  (v)))
00802 #define HW_WDOG_REFRESH_CLR(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) & ~(v)))
00803 #define HW_WDOG_REFRESH_TOG(x, v) (HW_WDOG_REFRESH_WR(x, HW_WDOG_REFRESH_RD(x) ^  (v)))
00804 /*@}*/
00805 
00806 /*
00807  * Constants & macros for individual WDOG_REFRESH bitfields
00808  */
00809 
00810 /*!
00811  * @name Register WDOG_REFRESH, field WDOGREFRESH[15:0] (RW)
00812  *
00813  * Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20
00814  * bus clock cycles written to this register refreshes the WDOG and prevents it
00815  * from resetting the system. Writing a value other than the above mentioned
00816  * sequence or if the sequence is longer than 20 bus cycles, resets the system, or if
00817  * IRQRSTEN is set, it interrupts and then resets the system.
00818  */
00819 /*@{*/
00820 #define BP_WDOG_REFRESH_WDOGREFRESH (0U)   /*!< Bit position for WDOG_REFRESH_WDOGREFRESH. */
00821 #define BM_WDOG_REFRESH_WDOGREFRESH (0xFFFFU) /*!< Bit mask for WDOG_REFRESH_WDOGREFRESH. */
00822 #define BS_WDOG_REFRESH_WDOGREFRESH (16U)  /*!< Bit field size in bits for WDOG_REFRESH_WDOGREFRESH. */
00823 
00824 /*! @brief Read current value of the WDOG_REFRESH_WDOGREFRESH field. */
00825 #define BR_WDOG_REFRESH_WDOGREFRESH(x) (HW_WDOG_REFRESH(x).U)
00826 
00827 /*! @brief Format value for bitfield WDOG_REFRESH_WDOGREFRESH. */
00828 #define BF_WDOG_REFRESH_WDOGREFRESH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_REFRESH_WDOGREFRESH) & BM_WDOG_REFRESH_WDOGREFRESH)
00829 
00830 /*! @brief Set the WDOGREFRESH field to a new value. */
00831 #define BW_WDOG_REFRESH_WDOGREFRESH(x, v) (HW_WDOG_REFRESH_WR(x, v))
00832 /*@}*/
00833 
00834 /*******************************************************************************
00835  * HW_WDOG_UNLOCK - Watchdog Unlock register
00836  ******************************************************************************/
00837 
00838 /*!
00839  * @brief HW_WDOG_UNLOCK - Watchdog Unlock register (RW)
00840  *
00841  * Reset value: 0xD928U
00842  */
00843 typedef union _hw_wdog_unlock
00844 {
00845     uint16_t U;
00846     struct _hw_wdog_unlock_bitfields
00847     {
00848         uint16_t WDOGUNLOCK : 16;      /*!< [15:0]  */
00849     } B;
00850 } hw_wdog_unlock_t;
00851 
00852 /*!
00853  * @name Constants and macros for entire WDOG_UNLOCK register
00854  */
00855 /*@{*/
00856 #define HW_WDOG_UNLOCK_ADDR(x)   ((x) + 0xEU)
00857 
00858 #define HW_WDOG_UNLOCK(x)        (*(__IO hw_wdog_unlock_t *) HW_WDOG_UNLOCK_ADDR(x))
00859 #define HW_WDOG_UNLOCK_RD(x)     (ADDRESS_READ(hw_wdog_unlock_t, HW_WDOG_UNLOCK_ADDR(x)))
00860 #define HW_WDOG_UNLOCK_WR(x, v)  (ADDRESS_WRITE(hw_wdog_unlock_t, HW_WDOG_UNLOCK_ADDR(x), v))
00861 #define HW_WDOG_UNLOCK_SET(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) |  (v)))
00862 #define HW_WDOG_UNLOCK_CLR(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) & ~(v)))
00863 #define HW_WDOG_UNLOCK_TOG(x, v) (HW_WDOG_UNLOCK_WR(x, HW_WDOG_UNLOCK_RD(x) ^  (v)))
00864 /*@}*/
00865 
00866 /*
00867  * Constants & macros for individual WDOG_UNLOCK bitfields
00868  */
00869 
00870 /*!
00871  * @name Register WDOG_UNLOCK, field WDOGUNLOCK[15:0] (RW)
00872  *
00873  * Writing the unlock sequence values to this register to makes the watchdog
00874  * write-once registers writable again. The required unlock sequence is 0xC520
00875  * followed by 0xD928 within 20 bus clock cycles. A valid unlock sequence opens a
00876  * window equal in length to the WCT within which you can update the registers.
00877  * Writing a value other than the above mentioned sequence or if the sequence is
00878  * longer than 20 bus cycles, resets the system or if IRQRSTEN is set, it interrupts
00879  * and then resets the system. The unlock sequence is effective only if
00880  * ALLOWUPDATE is set.
00881  */
00882 /*@{*/
00883 #define BP_WDOG_UNLOCK_WDOGUNLOCK (0U)     /*!< Bit position for WDOG_UNLOCK_WDOGUNLOCK. */
00884 #define BM_WDOG_UNLOCK_WDOGUNLOCK (0xFFFFU) /*!< Bit mask for WDOG_UNLOCK_WDOGUNLOCK. */
00885 #define BS_WDOG_UNLOCK_WDOGUNLOCK (16U)    /*!< Bit field size in bits for WDOG_UNLOCK_WDOGUNLOCK. */
00886 
00887 /*! @brief Read current value of the WDOG_UNLOCK_WDOGUNLOCK field. */
00888 #define BR_WDOG_UNLOCK_WDOGUNLOCK(x) (HW_WDOG_UNLOCK(x).U)
00889 
00890 /*! @brief Format value for bitfield WDOG_UNLOCK_WDOGUNLOCK. */
00891 #define BF_WDOG_UNLOCK_WDOGUNLOCK(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_UNLOCK_WDOGUNLOCK) & BM_WDOG_UNLOCK_WDOGUNLOCK)
00892 
00893 /*! @brief Set the WDOGUNLOCK field to a new value. */
00894 #define BW_WDOG_UNLOCK_WDOGUNLOCK(x, v) (HW_WDOG_UNLOCK_WR(x, v))
00895 /*@}*/
00896 
00897 /*******************************************************************************
00898  * HW_WDOG_TMROUTH - Watchdog Timer Output Register High
00899  ******************************************************************************/
00900 
00901 /*!
00902  * @brief HW_WDOG_TMROUTH - Watchdog Timer Output Register High (RW)
00903  *
00904  * Reset value: 0x0000U
00905  */
00906 typedef union _hw_wdog_tmrouth
00907 {
00908     uint16_t U;
00909     struct _hw_wdog_tmrouth_bitfields
00910     {
00911         uint16_t TIMEROUTHIGH : 16;    /*!< [15:0]  */
00912     } B;
00913 } hw_wdog_tmrouth_t;
00914 
00915 /*!
00916  * @name Constants and macros for entire WDOG_TMROUTH register
00917  */
00918 /*@{*/
00919 #define HW_WDOG_TMROUTH_ADDR(x)  ((x) + 0x10U)
00920 
00921 #define HW_WDOG_TMROUTH(x)       (*(__IO hw_wdog_tmrouth_t *) HW_WDOG_TMROUTH_ADDR(x))
00922 #define HW_WDOG_TMROUTH_RD(x)    (ADDRESS_READ(hw_wdog_tmrouth_t, HW_WDOG_TMROUTH_ADDR(x)))
00923 #define HW_WDOG_TMROUTH_WR(x, v) (ADDRESS_WRITE(hw_wdog_tmrouth_t, HW_WDOG_TMROUTH_ADDR(x), v))
00924 #define HW_WDOG_TMROUTH_SET(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) |  (v)))
00925 #define HW_WDOG_TMROUTH_CLR(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) & ~(v)))
00926 #define HW_WDOG_TMROUTH_TOG(x, v) (HW_WDOG_TMROUTH_WR(x, HW_WDOG_TMROUTH_RD(x) ^  (v)))
00927 /*@}*/
00928 
00929 /*
00930  * Constants & macros for individual WDOG_TMROUTH bitfields
00931  */
00932 
00933 /*!
00934  * @name Register WDOG_TMROUTH, field TIMEROUTHIGH[15:0] (RW)
00935  *
00936  * Shows the value of the upper 16 bits of the watchdog timer.
00937  */
00938 /*@{*/
00939 #define BP_WDOG_TMROUTH_TIMEROUTHIGH (0U)  /*!< Bit position for WDOG_TMROUTH_TIMEROUTHIGH. */
00940 #define BM_WDOG_TMROUTH_TIMEROUTHIGH (0xFFFFU) /*!< Bit mask for WDOG_TMROUTH_TIMEROUTHIGH. */
00941 #define BS_WDOG_TMROUTH_TIMEROUTHIGH (16U) /*!< Bit field size in bits for WDOG_TMROUTH_TIMEROUTHIGH. */
00942 
00943 /*! @brief Read current value of the WDOG_TMROUTH_TIMEROUTHIGH field. */
00944 #define BR_WDOG_TMROUTH_TIMEROUTHIGH(x) (HW_WDOG_TMROUTH(x).U)
00945 
00946 /*! @brief Format value for bitfield WDOG_TMROUTH_TIMEROUTHIGH. */
00947 #define BF_WDOG_TMROUTH_TIMEROUTHIGH(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTH_TIMEROUTHIGH) & BM_WDOG_TMROUTH_TIMEROUTHIGH)
00948 
00949 /*! @brief Set the TIMEROUTHIGH field to a new value. */
00950 #define BW_WDOG_TMROUTH_TIMEROUTHIGH(x, v) (HW_WDOG_TMROUTH_WR(x, v))
00951 /*@}*/
00952 
00953 /*******************************************************************************
00954  * HW_WDOG_TMROUTL - Watchdog Timer Output Register Low
00955  ******************************************************************************/
00956 
00957 /*!
00958  * @brief HW_WDOG_TMROUTL - Watchdog Timer Output Register Low (RW)
00959  *
00960  * Reset value: 0x0000U
00961  *
00962  * During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of
00963  * the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK
00964  * cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following
00965  * the watchdog timer.
00966  */
00967 typedef union _hw_wdog_tmroutl
00968 {
00969     uint16_t U;
00970     struct _hw_wdog_tmroutl_bitfields
00971     {
00972         uint16_t TIMEROUTLOW : 16;     /*!< [15:0]  */
00973     } B;
00974 } hw_wdog_tmroutl_t;
00975 
00976 /*!
00977  * @name Constants and macros for entire WDOG_TMROUTL register
00978  */
00979 /*@{*/
00980 #define HW_WDOG_TMROUTL_ADDR(x)  ((x) + 0x12U)
00981 
00982 #define HW_WDOG_TMROUTL(x)       (*(__IO hw_wdog_tmroutl_t *) HW_WDOG_TMROUTL_ADDR(x))
00983 #define HW_WDOG_TMROUTL_RD(x)    (ADDRESS_READ(hw_wdog_tmroutl_t, HW_WDOG_TMROUTL_ADDR(x)))
00984 #define HW_WDOG_TMROUTL_WR(x, v) (ADDRESS_WRITE(hw_wdog_tmroutl_t, HW_WDOG_TMROUTL_ADDR(x), v))
00985 #define HW_WDOG_TMROUTL_SET(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) |  (v)))
00986 #define HW_WDOG_TMROUTL_CLR(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) & ~(v)))
00987 #define HW_WDOG_TMROUTL_TOG(x, v) (HW_WDOG_TMROUTL_WR(x, HW_WDOG_TMROUTL_RD(x) ^  (v)))
00988 /*@}*/
00989 
00990 /*
00991  * Constants & macros for individual WDOG_TMROUTL bitfields
00992  */
00993 
00994 /*!
00995  * @name Register WDOG_TMROUTL, field TIMEROUTLOW[15:0] (RW)
00996  *
00997  * Shows the value of the lower 16 bits of the watchdog timer.
00998  */
00999 /*@{*/
01000 #define BP_WDOG_TMROUTL_TIMEROUTLOW (0U)   /*!< Bit position for WDOG_TMROUTL_TIMEROUTLOW. */
01001 #define BM_WDOG_TMROUTL_TIMEROUTLOW (0xFFFFU) /*!< Bit mask for WDOG_TMROUTL_TIMEROUTLOW. */
01002 #define BS_WDOG_TMROUTL_TIMEROUTLOW (16U)  /*!< Bit field size in bits for WDOG_TMROUTL_TIMEROUTLOW. */
01003 
01004 /*! @brief Read current value of the WDOG_TMROUTL_TIMEROUTLOW field. */
01005 #define BR_WDOG_TMROUTL_TIMEROUTLOW(x) (HW_WDOG_TMROUTL(x).U)
01006 
01007 /*! @brief Format value for bitfield WDOG_TMROUTL_TIMEROUTLOW. */
01008 #define BF_WDOG_TMROUTL_TIMEROUTLOW(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_TMROUTL_TIMEROUTLOW) & BM_WDOG_TMROUTL_TIMEROUTLOW)
01009 
01010 /*! @brief Set the TIMEROUTLOW field to a new value. */
01011 #define BW_WDOG_TMROUTL_TIMEROUTLOW(x, v) (HW_WDOG_TMROUTL_WR(x, v))
01012 /*@}*/
01013 
01014 /*******************************************************************************
01015  * HW_WDOG_RSTCNT - Watchdog Reset Count register
01016  ******************************************************************************/
01017 
01018 /*!
01019  * @brief HW_WDOG_RSTCNT - Watchdog Reset Count register (RW)
01020  *
01021  * Reset value: 0x0000U
01022  */
01023 typedef union _hw_wdog_rstcnt
01024 {
01025     uint16_t U;
01026     struct _hw_wdog_rstcnt_bitfields
01027     {
01028         uint16_t RSTCNT : 16;          /*!< [15:0]  */
01029     } B;
01030 } hw_wdog_rstcnt_t;
01031 
01032 /*!
01033  * @name Constants and macros for entire WDOG_RSTCNT register
01034  */
01035 /*@{*/
01036 #define HW_WDOG_RSTCNT_ADDR(x)   ((x) + 0x14U)
01037 
01038 #define HW_WDOG_RSTCNT(x)        (*(__IO hw_wdog_rstcnt_t *) HW_WDOG_RSTCNT_ADDR(x))
01039 #define HW_WDOG_RSTCNT_RD(x)     (ADDRESS_READ(hw_wdog_rstcnt_t, HW_WDOG_RSTCNT_ADDR(x)))
01040 #define HW_WDOG_RSTCNT_WR(x, v)  (ADDRESS_WRITE(hw_wdog_rstcnt_t, HW_WDOG_RSTCNT_ADDR(x), v))
01041 #define HW_WDOG_RSTCNT_SET(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) |  (v)))
01042 #define HW_WDOG_RSTCNT_CLR(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) & ~(v)))
01043 #define HW_WDOG_RSTCNT_TOG(x, v) (HW_WDOG_RSTCNT_WR(x, HW_WDOG_RSTCNT_RD(x) ^  (v)))
01044 /*@}*/
01045 
01046 /*
01047  * Constants & macros for individual WDOG_RSTCNT bitfields
01048  */
01049 
01050 /*!
01051  * @name Register WDOG_RSTCNT, field RSTCNT[15:0] (RW)
01052  *
01053  * Counts the number of times the watchdog resets the system. This register is
01054  * reset only on a POR. Writing 1 to the bit to be cleared enables you to clear
01055  * the contents of this register.
01056  */
01057 /*@{*/
01058 #define BP_WDOG_RSTCNT_RSTCNT (0U)         /*!< Bit position for WDOG_RSTCNT_RSTCNT. */
01059 #define BM_WDOG_RSTCNT_RSTCNT (0xFFFFU)    /*!< Bit mask for WDOG_RSTCNT_RSTCNT. */
01060 #define BS_WDOG_RSTCNT_RSTCNT (16U)        /*!< Bit field size in bits for WDOG_RSTCNT_RSTCNT. */
01061 
01062 /*! @brief Read current value of the WDOG_RSTCNT_RSTCNT field. */
01063 #define BR_WDOG_RSTCNT_RSTCNT(x) (HW_WDOG_RSTCNT(x).U)
01064 
01065 /*! @brief Format value for bitfield WDOG_RSTCNT_RSTCNT. */
01066 #define BF_WDOG_RSTCNT_RSTCNT(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_RSTCNT_RSTCNT) & BM_WDOG_RSTCNT_RSTCNT)
01067 
01068 /*! @brief Set the RSTCNT field to a new value. */
01069 #define BW_WDOG_RSTCNT_RSTCNT(x, v) (HW_WDOG_RSTCNT_WR(x, v))
01070 /*@}*/
01071 
01072 /*******************************************************************************
01073  * HW_WDOG_PRESC - Watchdog Prescaler register
01074  ******************************************************************************/
01075 
01076 /*!
01077  * @brief HW_WDOG_PRESC - Watchdog Prescaler register (RW)
01078  *
01079  * Reset value: 0x0400U
01080  */
01081 typedef union _hw_wdog_presc
01082 {
01083     uint16_t U;
01084     struct _hw_wdog_presc_bitfields
01085     {
01086         uint16_t RESERVED0 : 8;        /*!< [7:0]  */
01087         uint16_t PRESCVAL : 3;         /*!< [10:8]  */
01088         uint16_t RESERVED1 : 5;        /*!< [15:11]  */
01089     } B;
01090 } hw_wdog_presc_t;
01091 
01092 /*!
01093  * @name Constants and macros for entire WDOG_PRESC register
01094  */
01095 /*@{*/
01096 #define HW_WDOG_PRESC_ADDR(x)    ((x) + 0x16U)
01097 
01098 #define HW_WDOG_PRESC(x)         (*(__IO hw_wdog_presc_t *) HW_WDOG_PRESC_ADDR(x))
01099 #define HW_WDOG_PRESC_RD(x)      (ADDRESS_READ(hw_wdog_presc_t, HW_WDOG_PRESC_ADDR(x)))
01100 #define HW_WDOG_PRESC_WR(x, v)   (ADDRESS_WRITE(hw_wdog_presc_t, HW_WDOG_PRESC_ADDR(x), v))
01101 #define HW_WDOG_PRESC_SET(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) |  (v)))
01102 #define HW_WDOG_PRESC_CLR(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) & ~(v)))
01103 #define HW_WDOG_PRESC_TOG(x, v)  (HW_WDOG_PRESC_WR(x, HW_WDOG_PRESC_RD(x) ^  (v)))
01104 /*@}*/
01105 
01106 /*
01107  * Constants & macros for individual WDOG_PRESC bitfields
01108  */
01109 
01110 /*!
01111  * @name Register WDOG_PRESC, field PRESCVAL[10:8] (RW)
01112  *
01113  * 3-bit prescaler for the watchdog clock source. A value of zero indicates no
01114  * division of the input WDOG clock. The watchdog clock is divided by (PRESCVAL +
01115  * 1) to provide the prescaled WDOG_CLK.
01116  */
01117 /*@{*/
01118 #define BP_WDOG_PRESC_PRESCVAL (8U)        /*!< Bit position for WDOG_PRESC_PRESCVAL. */
01119 #define BM_WDOG_PRESC_PRESCVAL (0x0700U)   /*!< Bit mask for WDOG_PRESC_PRESCVAL. */
01120 #define BS_WDOG_PRESC_PRESCVAL (3U)        /*!< Bit field size in bits for WDOG_PRESC_PRESCVAL. */
01121 
01122 /*! @brief Read current value of the WDOG_PRESC_PRESCVAL field. */
01123 #define BR_WDOG_PRESC_PRESCVAL(x) (UNION_READ(hw_wdog_presc_t, HW_WDOG_PRESC_ADDR(x), U, B.PRESCVAL))
01124 
01125 /*! @brief Format value for bitfield WDOG_PRESC_PRESCVAL. */
01126 #define BF_WDOG_PRESC_PRESCVAL(v) ((uint16_t)((uint16_t)(v) << BP_WDOG_PRESC_PRESCVAL) & BM_WDOG_PRESC_PRESCVAL)
01127 
01128 /*! @brief Set the PRESCVAL field to a new value. */
01129 #define BW_WDOG_PRESC_PRESCVAL(x, v) (HW_WDOG_PRESC_WR(x, (HW_WDOG_PRESC_RD(x) & ~BM_WDOG_PRESC_PRESCVAL) | BF_WDOG_PRESC_PRESCVAL(v)))
01130 /*@}*/
01131 
01132 /*******************************************************************************
01133  * hw_wdog_t - module struct
01134  ******************************************************************************/
01135 /*!
01136  * @brief All WDOG module registers.
01137  */
01138 #pragma pack(1)
01139 typedef struct _hw_wdog
01140 {
01141     __IO hw_wdog_stctrlh_t STCTRLH ;        /*!< [0x0] Watchdog Status and Control Register High */
01142     __IO hw_wdog_stctrll_t STCTRLL ;        /*!< [0x2] Watchdog Status and Control Register Low */
01143     __IO hw_wdog_tovalh_t TOVALH ;          /*!< [0x4] Watchdog Time-out Value Register High */
01144     __IO hw_wdog_tovall_t TOVALL ;          /*!< [0x6] Watchdog Time-out Value Register Low */
01145     __IO hw_wdog_winh_t WINH ;              /*!< [0x8] Watchdog Window Register High */
01146     __IO hw_wdog_winl_t WINL ;              /*!< [0xA] Watchdog Window Register Low */
01147     __IO hw_wdog_refresh_t REFRESH ;        /*!< [0xC] Watchdog Refresh register */
01148     __IO hw_wdog_unlock_t UNLOCK ;          /*!< [0xE] Watchdog Unlock register */
01149     __IO hw_wdog_tmrouth_t TMROUTH ;        /*!< [0x10] Watchdog Timer Output Register High */
01150     __IO hw_wdog_tmroutl_t TMROUTL ;        /*!< [0x12] Watchdog Timer Output Register Low */
01151     __IO hw_wdog_rstcnt_t RSTCNT ;          /*!< [0x14] Watchdog Reset Count register */
01152     __IO hw_wdog_presc_t PRESC ;            /*!< [0x16] Watchdog Prescaler register */
01153 } hw_wdog_t;
01154 #pragma pack()
01155 
01156 /*! @brief Macro to access all WDOG registers. */
01157 /*! @param x WDOG module instance base address. */
01158 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01159  *     use the '&' operator, like <code>&HW_WDOG(WDOG_BASE)</code>. */
01160 #define HW_WDOG(x)     (*(hw_wdog_t *)(x))
01161 
01162 #endif /* __HW_WDOG_REGISTERS_H__ */
01163 /* EOF */