MK64F12_vref.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_VREF_REGISTERS_H__
00088 #define __HW_VREF_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 VREF
00095  *
00096  * Voltage Reference
00097  *
00098  * Registers defined in this header file:
00099  * - HW_VREF_TRM - VREF Trim Register
00100  * - HW_VREF_SC - VREF Status and Control Register
00101  *
00102  * - hw_vref_t - Struct containing all module registers.
00103  */
00104 
00105 #define HW_VREF_INSTANCE_COUNT (1U) /*!< Number of instances of the VREF module. */
00106 
00107 /*******************************************************************************
00108  * HW_VREF_TRM - VREF Trim Register
00109  ******************************************************************************/
00110 
00111 /*!
00112  * @brief HW_VREF_TRM - VREF Trim Register (RW)
00113  *
00114  * Reset value: 0x00U
00115  *
00116  * This register contains bits that contain the trim data for the Voltage
00117  * Reference.
00118  */
00119 typedef union _hw_vref_trm
00120 {
00121     uint8_t U;
00122     struct _hw_vref_trm_bitfields
00123     {
00124         uint8_t TRIM : 6;              /*!< [5:0] Trim bits */
00125         uint8_t CHOPEN : 1;            /*!< [6] Chop oscillator enable. When set,
00126                                         * internal chopping operation is enabled and the internal analog offset will be
00127                                         * minimized. */
00128         uint8_t RESERVED0 : 1;         /*!< [7]  */
00129     } B;
00130 } hw_vref_trm_t;
00131 
00132 /*!
00133  * @name Constants and macros for entire VREF_TRM register
00134  */
00135 /*@{*/
00136 #define HW_VREF_TRM_ADDR(x)      ((x) + 0x0U)
00137 
00138 #define HW_VREF_TRM(x)           (*(__IO hw_vref_trm_t *) HW_VREF_TRM_ADDR(x))
00139 #define HW_VREF_TRM_RD(x)        (ADDRESS_READ(hw_vref_trm_t, HW_VREF_TRM_ADDR(x)))
00140 #define HW_VREF_TRM_WR(x, v)     (ADDRESS_WRITE(hw_vref_trm_t, HW_VREF_TRM_ADDR(x), v))
00141 #define HW_VREF_TRM_SET(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) |  (v)))
00142 #define HW_VREF_TRM_CLR(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) & ~(v)))
00143 #define HW_VREF_TRM_TOG(x, v)    (HW_VREF_TRM_WR(x, HW_VREF_TRM_RD(x) ^  (v)))
00144 /*@}*/
00145 
00146 /*
00147  * Constants & macros for individual VREF_TRM bitfields
00148  */
00149 
00150 /*!
00151  * @name Register VREF_TRM, field TRIM[5:0] (RW)
00152  *
00153  * These bits change the resulting VREF by approximately +/- 0.5 mV for each
00154  * step. Min = minimum and max = maximum voltage reference output. For minimum and
00155  * maximum voltage reference output values, refer to the Data Sheet for this chip.
00156  *
00157  * Values:
00158  * - 000000 - Min
00159  * - 111111 - Max
00160  */
00161 /*@{*/
00162 #define BP_VREF_TRM_TRIM     (0U)          /*!< Bit position for VREF_TRM_TRIM. */
00163 #define BM_VREF_TRM_TRIM     (0x3FU)       /*!< Bit mask for VREF_TRM_TRIM. */
00164 #define BS_VREF_TRM_TRIM     (6U)          /*!< Bit field size in bits for VREF_TRM_TRIM. */
00165 
00166 /*! @brief Read current value of the VREF_TRM_TRIM field. */
00167 #define BR_VREF_TRM_TRIM(x)  (UNION_READ(hw_vref_trm_t, HW_VREF_TRM_ADDR(x), U, B.TRIM))
00168 
00169 /*! @brief Format value for bitfield VREF_TRM_TRIM. */
00170 #define BF_VREF_TRM_TRIM(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_TRIM) & BM_VREF_TRM_TRIM)
00171 
00172 /*! @brief Set the TRIM field to a new value. */
00173 #define BW_VREF_TRM_TRIM(x, v) (HW_VREF_TRM_WR(x, (HW_VREF_TRM_RD(x) & ~BM_VREF_TRM_TRIM) | BF_VREF_TRM_TRIM(v)))
00174 /*@}*/
00175 
00176 /*!
00177  * @name Register VREF_TRM, field CHOPEN[6] (RW)
00178  *
00179  * This bit is set during factory trimming of the VREF voltage. This bit should
00180  * be written to 1 to achieve the performance stated in the data sheet.
00181  *
00182  * Values:
00183  * - 0 - Chop oscillator is disabled.
00184  * - 1 - Chop oscillator is enabled.
00185  */
00186 /*@{*/
00187 #define BP_VREF_TRM_CHOPEN   (6U)          /*!< Bit position for VREF_TRM_CHOPEN. */
00188 #define BM_VREF_TRM_CHOPEN   (0x40U)       /*!< Bit mask for VREF_TRM_CHOPEN. */
00189 #define BS_VREF_TRM_CHOPEN   (1U)          /*!< Bit field size in bits for VREF_TRM_CHOPEN. */
00190 
00191 /*! @brief Read current value of the VREF_TRM_CHOPEN field. */
00192 #define BR_VREF_TRM_CHOPEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN)))
00193 
00194 /*! @brief Format value for bitfield VREF_TRM_CHOPEN. */
00195 #define BF_VREF_TRM_CHOPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_TRM_CHOPEN) & BM_VREF_TRM_CHOPEN)
00196 
00197 /*! @brief Set the CHOPEN field to a new value. */
00198 #define BW_VREF_TRM_CHOPEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_VREF_TRM_ADDR(x), BP_VREF_TRM_CHOPEN), v))
00199 /*@}*/
00200 
00201 /*******************************************************************************
00202  * HW_VREF_SC - VREF Status and Control Register
00203  ******************************************************************************/
00204 
00205 /*!
00206  * @brief HW_VREF_SC - VREF Status and Control Register (RW)
00207  *
00208  * Reset value: 0x00U
00209  *
00210  * This register contains the control bits used to enable the internal voltage
00211  * reference and to select the buffer mode to be used.
00212  */
00213 typedef union _hw_vref_sc
00214 {
00215     uint8_t U;
00216     struct _hw_vref_sc_bitfields
00217     {
00218         uint8_t MODE_LV : 2;           /*!< [1:0] Buffer Mode selection */
00219         uint8_t VREFST : 1;            /*!< [2] Internal Voltage Reference stable */
00220         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
00221         uint8_t ICOMPEN : 1;           /*!< [5] Second order curvature compensation
00222                                         * enable */
00223         uint8_t REGEN : 1;             /*!< [6] Regulator enable */
00224         uint8_t VREFEN : 1;            /*!< [7] Internal Voltage Reference enable */
00225     } B;
00226 } hw_vref_sc_t;
00227 
00228 /*!
00229  * @name Constants and macros for entire VREF_SC register
00230  */
00231 /*@{*/
00232 #define HW_VREF_SC_ADDR(x)       ((x) + 0x1U)
00233 
00234 #define HW_VREF_SC(x)            (*(__IO hw_vref_sc_t *) HW_VREF_SC_ADDR(x))
00235 #define HW_VREF_SC_RD(x)         (ADDRESS_READ(hw_vref_sc_t, HW_VREF_SC_ADDR(x)))
00236 #define HW_VREF_SC_WR(x, v)      (ADDRESS_WRITE(hw_vref_sc_t, HW_VREF_SC_ADDR(x), v))
00237 #define HW_VREF_SC_SET(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) |  (v)))
00238 #define HW_VREF_SC_CLR(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) & ~(v)))
00239 #define HW_VREF_SC_TOG(x, v)     (HW_VREF_SC_WR(x, HW_VREF_SC_RD(x) ^  (v)))
00240 /*@}*/
00241 
00242 /*
00243  * Constants & macros for individual VREF_SC bitfields
00244  */
00245 
00246 /*!
00247  * @name Register VREF_SC, field MODE_LV[1:0] (RW)
00248  *
00249  * These bits select the buffer modes for the Voltage Reference module.
00250  *
00251  * Values:
00252  * - 00 - Bandgap on only, for stabilization and startup
00253  * - 01 - High power buffer mode enabled
00254  * - 10 - Low-power buffer mode enabled
00255  * - 11 - Reserved
00256  */
00257 /*@{*/
00258 #define BP_VREF_SC_MODE_LV   (0U)          /*!< Bit position for VREF_SC_MODE_LV. */
00259 #define BM_VREF_SC_MODE_LV   (0x03U)       /*!< Bit mask for VREF_SC_MODE_LV. */
00260 #define BS_VREF_SC_MODE_LV   (2U)          /*!< Bit field size in bits for VREF_SC_MODE_LV. */
00261 
00262 /*! @brief Read current value of the VREF_SC_MODE_LV field. */
00263 #define BR_VREF_SC_MODE_LV(x) (UNION_READ(hw_vref_sc_t, HW_VREF_SC_ADDR(x), U, B.MODE_LV))
00264 
00265 /*! @brief Format value for bitfield VREF_SC_MODE_LV. */
00266 #define BF_VREF_SC_MODE_LV(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_MODE_LV) & BM_VREF_SC_MODE_LV)
00267 
00268 /*! @brief Set the MODE_LV field to a new value. */
00269 #define BW_VREF_SC_MODE_LV(x, v) (HW_VREF_SC_WR(x, (HW_VREF_SC_RD(x) & ~BM_VREF_SC_MODE_LV) | BF_VREF_SC_MODE_LV(v)))
00270 /*@}*/
00271 
00272 /*!
00273  * @name Register VREF_SC, field VREFST[2] (RO)
00274  *
00275  * This bit indicates that the bandgap reference within the Voltage Reference
00276  * module has completed its startup and stabilization.
00277  *
00278  * Values:
00279  * - 0 - The module is disabled or not stable.
00280  * - 1 - The module is stable.
00281  */
00282 /*@{*/
00283 #define BP_VREF_SC_VREFST    (2U)          /*!< Bit position for VREF_SC_VREFST. */
00284 #define BM_VREF_SC_VREFST    (0x04U)       /*!< Bit mask for VREF_SC_VREFST. */
00285 #define BS_VREF_SC_VREFST    (1U)          /*!< Bit field size in bits for VREF_SC_VREFST. */
00286 
00287 /*! @brief Read current value of the VREF_SC_VREFST field. */
00288 #define BR_VREF_SC_VREFST(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFST)))
00289 /*@}*/
00290 
00291 /*!
00292  * @name Register VREF_SC, field ICOMPEN[5] (RW)
00293  *
00294  * This bit is set during factory trimming of the VREF voltage. This bit should
00295  * be written to 1 to achieve the performance stated in the data sheet.
00296  *
00297  * Values:
00298  * - 0 - Disabled
00299  * - 1 - Enabled
00300  */
00301 /*@{*/
00302 #define BP_VREF_SC_ICOMPEN   (5U)          /*!< Bit position for VREF_SC_ICOMPEN. */
00303 #define BM_VREF_SC_ICOMPEN   (0x20U)       /*!< Bit mask for VREF_SC_ICOMPEN. */
00304 #define BS_VREF_SC_ICOMPEN   (1U)          /*!< Bit field size in bits for VREF_SC_ICOMPEN. */
00305 
00306 /*! @brief Read current value of the VREF_SC_ICOMPEN field. */
00307 #define BR_VREF_SC_ICOMPEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN)))
00308 
00309 /*! @brief Format value for bitfield VREF_SC_ICOMPEN. */
00310 #define BF_VREF_SC_ICOMPEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_ICOMPEN) & BM_VREF_SC_ICOMPEN)
00311 
00312 /*! @brief Set the ICOMPEN field to a new value. */
00313 #define BW_VREF_SC_ICOMPEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_ICOMPEN), v))
00314 /*@}*/
00315 
00316 /*!
00317  * @name Register VREF_SC, field REGEN[6] (RW)
00318  *
00319  * This bit is used to enable the internal 1.75 V regulator to produce a
00320  * constant internal voltage supply in order to reduce the sensitivity to external
00321  * supply noise and variation. If it is desired to keep the regulator enabled in very
00322  * low power modes, refer to the Chip Configuration details for a description on
00323  * how this can be achieved. This bit is set during factory trimming of the VREF
00324  * voltage. This bit should be written to 1 to achieve the performance stated in
00325  * the data sheet.
00326  *
00327  * Values:
00328  * - 0 - Internal 1.75 V regulator is disabled.
00329  * - 1 - Internal 1.75 V regulator is enabled.
00330  */
00331 /*@{*/
00332 #define BP_VREF_SC_REGEN     (6U)          /*!< Bit position for VREF_SC_REGEN. */
00333 #define BM_VREF_SC_REGEN     (0x40U)       /*!< Bit mask for VREF_SC_REGEN. */
00334 #define BS_VREF_SC_REGEN     (1U)          /*!< Bit field size in bits for VREF_SC_REGEN. */
00335 
00336 /*! @brief Read current value of the VREF_SC_REGEN field. */
00337 #define BR_VREF_SC_REGEN(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN)))
00338 
00339 /*! @brief Format value for bitfield VREF_SC_REGEN. */
00340 #define BF_VREF_SC_REGEN(v)  ((uint8_t)((uint8_t)(v) << BP_VREF_SC_REGEN) & BM_VREF_SC_REGEN)
00341 
00342 /*! @brief Set the REGEN field to a new value. */
00343 #define BW_VREF_SC_REGEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_REGEN), v))
00344 /*@}*/
00345 
00346 /*!
00347  * @name Register VREF_SC, field VREFEN[7] (RW)
00348  *
00349  * This bit is used to enable the bandgap reference within the Voltage Reference
00350  * module. After the VREF is enabled, turning off the clock to the VREF module
00351  * via the corresponding clock gate register will not disable the VREF. VREF must
00352  * be disabled via this VREFEN bit.
00353  *
00354  * Values:
00355  * - 0 - The module is disabled.
00356  * - 1 - The module is enabled.
00357  */
00358 /*@{*/
00359 #define BP_VREF_SC_VREFEN    (7U)          /*!< Bit position for VREF_SC_VREFEN. */
00360 #define BM_VREF_SC_VREFEN    (0x80U)       /*!< Bit mask for VREF_SC_VREFEN. */
00361 #define BS_VREF_SC_VREFEN    (1U)          /*!< Bit field size in bits for VREF_SC_VREFEN. */
00362 
00363 /*! @brief Read current value of the VREF_SC_VREFEN field. */
00364 #define BR_VREF_SC_VREFEN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN)))
00365 
00366 /*! @brief Format value for bitfield VREF_SC_VREFEN. */
00367 #define BF_VREF_SC_VREFEN(v) ((uint8_t)((uint8_t)(v) << BP_VREF_SC_VREFEN) & BM_VREF_SC_VREFEN)
00368 
00369 /*! @brief Set the VREFEN field to a new value. */
00370 #define BW_VREF_SC_VREFEN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_VREF_SC_ADDR(x), BP_VREF_SC_VREFEN), v))
00371 /*@}*/
00372 
00373 /*******************************************************************************
00374  * hw_vref_t - module struct
00375  ******************************************************************************/
00376 /*!
00377  * @brief All VREF module registers.
00378  */
00379 #pragma pack(1)
00380 typedef struct _hw_vref
00381 {
00382     __IO hw_vref_trm_t TRM ;                /*!< [0x0] VREF Trim Register */
00383     __IO hw_vref_sc_t SC ;                  /*!< [0x1] VREF Status and Control Register */
00384 } hw_vref_t;
00385 #pragma pack()
00386 
00387 /*! @brief Macro to access all VREF registers. */
00388 /*! @param x VREF module instance base address. */
00389 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00390  *     use the '&' operator, like <code>&HW_VREF(VREF_BASE)</code>. */
00391 #define HW_VREF(x)     (*(hw_vref_t *)(x))
00392 
00393 #endif /* __HW_VREF_REGISTERS_H__ */
00394 /* EOF */