MK64F12_usbdcd.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_USBDCD_REGISTERS_H__
00088 #define __HW_USBDCD_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 USBDCD
00095  *
00096  * USB Device Charger Detection module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_USBDCD_CONTROL - Control register
00100  * - HW_USBDCD_CLOCK - Clock register
00101  * - HW_USBDCD_STATUS - Status register
00102  * - HW_USBDCD_TIMER0 - TIMER0 register
00103  * - HW_USBDCD_TIMER1 - TIMER1 register
00104  * - HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
00105  * - HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
00106  *
00107  * - hw_usbdcd_t - Struct containing all module registers.
00108  */
00109 
00110 #define HW_USBDCD_INSTANCE_COUNT (1U) /*!< Number of instances of the USBDCD module. */
00111 
00112 /*******************************************************************************
00113  * HW_USBDCD_CONTROL - Control register
00114  ******************************************************************************/
00115 
00116 /*!
00117  * @brief HW_USBDCD_CONTROL - Control register (RW)
00118  *
00119  * Reset value: 0x00010000U
00120  *
00121  * Contains the control and interrupt bit fields.
00122  */
00123 typedef union _hw_usbdcd_control
00124 {
00125     uint32_t U;
00126     struct _hw_usbdcd_control_bitfields
00127     {
00128         uint32_t IACK : 1;             /*!< [0] Interrupt Acknowledge */
00129         uint32_t RESERVED0 : 7;        /*!< [7:1]  */
00130         uint32_t IF : 1;               /*!< [8] Interrupt Flag */
00131         uint32_t RESERVED1 : 7;        /*!< [15:9]  */
00132         uint32_t IE : 1;               /*!< [16] Interrupt Enable */
00133         uint32_t BC12 : 1;             /*!< [17]  */
00134         uint32_t RESERVED2 : 6;        /*!< [23:18]  */
00135         uint32_t START : 1;            /*!< [24] Start Change Detection Sequence */
00136         uint32_t SR : 1;               /*!< [25] Software Reset */
00137         uint32_t RESERVED3 : 6;        /*!< [31:26]  */
00138     } B;
00139 } hw_usbdcd_control_t;
00140 
00141 /*!
00142  * @name Constants and macros for entire USBDCD_CONTROL register
00143  */
00144 /*@{*/
00145 #define HW_USBDCD_CONTROL_ADDR(x) ((x) + 0x0U)
00146 
00147 #define HW_USBDCD_CONTROL(x)     (*(__IO hw_usbdcd_control_t *) HW_USBDCD_CONTROL_ADDR(x))
00148 #define HW_USBDCD_CONTROL_RD(x)  (ADDRESS_READ(hw_usbdcd_control_t, HW_USBDCD_CONTROL_ADDR(x)))
00149 #define HW_USBDCD_CONTROL_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_control_t, HW_USBDCD_CONTROL_ADDR(x), v))
00150 #define HW_USBDCD_CONTROL_SET(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) |  (v)))
00151 #define HW_USBDCD_CONTROL_CLR(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) & ~(v)))
00152 #define HW_USBDCD_CONTROL_TOG(x, v) (HW_USBDCD_CONTROL_WR(x, HW_USBDCD_CONTROL_RD(x) ^  (v)))
00153 /*@}*/
00154 
00155 /*
00156  * Constants & macros for individual USBDCD_CONTROL bitfields
00157  */
00158 
00159 /*!
00160  * @name Register USBDCD_CONTROL, field IACK[0] (WORZ)
00161  *
00162  * Determines whether the interrupt is cleared.
00163  *
00164  * Values:
00165  * - 0 - Do not clear the interrupt.
00166  * - 1 - Clear the IF bit (interrupt flag).
00167  */
00168 /*@{*/
00169 #define BP_USBDCD_CONTROL_IACK (0U)        /*!< Bit position for USBDCD_CONTROL_IACK. */
00170 #define BM_USBDCD_CONTROL_IACK (0x00000001U) /*!< Bit mask for USBDCD_CONTROL_IACK. */
00171 #define BS_USBDCD_CONTROL_IACK (1U)        /*!< Bit field size in bits for USBDCD_CONTROL_IACK. */
00172 
00173 /*! @brief Format value for bitfield USBDCD_CONTROL_IACK. */
00174 #define BF_USBDCD_CONTROL_IACK(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IACK) & BM_USBDCD_CONTROL_IACK)
00175 
00176 /*! @brief Set the IACK field to a new value. */
00177 #define BW_USBDCD_CONTROL_IACK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IACK), v))
00178 /*@}*/
00179 
00180 /*!
00181  * @name Register USBDCD_CONTROL, field IF[8] (RO)
00182  *
00183  * Determines whether an interrupt is pending.
00184  *
00185  * Values:
00186  * - 0 - No interrupt is pending.
00187  * - 1 - An interrupt is pending.
00188  */
00189 /*@{*/
00190 #define BP_USBDCD_CONTROL_IF (8U)          /*!< Bit position for USBDCD_CONTROL_IF. */
00191 #define BM_USBDCD_CONTROL_IF (0x00000100U) /*!< Bit mask for USBDCD_CONTROL_IF. */
00192 #define BS_USBDCD_CONTROL_IF (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_IF. */
00193 
00194 /*! @brief Read current value of the USBDCD_CONTROL_IF field. */
00195 #define BR_USBDCD_CONTROL_IF(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IF)))
00196 /*@}*/
00197 
00198 /*!
00199  * @name Register USBDCD_CONTROL, field IE[16] (RW)
00200  *
00201  * Enables/disables interrupts to the system.
00202  *
00203  * Values:
00204  * - 0 - Disable interrupts to the system.
00205  * - 1 - Enable interrupts to the system.
00206  */
00207 /*@{*/
00208 #define BP_USBDCD_CONTROL_IE (16U)         /*!< Bit position for USBDCD_CONTROL_IE. */
00209 #define BM_USBDCD_CONTROL_IE (0x00010000U) /*!< Bit mask for USBDCD_CONTROL_IE. */
00210 #define BS_USBDCD_CONTROL_IE (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_IE. */
00211 
00212 /*! @brief Read current value of the USBDCD_CONTROL_IE field. */
00213 #define BR_USBDCD_CONTROL_IE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE)))
00214 
00215 /*! @brief Format value for bitfield USBDCD_CONTROL_IE. */
00216 #define BF_USBDCD_CONTROL_IE(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_IE) & BM_USBDCD_CONTROL_IE)
00217 
00218 /*! @brief Set the IE field to a new value. */
00219 #define BW_USBDCD_CONTROL_IE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_IE), v))
00220 /*@}*/
00221 
00222 /*!
00223  * @name Register USBDCD_CONTROL, field BC12[17] (RW)
00224  *
00225  * BC1.2 compatibility. This bit cannot be changed after start detection.
00226  *
00227  * Values:
00228  * - 0 - Compatible with BC1.1 (default)
00229  * - 1 - Compatible with BC1.2
00230  */
00231 /*@{*/
00232 #define BP_USBDCD_CONTROL_BC12 (17U)       /*!< Bit position for USBDCD_CONTROL_BC12. */
00233 #define BM_USBDCD_CONTROL_BC12 (0x00020000U) /*!< Bit mask for USBDCD_CONTROL_BC12. */
00234 #define BS_USBDCD_CONTROL_BC12 (1U)        /*!< Bit field size in bits for USBDCD_CONTROL_BC12. */
00235 
00236 /*! @brief Read current value of the USBDCD_CONTROL_BC12 field. */
00237 #define BR_USBDCD_CONTROL_BC12(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12)))
00238 
00239 /*! @brief Format value for bitfield USBDCD_CONTROL_BC12. */
00240 #define BF_USBDCD_CONTROL_BC12(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_BC12) & BM_USBDCD_CONTROL_BC12)
00241 
00242 /*! @brief Set the BC12 field to a new value. */
00243 #define BW_USBDCD_CONTROL_BC12(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_BC12), v))
00244 /*@}*/
00245 
00246 /*!
00247  * @name Register USBDCD_CONTROL, field START[24] (WORZ)
00248  *
00249  * Determines whether the charger detection sequence is initiated.
00250  *
00251  * Values:
00252  * - 0 - Do not start the sequence. Writes of this value have no effect.
00253  * - 1 - Initiate the charger detection sequence. If the sequence is already
00254  *     running, writes of this value have no effect.
00255  */
00256 /*@{*/
00257 #define BP_USBDCD_CONTROL_START (24U)      /*!< Bit position for USBDCD_CONTROL_START. */
00258 #define BM_USBDCD_CONTROL_START (0x01000000U) /*!< Bit mask for USBDCD_CONTROL_START. */
00259 #define BS_USBDCD_CONTROL_START (1U)       /*!< Bit field size in bits for USBDCD_CONTROL_START. */
00260 
00261 /*! @brief Format value for bitfield USBDCD_CONTROL_START. */
00262 #define BF_USBDCD_CONTROL_START(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_START) & BM_USBDCD_CONTROL_START)
00263 
00264 /*! @brief Set the START field to a new value. */
00265 #define BW_USBDCD_CONTROL_START(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_START), v))
00266 /*@}*/
00267 
00268 /*!
00269  * @name Register USBDCD_CONTROL, field SR[25] (WORZ)
00270  *
00271  * Determines whether a software reset is performed.
00272  *
00273  * Values:
00274  * - 0 - Do not perform a software reset.
00275  * - 1 - Perform a software reset.
00276  */
00277 /*@{*/
00278 #define BP_USBDCD_CONTROL_SR (25U)         /*!< Bit position for USBDCD_CONTROL_SR. */
00279 #define BM_USBDCD_CONTROL_SR (0x02000000U) /*!< Bit mask for USBDCD_CONTROL_SR. */
00280 #define BS_USBDCD_CONTROL_SR (1U)          /*!< Bit field size in bits for USBDCD_CONTROL_SR. */
00281 
00282 /*! @brief Format value for bitfield USBDCD_CONTROL_SR. */
00283 #define BF_USBDCD_CONTROL_SR(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CONTROL_SR) & BM_USBDCD_CONTROL_SR)
00284 
00285 /*! @brief Set the SR field to a new value. */
00286 #define BW_USBDCD_CONTROL_SR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CONTROL_ADDR(x), BP_USBDCD_CONTROL_SR), v))
00287 /*@}*/
00288 
00289 /*******************************************************************************
00290  * HW_USBDCD_CLOCK - Clock register
00291  ******************************************************************************/
00292 
00293 /*!
00294  * @brief HW_USBDCD_CLOCK - Clock register (RW)
00295  *
00296  * Reset value: 0x000000C1U
00297  */
00298 typedef union _hw_usbdcd_clock
00299 {
00300     uint32_t U;
00301     struct _hw_usbdcd_clock_bitfields
00302     {
00303         uint32_t CLOCK_UNIT : 1;       /*!< [0] Unit of Measurement Encoding for
00304                                         * Clock Speed */
00305         uint32_t RESERVED0 : 1;        /*!< [1]  */
00306         uint32_t CLOCK_SPEED : 10;     /*!< [11:2] Numerical Value of Clock Speed
00307                                         * in Binary */
00308         uint32_t RESERVED1 : 20;       /*!< [31:12]  */
00309     } B;
00310 } hw_usbdcd_clock_t;
00311 
00312 /*!
00313  * @name Constants and macros for entire USBDCD_CLOCK register
00314  */
00315 /*@{*/
00316 #define HW_USBDCD_CLOCK_ADDR(x)  ((x) + 0x4U)
00317 
00318 #define HW_USBDCD_CLOCK(x)       (*(__IO hw_usbdcd_clock_t *) HW_USBDCD_CLOCK_ADDR(x))
00319 #define HW_USBDCD_CLOCK_RD(x)    (ADDRESS_READ(hw_usbdcd_clock_t, HW_USBDCD_CLOCK_ADDR(x)))
00320 #define HW_USBDCD_CLOCK_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_clock_t, HW_USBDCD_CLOCK_ADDR(x), v))
00321 #define HW_USBDCD_CLOCK_SET(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) |  (v)))
00322 #define HW_USBDCD_CLOCK_CLR(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) & ~(v)))
00323 #define HW_USBDCD_CLOCK_TOG(x, v) (HW_USBDCD_CLOCK_WR(x, HW_USBDCD_CLOCK_RD(x) ^  (v)))
00324 /*@}*/
00325 
00326 /*
00327  * Constants & macros for individual USBDCD_CLOCK bitfields
00328  */
00329 
00330 /*!
00331  * @name Register USBDCD_CLOCK, field CLOCK_UNIT[0] (RW)
00332  *
00333  * Specifies the unit of measure for the clock speed.
00334  *
00335  * Values:
00336  * - 0 - kHz Speed (between 1 kHz and 1023 kHz)
00337  * - 1 - MHz Speed (between 1 MHz and 1023 MHz)
00338  */
00339 /*@{*/
00340 #define BP_USBDCD_CLOCK_CLOCK_UNIT (0U)    /*!< Bit position for USBDCD_CLOCK_CLOCK_UNIT. */
00341 #define BM_USBDCD_CLOCK_CLOCK_UNIT (0x00000001U) /*!< Bit mask for USBDCD_CLOCK_CLOCK_UNIT. */
00342 #define BS_USBDCD_CLOCK_CLOCK_UNIT (1U)    /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_UNIT. */
00343 
00344 /*! @brief Read current value of the USBDCD_CLOCK_CLOCK_UNIT field. */
00345 #define BR_USBDCD_CLOCK_CLOCK_UNIT(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT)))
00346 
00347 /*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_UNIT. */
00348 #define BF_USBDCD_CLOCK_CLOCK_UNIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_UNIT) & BM_USBDCD_CLOCK_CLOCK_UNIT)
00349 
00350 /*! @brief Set the CLOCK_UNIT field to a new value. */
00351 #define BW_USBDCD_CLOCK_CLOCK_UNIT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_CLOCK_ADDR(x), BP_USBDCD_CLOCK_CLOCK_UNIT), v))
00352 /*@}*/
00353 
00354 /*!
00355  * @name Register USBDCD_CLOCK, field CLOCK_SPEED[11:2] (RW)
00356  *
00357  * The unit of measure is programmed in CLOCK_UNIT. The valid range is from 1 to
00358  * 1023 when clock unit is MHz and 4 to 1023 when clock unit is kHz. Examples
00359  * with CLOCK_UNIT = 1: For 48 MHz: 0b00_0011_0000 (48) (Default) For 24 MHz:
00360  * 0b00_0001_1000 (24) Examples with CLOCK_UNIT = 0: For 100 kHz: 0b00_0110_0100 (100)
00361  * For 500 kHz: 0b01_1111_0100 (500)
00362  */
00363 /*@{*/
00364 #define BP_USBDCD_CLOCK_CLOCK_SPEED (2U)   /*!< Bit position for USBDCD_CLOCK_CLOCK_SPEED. */
00365 #define BM_USBDCD_CLOCK_CLOCK_SPEED (0x00000FFCU) /*!< Bit mask for USBDCD_CLOCK_CLOCK_SPEED. */
00366 #define BS_USBDCD_CLOCK_CLOCK_SPEED (10U)  /*!< Bit field size in bits for USBDCD_CLOCK_CLOCK_SPEED. */
00367 
00368 /*! @brief Read current value of the USBDCD_CLOCK_CLOCK_SPEED field. */
00369 #define BR_USBDCD_CLOCK_CLOCK_SPEED(x) (UNION_READ(hw_usbdcd_clock_t, HW_USBDCD_CLOCK_ADDR(x), U, B.CLOCK_SPEED))
00370 
00371 /*! @brief Format value for bitfield USBDCD_CLOCK_CLOCK_SPEED. */
00372 #define BF_USBDCD_CLOCK_CLOCK_SPEED(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_CLOCK_CLOCK_SPEED) & BM_USBDCD_CLOCK_CLOCK_SPEED)
00373 
00374 /*! @brief Set the CLOCK_SPEED field to a new value. */
00375 #define BW_USBDCD_CLOCK_CLOCK_SPEED(x, v) (HW_USBDCD_CLOCK_WR(x, (HW_USBDCD_CLOCK_RD(x) & ~BM_USBDCD_CLOCK_CLOCK_SPEED) | BF_USBDCD_CLOCK_CLOCK_SPEED(v)))
00376 /*@}*/
00377 
00378 /*******************************************************************************
00379  * HW_USBDCD_STATUS - Status register
00380  ******************************************************************************/
00381 
00382 /*!
00383  * @brief HW_USBDCD_STATUS - Status register (RO)
00384  *
00385  * Reset value: 0x00000000U
00386  *
00387  * Provides the current state of the module for system software monitoring.
00388  */
00389 typedef union _hw_usbdcd_status
00390 {
00391     uint32_t U;
00392     struct _hw_usbdcd_status_bitfields
00393     {
00394         uint32_t RESERVED0 : 16;       /*!< [15:0]  */
00395         uint32_t SEQ_RES : 2;          /*!< [17:16] Charger Detection Sequence Results
00396                                         * */
00397         uint32_t SEQ_STAT : 2;         /*!< [19:18] Charger Detection Sequence Status
00398                                         * */
00399         uint32_t ERR : 1;              /*!< [20] Error Flag */
00400         uint32_t TO : 1;               /*!< [21] Timeout Flag */
00401         uint32_t ACTIVE : 1;           /*!< [22] Active Status Indicator */
00402         uint32_t RESERVED1 : 9;        /*!< [31:23]  */
00403     } B;
00404 } hw_usbdcd_status_t;
00405 
00406 /*!
00407  * @name Constants and macros for entire USBDCD_STATUS register
00408  */
00409 /*@{*/
00410 #define HW_USBDCD_STATUS_ADDR(x) ((x) + 0x8U)
00411 
00412 #define HW_USBDCD_STATUS(x)      (*(__I hw_usbdcd_status_t *) HW_USBDCD_STATUS_ADDR(x))
00413 #define HW_USBDCD_STATUS_RD(x)   (ADDRESS_READ(hw_usbdcd_status_t, HW_USBDCD_STATUS_ADDR(x)))
00414 /*@}*/
00415 
00416 /*
00417  * Constants & macros for individual USBDCD_STATUS bitfields
00418  */
00419 
00420 /*!
00421  * @name Register USBDCD_STATUS, field SEQ_RES[17:16] (RO)
00422  *
00423  * Reports how the charger detection is attached.
00424  *
00425  * Values:
00426  * - 00 - No results to report.
00427  * - 01 - Attached to a standard host. Must comply with USB 2.0 by drawing only
00428  *     2.5 mA (max) until connected.
00429  * - 10 - Attached to a charging port. The exact meaning depends on bit 18: 0:
00430  *     Attached to either a charging host or a dedicated charger. The charger type
00431  *     detection has not completed. 1: Attached to a charging host. The charger
00432  *     type detection has completed.
00433  * - 11 - Attached to a dedicated charger.
00434  */
00435 /*@{*/
00436 #define BP_USBDCD_STATUS_SEQ_RES (16U)     /*!< Bit position for USBDCD_STATUS_SEQ_RES. */
00437 #define BM_USBDCD_STATUS_SEQ_RES (0x00030000U) /*!< Bit mask for USBDCD_STATUS_SEQ_RES. */
00438 #define BS_USBDCD_STATUS_SEQ_RES (2U)      /*!< Bit field size in bits for USBDCD_STATUS_SEQ_RES. */
00439 
00440 /*! @brief Read current value of the USBDCD_STATUS_SEQ_RES field. */
00441 #define BR_USBDCD_STATUS_SEQ_RES(x) (UNION_READ(hw_usbdcd_status_t, HW_USBDCD_STATUS_ADDR(x), U, B.SEQ_RES))
00442 /*@}*/
00443 
00444 /*!
00445  * @name Register USBDCD_STATUS, field SEQ_STAT[19:18] (RO)
00446  *
00447  * Indicates the status of the charger detection sequence.
00448  *
00449  * Values:
00450  * - 00 - The module is either not enabled, or the module is enabled but the
00451  *     data pins have not yet been detected.
00452  * - 01 - Data pin contact detection is complete.
00453  * - 10 - Charging port detection is complete.
00454  * - 11 - Charger type detection is complete.
00455  */
00456 /*@{*/
00457 #define BP_USBDCD_STATUS_SEQ_STAT (18U)    /*!< Bit position for USBDCD_STATUS_SEQ_STAT. */
00458 #define BM_USBDCD_STATUS_SEQ_STAT (0x000C0000U) /*!< Bit mask for USBDCD_STATUS_SEQ_STAT. */
00459 #define BS_USBDCD_STATUS_SEQ_STAT (2U)     /*!< Bit field size in bits for USBDCD_STATUS_SEQ_STAT. */
00460 
00461 /*! @brief Read current value of the USBDCD_STATUS_SEQ_STAT field. */
00462 #define BR_USBDCD_STATUS_SEQ_STAT(x) (UNION_READ(hw_usbdcd_status_t, HW_USBDCD_STATUS_ADDR(x), U, B.SEQ_STAT))
00463 /*@}*/
00464 
00465 /*!
00466  * @name Register USBDCD_STATUS, field ERR[20] (RO)
00467  *
00468  * Indicates whether there is an error in the detection sequence.
00469  *
00470  * Values:
00471  * - 0 - No sequence errors.
00472  * - 1 - Error in the detection sequence. See the SEQ_STAT field to determine
00473  *     the phase in which the error occurred.
00474  */
00475 /*@{*/
00476 #define BP_USBDCD_STATUS_ERR (20U)         /*!< Bit position for USBDCD_STATUS_ERR. */
00477 #define BM_USBDCD_STATUS_ERR (0x00100000U) /*!< Bit mask for USBDCD_STATUS_ERR. */
00478 #define BS_USBDCD_STATUS_ERR (1U)          /*!< Bit field size in bits for USBDCD_STATUS_ERR. */
00479 
00480 /*! @brief Read current value of the USBDCD_STATUS_ERR field. */
00481 #define BR_USBDCD_STATUS_ERR(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ERR)))
00482 /*@}*/
00483 
00484 /*!
00485  * @name Register USBDCD_STATUS, field TO[21] (RO)
00486  *
00487  * Indicates whether the detection sequence has passed the timeout threshhold.
00488  *
00489  * Values:
00490  * - 0 - The detection sequence has not been running for over 1 s.
00491  * - 1 - It has been over 1 s since the data pin contact was detected and
00492  *     debounced.
00493  */
00494 /*@{*/
00495 #define BP_USBDCD_STATUS_TO  (21U)         /*!< Bit position for USBDCD_STATUS_TO. */
00496 #define BM_USBDCD_STATUS_TO  (0x00200000U) /*!< Bit mask for USBDCD_STATUS_TO. */
00497 #define BS_USBDCD_STATUS_TO  (1U)          /*!< Bit field size in bits for USBDCD_STATUS_TO. */
00498 
00499 /*! @brief Read current value of the USBDCD_STATUS_TO field. */
00500 #define BR_USBDCD_STATUS_TO(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_TO)))
00501 /*@}*/
00502 
00503 /*!
00504  * @name Register USBDCD_STATUS, field ACTIVE[22] (RO)
00505  *
00506  * Indicates whether the sequence is running.
00507  *
00508  * Values:
00509  * - 0 - The sequence is not running.
00510  * - 1 - The sequence is running.
00511  */
00512 /*@{*/
00513 #define BP_USBDCD_STATUS_ACTIVE (22U)      /*!< Bit position for USBDCD_STATUS_ACTIVE. */
00514 #define BM_USBDCD_STATUS_ACTIVE (0x00400000U) /*!< Bit mask for USBDCD_STATUS_ACTIVE. */
00515 #define BS_USBDCD_STATUS_ACTIVE (1U)       /*!< Bit field size in bits for USBDCD_STATUS_ACTIVE. */
00516 
00517 /*! @brief Read current value of the USBDCD_STATUS_ACTIVE field. */
00518 #define BR_USBDCD_STATUS_ACTIVE(x) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_USBDCD_STATUS_ADDR(x), BP_USBDCD_STATUS_ACTIVE)))
00519 /*@}*/
00520 
00521 /*******************************************************************************
00522  * HW_USBDCD_TIMER0 - TIMER0 register
00523  ******************************************************************************/
00524 
00525 /*!
00526  * @brief HW_USBDCD_TIMER0 - TIMER0 register (RW)
00527  *
00528  * Reset value: 0x00100000U
00529  *
00530  * TIMER0 has an TSEQ_INIT field that represents the system latency in ms.
00531  * Latency is measured from the time when VBUS goes active until the time system
00532  * software initiates charger detection sequence in USBDCD module. When software sets
00533  * the CONTROL[START] bit, the Unit Connection Timer (TUNITCON) is initialized
00534  * with the value of TSEQ_INIT. Valid values are 0-1023, however the USB Battery
00535  * Charging Specification requires the entire sequence, including TSEQ_INIT, to be
00536  * completed in 1s or less.
00537  */
00538 typedef union _hw_usbdcd_timer0
00539 {
00540     uint32_t U;
00541     struct _hw_usbdcd_timer0_bitfields
00542     {
00543         uint32_t TUNITCON : 12;        /*!< [11:0] Unit Connection Timer Elapse (in
00544                                         * ms) */
00545         uint32_t RESERVED0 : 4;        /*!< [15:12]  */
00546         uint32_t TSEQ_INIT : 10;       /*!< [25:16] Sequence Initiation Time */
00547         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
00548     } B;
00549 } hw_usbdcd_timer0_t;
00550 
00551 /*!
00552  * @name Constants and macros for entire USBDCD_TIMER0 register
00553  */
00554 /*@{*/
00555 #define HW_USBDCD_TIMER0_ADDR(x) ((x) + 0x10U)
00556 
00557 #define HW_USBDCD_TIMER0(x)      (*(__IO hw_usbdcd_timer0_t *) HW_USBDCD_TIMER0_ADDR(x))
00558 #define HW_USBDCD_TIMER0_RD(x)   (ADDRESS_READ(hw_usbdcd_timer0_t, HW_USBDCD_TIMER0_ADDR(x)))
00559 #define HW_USBDCD_TIMER0_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_timer0_t, HW_USBDCD_TIMER0_ADDR(x), v))
00560 #define HW_USBDCD_TIMER0_SET(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) |  (v)))
00561 #define HW_USBDCD_TIMER0_CLR(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) & ~(v)))
00562 #define HW_USBDCD_TIMER0_TOG(x, v) (HW_USBDCD_TIMER0_WR(x, HW_USBDCD_TIMER0_RD(x) ^  (v)))
00563 /*@}*/
00564 
00565 /*
00566  * Constants & macros for individual USBDCD_TIMER0 bitfields
00567  */
00568 
00569 /*!
00570  * @name Register USBDCD_TIMER0, field TUNITCON[11:0] (RO)
00571  *
00572  * Displays the amount of elapsed time since the event of setting the START bit
00573  * plus the value of TSEQ_INIT. The timer is automatically initialized with the
00574  * value of TSEQ_INIT before starting to count. This timer enables compliance with
00575  * the maximum time allowed to connect T UNIT_CON under the USB Battery Charging
00576  * Specification. If the timer reaches the one second limit, the module triggers
00577  * an interrupt and sets the error flag STATUS[ERR]. The timer continues
00578  * counting throughout the charger detection sequence, even when control has been passed
00579  * to software. As long as the module is active, the timer continues to count
00580  * until it reaches the maximum value of 0xFFF (4095 ms). The timer does not
00581  * rollover to zero. A software reset clears the timer.
00582  */
00583 /*@{*/
00584 #define BP_USBDCD_TIMER0_TUNITCON (0U)     /*!< Bit position for USBDCD_TIMER0_TUNITCON. */
00585 #define BM_USBDCD_TIMER0_TUNITCON (0x00000FFFU) /*!< Bit mask for USBDCD_TIMER0_TUNITCON. */
00586 #define BS_USBDCD_TIMER0_TUNITCON (12U)    /*!< Bit field size in bits for USBDCD_TIMER0_TUNITCON. */
00587 
00588 /*! @brief Read current value of the USBDCD_TIMER0_TUNITCON field. */
00589 #define BR_USBDCD_TIMER0_TUNITCON(x) (UNION_READ(hw_usbdcd_timer0_t, HW_USBDCD_TIMER0_ADDR(x), U, B.TUNITCON))
00590 /*@}*/
00591 
00592 /*!
00593  * @name Register USBDCD_TIMER0, field TSEQ_INIT[25:16] (RW)
00594  *
00595  * TSEQ_INIT represents the system latency (in ms) measured from the time VBUS
00596  * goes active to the time system software initiates the charger detection
00597  * sequence in the USBDCD module. When software sets the CONTROL[START] bit, the Unit
00598  * Connection Timer (TUNITCON) is initialized with the value of TSEQ_INIT. Valid
00599  * values are 0-1023, but the USB Battery Charging Specification requires the
00600  * entire sequence, including TSEQ_INIT, to be completed in 1s or less.
00601  */
00602 /*@{*/
00603 #define BP_USBDCD_TIMER0_TSEQ_INIT (16U)   /*!< Bit position for USBDCD_TIMER0_TSEQ_INIT. */
00604 #define BM_USBDCD_TIMER0_TSEQ_INIT (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER0_TSEQ_INIT. */
00605 #define BS_USBDCD_TIMER0_TSEQ_INIT (10U)   /*!< Bit field size in bits for USBDCD_TIMER0_TSEQ_INIT. */
00606 
00607 /*! @brief Read current value of the USBDCD_TIMER0_TSEQ_INIT field. */
00608 #define BR_USBDCD_TIMER0_TSEQ_INIT(x) (UNION_READ(hw_usbdcd_timer0_t, HW_USBDCD_TIMER0_ADDR(x), U, B.TSEQ_INIT))
00609 
00610 /*! @brief Format value for bitfield USBDCD_TIMER0_TSEQ_INIT. */
00611 #define BF_USBDCD_TIMER0_TSEQ_INIT(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER0_TSEQ_INIT) & BM_USBDCD_TIMER0_TSEQ_INIT)
00612 
00613 /*! @brief Set the TSEQ_INIT field to a new value. */
00614 #define BW_USBDCD_TIMER0_TSEQ_INIT(x, v) (HW_USBDCD_TIMER0_WR(x, (HW_USBDCD_TIMER0_RD(x) & ~BM_USBDCD_TIMER0_TSEQ_INIT) | BF_USBDCD_TIMER0_TSEQ_INIT(v)))
00615 /*@}*/
00616 
00617 /*******************************************************************************
00618  * HW_USBDCD_TIMER1 - TIMER1 register
00619  ******************************************************************************/
00620 
00621 /*!
00622  * @brief HW_USBDCD_TIMER1 - TIMER1 register (RW)
00623  *
00624  * Reset value: 0x000A0028U
00625  *
00626  * TIMER1 contains timing parameters. Note that register values can be written
00627  * that are not compliant with the USB Battery Charging Specification, so care
00628  * should be taken when overwriting the default values.
00629  */
00630 typedef union _hw_usbdcd_timer1
00631 {
00632     uint32_t U;
00633     struct _hw_usbdcd_timer1_bitfields
00634     {
00635         uint32_t TVDPSRC_ON : 10;      /*!< [9:0] Time Period Comparator Enabled */
00636         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
00637         uint32_t TDCD_DBNC : 10;       /*!< [25:16] Time Period to Debounce D+
00638                                         * Signal */
00639         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
00640     } B;
00641 } hw_usbdcd_timer1_t;
00642 
00643 /*!
00644  * @name Constants and macros for entire USBDCD_TIMER1 register
00645  */
00646 /*@{*/
00647 #define HW_USBDCD_TIMER1_ADDR(x) ((x) + 0x14U)
00648 
00649 #define HW_USBDCD_TIMER1(x)      (*(__IO hw_usbdcd_timer1_t *) HW_USBDCD_TIMER1_ADDR(x))
00650 #define HW_USBDCD_TIMER1_RD(x)   (ADDRESS_READ(hw_usbdcd_timer1_t, HW_USBDCD_TIMER1_ADDR(x)))
00651 #define HW_USBDCD_TIMER1_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_timer1_t, HW_USBDCD_TIMER1_ADDR(x), v))
00652 #define HW_USBDCD_TIMER1_SET(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) |  (v)))
00653 #define HW_USBDCD_TIMER1_CLR(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) & ~(v)))
00654 #define HW_USBDCD_TIMER1_TOG(x, v) (HW_USBDCD_TIMER1_WR(x, HW_USBDCD_TIMER1_RD(x) ^  (v)))
00655 /*@}*/
00656 
00657 /*
00658  * Constants & macros for individual USBDCD_TIMER1 bitfields
00659  */
00660 
00661 /*!
00662  * @name Register USBDCD_TIMER1, field TVDPSRC_ON[9:0] (RW)
00663  *
00664  * This timing parameter is used after detection of the data pin. See "Charging
00665  * Port Detection". Valid values are 1-1023, but the USB Battery Charging
00666  * Specification requires a minimum value of 40 ms.
00667  */
00668 /*@{*/
00669 #define BP_USBDCD_TIMER1_TVDPSRC_ON (0U)   /*!< Bit position for USBDCD_TIMER1_TVDPSRC_ON. */
00670 #define BM_USBDCD_TIMER1_TVDPSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER1_TVDPSRC_ON. */
00671 #define BS_USBDCD_TIMER1_TVDPSRC_ON (10U)  /*!< Bit field size in bits for USBDCD_TIMER1_TVDPSRC_ON. */
00672 
00673 /*! @brief Read current value of the USBDCD_TIMER1_TVDPSRC_ON field. */
00674 #define BR_USBDCD_TIMER1_TVDPSRC_ON(x) (UNION_READ(hw_usbdcd_timer1_t, HW_USBDCD_TIMER1_ADDR(x), U, B.TVDPSRC_ON))
00675 
00676 /*! @brief Format value for bitfield USBDCD_TIMER1_TVDPSRC_ON. */
00677 #define BF_USBDCD_TIMER1_TVDPSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TVDPSRC_ON) & BM_USBDCD_TIMER1_TVDPSRC_ON)
00678 
00679 /*! @brief Set the TVDPSRC_ON field to a new value. */
00680 #define BW_USBDCD_TIMER1_TVDPSRC_ON(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TVDPSRC_ON) | BF_USBDCD_TIMER1_TVDPSRC_ON(v)))
00681 /*@}*/
00682 
00683 /*!
00684  * @name Register USBDCD_TIMER1, field TDCD_DBNC[25:16] (RW)
00685  *
00686  * Sets the time period (ms) to debounce the D+ signal during the data pin
00687  * contact detection phase. See "Debouncing the data pin contact" Valid values are
00688  * 1-1023, but the USB Battery Charging Specification requires a minimum value of 10
00689  * ms.
00690  */
00691 /*@{*/
00692 #define BP_USBDCD_TIMER1_TDCD_DBNC (16U)   /*!< Bit position for USBDCD_TIMER1_TDCD_DBNC. */
00693 #define BM_USBDCD_TIMER1_TDCD_DBNC (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER1_TDCD_DBNC. */
00694 #define BS_USBDCD_TIMER1_TDCD_DBNC (10U)   /*!< Bit field size in bits for USBDCD_TIMER1_TDCD_DBNC. */
00695 
00696 /*! @brief Read current value of the USBDCD_TIMER1_TDCD_DBNC field. */
00697 #define BR_USBDCD_TIMER1_TDCD_DBNC(x) (UNION_READ(hw_usbdcd_timer1_t, HW_USBDCD_TIMER1_ADDR(x), U, B.TDCD_DBNC))
00698 
00699 /*! @brief Format value for bitfield USBDCD_TIMER1_TDCD_DBNC. */
00700 #define BF_USBDCD_TIMER1_TDCD_DBNC(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER1_TDCD_DBNC) & BM_USBDCD_TIMER1_TDCD_DBNC)
00701 
00702 /*! @brief Set the TDCD_DBNC field to a new value. */
00703 #define BW_USBDCD_TIMER1_TDCD_DBNC(x, v) (HW_USBDCD_TIMER1_WR(x, (HW_USBDCD_TIMER1_RD(x) & ~BM_USBDCD_TIMER1_TDCD_DBNC) | BF_USBDCD_TIMER1_TDCD_DBNC(v)))
00704 /*@}*/
00705 
00706 /*******************************************************************************
00707  * HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register
00708  ******************************************************************************/
00709 
00710 /*!
00711  * @brief HW_USBDCD_TIMER2_BC11 - TIMER2_BC11 register (RW)
00712  *
00713  * Reset value: 0x00280001U
00714  *
00715  * TIMER2_BC11 contains timing parameters for USB Battery Charging
00716  * Specification, v1.1. Register values can be written that are not compliant with the USB
00717  * Battery Charging Specification, so care should be taken when overwriting the
00718  * default values.
00719  */
00720 typedef union _hw_usbdcd_timer2_bc11
00721 {
00722     uint32_t U;
00723     struct _hw_usbdcd_timer2_bc11_bitfields
00724     {
00725         uint32_t CHECK_DM : 4;         /*!< [3:0] Time Before Check of D- Line */
00726         uint32_t RESERVED0 : 12;       /*!< [15:4]  */
00727         uint32_t TVDPSRC_CON : 10;     /*!< [25:16] Time Period Before Enabling
00728                                         * D+ Pullup */
00729         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
00730     } B;
00731 } hw_usbdcd_timer2_bc11_t;
00732 
00733 /*!
00734  * @name Constants and macros for entire USBDCD_TIMER2_BC11 register
00735  */
00736 /*@{*/
00737 #define HW_USBDCD_TIMER2_BC11_ADDR(x) ((x) + 0x18U)
00738 
00739 #define HW_USBDCD_TIMER2_BC11(x) (*(__IO hw_usbdcd_timer2_bc11_t *) HW_USBDCD_TIMER2_BC11_ADDR(x))
00740 #define HW_USBDCD_TIMER2_BC11_RD(x) (ADDRESS_READ(hw_usbdcd_timer2_bc11_t, HW_USBDCD_TIMER2_BC11_ADDR(x)))
00741 #define HW_USBDCD_TIMER2_BC11_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_timer2_bc11_t, HW_USBDCD_TIMER2_BC11_ADDR(x), v))
00742 #define HW_USBDCD_TIMER2_BC11_SET(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) |  (v)))
00743 #define HW_USBDCD_TIMER2_BC11_CLR(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) & ~(v)))
00744 #define HW_USBDCD_TIMER2_BC11_TOG(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, HW_USBDCD_TIMER2_BC11_RD(x) ^  (v)))
00745 /*@}*/
00746 
00747 /*
00748  * Constants & macros for individual USBDCD_TIMER2_BC11 bitfields
00749  */
00750 
00751 /*!
00752  * @name Register USBDCD_TIMER2_BC11, field CHECK_DM[3:0] (RW)
00753  *
00754  * Sets the amount of time (in ms) that the module waits after the device
00755  * connects to the USB bus until checking the state of the D- line to determine the
00756  * type of charging port. See "Charger Type Detection." Valid values are 1-15ms.
00757  */
00758 /*@{*/
00759 #define BP_USBDCD_TIMER2_BC11_CHECK_DM (0U) /*!< Bit position for USBDCD_TIMER2_BC11_CHECK_DM. */
00760 #define BM_USBDCD_TIMER2_BC11_CHECK_DM (0x0000000FU) /*!< Bit mask for USBDCD_TIMER2_BC11_CHECK_DM. */
00761 #define BS_USBDCD_TIMER2_BC11_CHECK_DM (4U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_CHECK_DM. */
00762 
00763 /*! @brief Read current value of the USBDCD_TIMER2_BC11_CHECK_DM field. */
00764 #define BR_USBDCD_TIMER2_BC11_CHECK_DM(x) (UNION_READ(hw_usbdcd_timer2_bc11_t, HW_USBDCD_TIMER2_BC11_ADDR(x), U, B.CHECK_DM))
00765 
00766 /*! @brief Format value for bitfield USBDCD_TIMER2_BC11_CHECK_DM. */
00767 #define BF_USBDCD_TIMER2_BC11_CHECK_DM(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_CHECK_DM) & BM_USBDCD_TIMER2_BC11_CHECK_DM)
00768 
00769 /*! @brief Set the CHECK_DM field to a new value. */
00770 #define BW_USBDCD_TIMER2_BC11_CHECK_DM(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_CHECK_DM) | BF_USBDCD_TIMER2_BC11_CHECK_DM(v)))
00771 /*@}*/
00772 
00773 /*!
00774  * @name Register USBDCD_TIMER2_BC11, field TVDPSRC_CON[25:16] (RW)
00775  *
00776  * Sets the time period (ms) that the module waits after charging port detection
00777  * before system software must enable the D+ pullup to connect to the USB host.
00778  * Valid values are 1-1023, but the USB Battery Charging Specification requires a
00779  * minimum value of 40 ms.
00780  */
00781 /*@{*/
00782 #define BP_USBDCD_TIMER2_BC11_TVDPSRC_CON (16U) /*!< Bit position for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
00783 #define BM_USBDCD_TIMER2_BC11_TVDPSRC_CON (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
00784 #define BS_USBDCD_TIMER2_BC11_TVDPSRC_CON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC11_TVDPSRC_CON. */
00785 
00786 /*! @brief Read current value of the USBDCD_TIMER2_BC11_TVDPSRC_CON field. */
00787 #define BR_USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (UNION_READ(hw_usbdcd_timer2_bc11_t, HW_USBDCD_TIMER2_BC11_ADDR(x), U, B.TVDPSRC_CON))
00788 
00789 /*! @brief Format value for bitfield USBDCD_TIMER2_BC11_TVDPSRC_CON. */
00790 #define BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC11_TVDPSRC_CON) & BM_USBDCD_TIMER2_BC11_TVDPSRC_CON)
00791 
00792 /*! @brief Set the TVDPSRC_CON field to a new value. */
00793 #define BW_USBDCD_TIMER2_BC11_TVDPSRC_CON(x, v) (HW_USBDCD_TIMER2_BC11_WR(x, (HW_USBDCD_TIMER2_BC11_RD(x) & ~BM_USBDCD_TIMER2_BC11_TVDPSRC_CON) | BF_USBDCD_TIMER2_BC11_TVDPSRC_CON(v)))
00794 /*@}*/
00795 /*******************************************************************************
00796  * HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register
00797  ******************************************************************************/
00798 
00799 /*!
00800  * @brief HW_USBDCD_TIMER2_BC12 - TIMER2_BC12 register (RW)
00801  *
00802  * Reset value: 0x00010028U
00803  *
00804  * TIMER2_BC12 contains timing parameters for USB Battery Charging
00805  * Specification, v1.2. Register values can be written that are not compliant with the USB
00806  * Battery Charging Specification, so care should be taken when overwriting the
00807  * default values.
00808  */
00809 typedef union _hw_usbdcd_timer2_bc12
00810 {
00811     uint32_t U;
00812     struct _hw_usbdcd_timer2_bc12_bitfields
00813     {
00814         uint32_t TVDMSRC_ON : 10;      /*!< [9:0]  */
00815         uint32_t RESERVED0 : 6;        /*!< [15:10]  */
00816         uint32_t TWAIT_AFTER_PRD : 10; /*!< [25:16]  */
00817         uint32_t RESERVED1 : 6;        /*!< [31:26]  */
00818     } B;
00819 } hw_usbdcd_timer2_bc12_t;
00820 
00821 /*!
00822  * @name Constants and macros for entire USBDCD_TIMER2_BC12 register
00823  */
00824 /*@{*/
00825 #define HW_USBDCD_TIMER2_BC12_ADDR(x) ((x) + 0x18U)
00826 
00827 #define HW_USBDCD_TIMER2_BC12(x) (*(__IO hw_usbdcd_timer2_bc12_t *) HW_USBDCD_TIMER2_BC12_ADDR(x))
00828 #define HW_USBDCD_TIMER2_BC12_RD(x) (ADDRESS_READ(hw_usbdcd_timer2_bc12_t, HW_USBDCD_TIMER2_BC12_ADDR(x)))
00829 #define HW_USBDCD_TIMER2_BC12_WR(x, v) (ADDRESS_WRITE(hw_usbdcd_timer2_bc12_t, HW_USBDCD_TIMER2_BC12_ADDR(x), v))
00830 #define HW_USBDCD_TIMER2_BC12_SET(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) |  (v)))
00831 #define HW_USBDCD_TIMER2_BC12_CLR(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) & ~(v)))
00832 #define HW_USBDCD_TIMER2_BC12_TOG(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, HW_USBDCD_TIMER2_BC12_RD(x) ^  (v)))
00833 /*@}*/
00834 
00835 /*
00836  * Constants & macros for individual USBDCD_TIMER2_BC12 bitfields
00837  */
00838 
00839 /*!
00840  * @name Register USBDCD_TIMER2_BC12, field TVDMSRC_ON[9:0] (RW)
00841  *
00842  * Sets the amount of time (in ms) that the module enables the VDM_SRC. Valid
00843  * values are 0-40ms.
00844  */
00845 /*@{*/
00846 #define BP_USBDCD_TIMER2_BC12_TVDMSRC_ON (0U) /*!< Bit position for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
00847 #define BM_USBDCD_TIMER2_BC12_TVDMSRC_ON (0x000003FFU) /*!< Bit mask for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
00848 #define BS_USBDCD_TIMER2_BC12_TVDMSRC_ON (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TVDMSRC_ON. */
00849 
00850 /*! @brief Read current value of the USBDCD_TIMER2_BC12_TVDMSRC_ON field. */
00851 #define BR_USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (UNION_READ(hw_usbdcd_timer2_bc12_t, HW_USBDCD_TIMER2_BC12_ADDR(x), U, B.TVDMSRC_ON))
00852 
00853 /*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TVDMSRC_ON. */
00854 #define BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TVDMSRC_ON) & BM_USBDCD_TIMER2_BC12_TVDMSRC_ON)
00855 
00856 /*! @brief Set the TVDMSRC_ON field to a new value. */
00857 #define BW_USBDCD_TIMER2_BC12_TVDMSRC_ON(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TVDMSRC_ON) | BF_USBDCD_TIMER2_BC12_TVDMSRC_ON(v)))
00858 /*@}*/
00859 
00860 /*!
00861  * @name Register USBDCD_TIMER2_BC12, field TWAIT_AFTER_PRD[25:16] (RW)
00862  *
00863  * Sets the amount of time (in ms) that the module waits after primary detection
00864  * before start to secondary detection. Valid values are 1-1023ms. Default is
00865  * 1ms.
00866  */
00867 /*@{*/
00868 #define BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (16U) /*!< Bit position for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
00869 #define BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (0x03FF0000U) /*!< Bit mask for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
00870 #define BS_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD (10U) /*!< Bit field size in bits for USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
00871 
00872 /*! @brief Read current value of the USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD field. */
00873 #define BR_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (UNION_READ(hw_usbdcd_timer2_bc12_t, HW_USBDCD_TIMER2_BC12_ADDR(x), U, B.TWAIT_AFTER_PRD))
00874 
00875 /*! @brief Format value for bitfield USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD. */
00876 #define BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v) ((uint32_t)((uint32_t)(v) << BP_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) & BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD)
00877 
00878 /*! @brief Set the TWAIT_AFTER_PRD field to a new value. */
00879 #define BW_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x, v) (HW_USBDCD_TIMER2_BC12_WR(x, (HW_USBDCD_TIMER2_BC12_RD(x) & ~BM_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD) | BF_USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(v)))
00880 /*@}*/
00881 
00882 /*
00883 ** Start of section using anonymous unions
00884 */
00885 
00886 #if defined(__ARMCC_VERSION)
00887   #pragma push
00888   #pragma anon_unions
00889 #elif defined(__CWCC__)
00890   #pragma push
00891   #pragma cpp_extensions on
00892 #elif defined(__GNUC__)
00893   /* anonymous unions are enabled by default */
00894 #elif defined(__IAR_SYSTEMS_ICC__)
00895   #pragma language=extended
00896 #else
00897   #error Not supported compiler type
00898 #endif
00899 
00900 /*******************************************************************************
00901  * hw_usbdcd_t - module struct
00902  ******************************************************************************/
00903 /*!
00904  * @brief All USBDCD module registers.
00905  */
00906 #pragma pack(1)
00907 typedef struct _hw_usbdcd
00908 {
00909     __IO hw_usbdcd_control_t CONTROL ;      /*!< [0x0] Control register */
00910     __IO hw_usbdcd_clock_t CLOCK ;          /*!< [0x4] Clock register */
00911     __I hw_usbdcd_status_t STATUS ;         /*!< [0x8] Status register */
00912     uint8_t _reserved0[4];
00913     __IO hw_usbdcd_timer0_t TIMER0 ;        /*!< [0x10] TIMER0 register */
00914     __IO hw_usbdcd_timer1_t TIMER1 ;        /*!< [0x14] TIMER1 register */
00915     union {
00916         __IO hw_usbdcd_timer2_bc11_t TIMER2_BC11 ; /*!< [0x18] TIMER2_BC11 register */
00917         __IO hw_usbdcd_timer2_bc12_t TIMER2_BC12 ; /*!< [0x18] TIMER2_BC12 register */
00918     };
00919 } hw_usbdcd_t;
00920 #pragma pack()
00921 
00922 /*! @brief Macro to access all USBDCD registers. */
00923 /*! @param x USBDCD module instance base address. */
00924 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00925  *     use the '&' operator, like <code>&HW_USBDCD(USBDCD_BASE)</code>. */
00926 #define HW_USBDCD(x)   (*(hw_usbdcd_t *)(x))
00927 
00928 /*
00929 ** End of section using anonymous unions
00930 */
00931 
00932 #if defined(__ARMCC_VERSION)
00933   #pragma pop
00934 #elif defined(__CWCC__)
00935   #pragma pop
00936 #elif defined(__GNUC__)
00937   /* leave anonymous unions enabled */
00938 #elif defined(__IAR_SYSTEMS_ICC__)
00939   #pragma language=default
00940 #else
00941   #error Not supported compiler type
00942 #endif
00943 
00944 #endif /* __HW_USBDCD_REGISTERS_H__ */
00945 /* EOF */