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target-mcu-k64f
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MK64F12_uart.h
00001 /* 00002 ** ################################################################### 00003 ** Compilers: Keil ARM C/C++ Compiler 00004 ** Freescale C/C++ for Embedded ARM 00005 ** GNU C Compiler 00006 ** IAR ANSI C/C++ Compiler for ARM 00007 ** 00008 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 00009 ** Version: rev. 2.5, 2014-02-10 00010 ** Build: b140604 00011 ** 00012 ** Abstract: 00013 ** Extension to the CMSIS register access layer header. 00014 ** 00015 ** Copyright (c) 2014 Freescale Semiconductor, Inc. 00016 ** All rights reserved. 00017 ** 00018 ** (C) COPYRIGHT 2015-2015 ARM Limited 00019 ** ALL RIGHTS RESERVED 00020 ** 00021 ** Redistribution and use in source and binary forms, with or without modification, 00022 ** are permitted provided that the following conditions are met: 00023 ** 00024 ** o Redistributions of source code must retain the above copyright notice, this list 00025 ** of conditions and the following disclaimer. 00026 ** 00027 ** o Redistributions in binary form must reproduce the above copyright notice, this 00028 ** list of conditions and the following disclaimer in the documentation and/or 00029 ** other materials provided with the distribution. 00030 ** 00031 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 00032 ** contributors may be used to endorse or promote products derived from this 00033 ** software without specific prior written permission. 00034 ** 00035 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00036 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00037 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00038 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00039 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00040 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00041 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00042 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00043 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00044 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00045 ** 00046 ** http: www.freescale.com 00047 ** mail: support@freescale.com 00048 ** 00049 ** Revisions: 00050 ** - rev. 1.0 (2013-08-12) 00051 ** Initial version. 00052 ** - rev. 2.0 (2013-10-29) 00053 ** Register accessor macros added to the memory map. 00054 ** Symbols for Processor Expert memory map compatibility added to the memory map. 00055 ** Startup file for gcc has been updated according to CMSIS 3.2. 00056 ** System initialization updated. 00057 ** MCG - registers updated. 00058 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 00059 ** - rev. 2.1 (2013-10-30) 00060 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 00061 ** - rev. 2.2 (2013-12-09) 00062 ** DMA - EARS register removed. 00063 ** AIPS0, AIPS1 - MPRA register updated. 00064 ** - rev. 2.3 (2014-01-24) 00065 ** Update according to reference manual rev. 2 00066 ** ENET, MCG, MCM, SIM, USB - registers updated 00067 ** - rev. 2.4 (2014-02-10) 00068 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00069 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00070 ** - rev. 2.5 (2014-02-10) 00071 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 00072 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 00073 ** Module access macro module_BASES replaced by module_BASE_PTRS. 00074 ** - rev. 2.6 (2015-08-03) (ARM) 00075 ** All accesses to memory are replaced by equivalent macros; this allows 00076 ** memory read/write operations to be re-defined if needed (for example, 00077 ** to implement new security features 00078 ** 00079 ** ################################################################### 00080 */ 00081 00082 /* 00083 * WARNING! DO NOT EDIT THIS FILE DIRECTLY! 00084 * 00085 * This file was generated automatically and any changes may be lost. 00086 */ 00087 #ifndef __HW_UART_REGISTERS_H__ 00088 #define __HW_UART_REGISTERS_H__ 00089 00090 #include "MK64F12.h" 00091 #include "fsl_bitaccess.h" 00092 00093 /* 00094 * MK64F12 UART 00095 * 00096 * Serial Communication Interface 00097 * 00098 * Registers defined in this header file: 00099 * - HW_UART_BDH - UART Baud Rate Registers: High 00100 * - HW_UART_BDL - UART Baud Rate Registers: Low 00101 * - HW_UART_C1 - UART Control Register 1 00102 * - HW_UART_C2 - UART Control Register 2 00103 * - HW_UART_S1 - UART Status Register 1 00104 * - HW_UART_S2 - UART Status Register 2 00105 * - HW_UART_C3 - UART Control Register 3 00106 * - HW_UART_D - UART Data Register 00107 * - HW_UART_MA1 - UART Match Address Registers 1 00108 * - HW_UART_MA2 - UART Match Address Registers 2 00109 * - HW_UART_C4 - UART Control Register 4 00110 * - HW_UART_C5 - UART Control Register 5 00111 * - HW_UART_ED - UART Extended Data Register 00112 * - HW_UART_MODEM - UART Modem Register 00113 * - HW_UART_IR - UART Infrared Register 00114 * - HW_UART_PFIFO - UART FIFO Parameters 00115 * - HW_UART_CFIFO - UART FIFO Control Register 00116 * - HW_UART_SFIFO - UART FIFO Status Register 00117 * - HW_UART_TWFIFO - UART FIFO Transmit Watermark 00118 * - HW_UART_TCFIFO - UART FIFO Transmit Count 00119 * - HW_UART_RWFIFO - UART FIFO Receive Watermark 00120 * - HW_UART_RCFIFO - UART FIFO Receive Count 00121 * - HW_UART_C7816 - UART 7816 Control Register 00122 * - HW_UART_IE7816 - UART 7816 Interrupt Enable Register 00123 * - HW_UART_IS7816 - UART 7816 Interrupt Status Register 00124 * - HW_UART_WP7816T0 - UART 7816 Wait Parameter Register 00125 * - HW_UART_WP7816T1 - UART 7816 Wait Parameter Register 00126 * - HW_UART_WN7816 - UART 7816 Wait N Register 00127 * - HW_UART_WF7816 - UART 7816 Wait FD Register 00128 * - HW_UART_ET7816 - UART 7816 Error Threshold Register 00129 * - HW_UART_TL7816 - UART 7816 Transmit Length Register 00130 * 00131 * - hw_uart_t - Struct containing all module registers. 00132 */ 00133 00134 #define HW_UART_INSTANCE_COUNT (6U) /*!< Number of instances of the UART module. */ 00135 #define HW_UART0 (0U) /*!< Instance number for UART0. */ 00136 #define HW_UART1 (1U) /*!< Instance number for UART1. */ 00137 #define HW_UART2 (2U) /*!< Instance number for UART2. */ 00138 #define HW_UART3 (3U) /*!< Instance number for UART3. */ 00139 #define HW_UART4 (4U) /*!< Instance number for UART4. */ 00140 #define HW_UART5 (5U) /*!< Instance number for UART5. */ 00141 00142 /******************************************************************************* 00143 * HW_UART_BDH - UART Baud Rate Registers: High 00144 ******************************************************************************/ 00145 00146 /*! 00147 * @brief HW_UART_BDH - UART Baud Rate Registers: High (RW) 00148 * 00149 * Reset value: 0x00U 00150 * 00151 * This register, along with the BDL register, controls the prescale divisor for 00152 * UART baud rate generation. To update the 13-bit baud rate setting 00153 * (SBR[12:0]), first write to BDH to buffer the high half of the new value and then write 00154 * to BDL. The working value in BDH does not change until BDL is written. BDL is 00155 * reset to a nonzero value, but after reset, the baud rate generator remains 00156 * disabled until the first time the receiver or transmitter is enabled, that is, 00157 * when C2[RE] or C2[TE] is set. 00158 */ 00159 typedef union _hw_uart_bdh 00160 { 00161 uint8_t U; 00162 struct _hw_uart_bdh_bitfields 00163 { 00164 uint8_t SBR : 5; /*!< [4:0] UART Baud Rate Bits */ 00165 uint8_t SBNS : 1; /*!< [5] Stop Bit Number Select */ 00166 uint8_t RXEDGIE : 1; /*!< [6] RxD Input Active Edge Interrupt Enable 00167 * */ 00168 uint8_t LBKDIE : 1; /*!< [7] LIN Break Detect Interrupt or DMA 00169 * Request Enable */ 00170 } B; 00171 } hw_uart_bdh_t; 00172 00173 /*! 00174 * @name Constants and macros for entire UART_BDH register 00175 */ 00176 /*@{*/ 00177 #define HW_UART_BDH_ADDR(x) ((x) + 0x0U) 00178 00179 #define HW_UART_BDH(x) (*(__IO hw_uart_bdh_t *) HW_UART_BDH_ADDR(x)) 00180 #define HW_UART_BDH_RD(x) (ADDRESS_READ(hw_uart_bdh_t, HW_UART_BDH_ADDR(x))) 00181 #define HW_UART_BDH_WR(x, v) (ADDRESS_WRITE(hw_uart_bdh_t, HW_UART_BDH_ADDR(x), v)) 00182 #define HW_UART_BDH_SET(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) | (v))) 00183 #define HW_UART_BDH_CLR(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) & ~(v))) 00184 #define HW_UART_BDH_TOG(x, v) (HW_UART_BDH_WR(x, HW_UART_BDH_RD(x) ^ (v))) 00185 /*@}*/ 00186 00187 /* 00188 * Constants & macros for individual UART_BDH bitfields 00189 */ 00190 00191 /*! 00192 * @name Register UART_BDH, field SBR[4:0] (RW) 00193 * 00194 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate 00195 * generation for details. The baud rate generator is disabled until C2[TE] or 00196 * C2[RE] is set for the first time after reset.The baud rate generator is disabled 00197 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because 00198 * writing to BDH puts the data in a temporary location until BDL is written. 00199 */ 00200 /*@{*/ 00201 #define BP_UART_BDH_SBR (0U) /*!< Bit position for UART_BDH_SBR. */ 00202 #define BM_UART_BDH_SBR (0x1FU) /*!< Bit mask for UART_BDH_SBR. */ 00203 #define BS_UART_BDH_SBR (5U) /*!< Bit field size in bits for UART_BDH_SBR. */ 00204 00205 /*! @brief Read current value of the UART_BDH_SBR field. */ 00206 #define BR_UART_BDH_SBR(x) (UNION_READ(hw_uart_bdh_t, HW_UART_BDH_ADDR(x), U, B.SBR)) 00207 00208 /*! @brief Format value for bitfield UART_BDH_SBR. */ 00209 #define BF_UART_BDH_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBR) & BM_UART_BDH_SBR) 00210 00211 /*! @brief Set the SBR field to a new value. */ 00212 #define BW_UART_BDH_SBR(x, v) (HW_UART_BDH_WR(x, (HW_UART_BDH_RD(x) & ~BM_UART_BDH_SBR) | BF_UART_BDH_SBR(v))) 00213 /*@}*/ 00214 00215 /*! 00216 * @name Register UART_BDH, field SBNS[5] (RW) 00217 * 00218 * SBNS selects the number of stop bits present in a data frame. This field 00219 * valid for all 8, 9 and 10 bit data formats available. This field is not valid when 00220 * C7816[ISO7816E] is enabled. 00221 * 00222 * Values: 00223 * - 0 - Data frame consists of a single stop bit. 00224 * - 1 - Data frame consists of two stop bits. 00225 */ 00226 /*@{*/ 00227 #define BP_UART_BDH_SBNS (5U) /*!< Bit position for UART_BDH_SBNS. */ 00228 #define BM_UART_BDH_SBNS (0x20U) /*!< Bit mask for UART_BDH_SBNS. */ 00229 #define BS_UART_BDH_SBNS (1U) /*!< Bit field size in bits for UART_BDH_SBNS. */ 00230 00231 /*! @brief Read current value of the UART_BDH_SBNS field. */ 00232 #define BR_UART_BDH_SBNS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS))) 00233 00234 /*! @brief Format value for bitfield UART_BDH_SBNS. */ 00235 #define BF_UART_BDH_SBNS(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_SBNS) & BM_UART_BDH_SBNS) 00236 00237 /*! @brief Set the SBNS field to a new value. */ 00238 #define BW_UART_BDH_SBNS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_SBNS), v)) 00239 /*@}*/ 00240 00241 /*! 00242 * @name Register UART_BDH, field RXEDGIE[6] (RW) 00243 * 00244 * Enables the receive input active edge, RXEDGIF, to generate interrupt 00245 * requests. 00246 * 00247 * Values: 00248 * - 0 - Hardware interrupts from RXEDGIF disabled using polling. 00249 * - 1 - RXEDGIF interrupt request enabled. 00250 */ 00251 /*@{*/ 00252 #define BP_UART_BDH_RXEDGIE (6U) /*!< Bit position for UART_BDH_RXEDGIE. */ 00253 #define BM_UART_BDH_RXEDGIE (0x40U) /*!< Bit mask for UART_BDH_RXEDGIE. */ 00254 #define BS_UART_BDH_RXEDGIE (1U) /*!< Bit field size in bits for UART_BDH_RXEDGIE. */ 00255 00256 /*! @brief Read current value of the UART_BDH_RXEDGIE field. */ 00257 #define BR_UART_BDH_RXEDGIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE))) 00258 00259 /*! @brief Format value for bitfield UART_BDH_RXEDGIE. */ 00260 #define BF_UART_BDH_RXEDGIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_RXEDGIE) & BM_UART_BDH_RXEDGIE) 00261 00262 /*! @brief Set the RXEDGIE field to a new value. */ 00263 #define BW_UART_BDH_RXEDGIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_RXEDGIE), v)) 00264 /*@}*/ 00265 00266 /*! 00267 * @name Register UART_BDH, field LBKDIE[7] (RW) 00268 * 00269 * Enables the LIN break detect flag, LBKDIF, to generate interrupt requests 00270 * based on the state of LBKDDMAS. or DMA transfer requests, 00271 * 00272 * Values: 00273 * - 0 - LBKDIF interrupt and DMA transfer requests disabled. 00274 * - 1 - LBKDIF interrupt or DMA transfer requests enabled. 00275 */ 00276 /*@{*/ 00277 #define BP_UART_BDH_LBKDIE (7U) /*!< Bit position for UART_BDH_LBKDIE. */ 00278 #define BM_UART_BDH_LBKDIE (0x80U) /*!< Bit mask for UART_BDH_LBKDIE. */ 00279 #define BS_UART_BDH_LBKDIE (1U) /*!< Bit field size in bits for UART_BDH_LBKDIE. */ 00280 00281 /*! @brief Read current value of the UART_BDH_LBKDIE field. */ 00282 #define BR_UART_BDH_LBKDIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE))) 00283 00284 /*! @brief Format value for bitfield UART_BDH_LBKDIE. */ 00285 #define BF_UART_BDH_LBKDIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDH_LBKDIE) & BM_UART_BDH_LBKDIE) 00286 00287 /*! @brief Set the LBKDIE field to a new value. */ 00288 #define BW_UART_BDH_LBKDIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_BDH_ADDR(x), BP_UART_BDH_LBKDIE), v)) 00289 /*@}*/ 00290 00291 /******************************************************************************* 00292 * HW_UART_BDL - UART Baud Rate Registers: Low 00293 ******************************************************************************/ 00294 00295 /*! 00296 * @brief HW_UART_BDL - UART Baud Rate Registers: Low (RW) 00297 * 00298 * Reset value: 0x04U 00299 * 00300 * This register, along with the BDH register, controls the prescale divisor for 00301 * UART baud rate generation. To update the 13-bit baud rate setting, SBR[12:0], 00302 * first write to BDH to buffer the high half of the new value and then write to 00303 * BDL. The working value in BDH does not change until BDL is written. BDL is 00304 * reset to a nonzero value, but after reset, the baud rate generator remains 00305 * disabled until the first time the receiver or transmitter is enabled, that is, when 00306 * C2[RE] or C2[TE] is set. 00307 */ 00308 typedef union _hw_uart_bdl 00309 { 00310 uint8_t U; 00311 struct _hw_uart_bdl_bitfields 00312 { 00313 uint8_t SBR : 8; /*!< [7:0] UART Baud Rate Bits */ 00314 } B; 00315 } hw_uart_bdl_t; 00316 00317 /*! 00318 * @name Constants and macros for entire UART_BDL register 00319 */ 00320 /*@{*/ 00321 #define HW_UART_BDL_ADDR(x) ((x) + 0x1U) 00322 00323 #define HW_UART_BDL(x) (*(__IO hw_uart_bdl_t *) HW_UART_BDL_ADDR(x)) 00324 #define HW_UART_BDL_RD(x) (ADDRESS_READ(hw_uart_bdl_t, HW_UART_BDL_ADDR(x))) 00325 #define HW_UART_BDL_WR(x, v) (ADDRESS_WRITE(hw_uart_bdl_t, HW_UART_BDL_ADDR(x), v)) 00326 #define HW_UART_BDL_SET(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) | (v))) 00327 #define HW_UART_BDL_CLR(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) & ~(v))) 00328 #define HW_UART_BDL_TOG(x, v) (HW_UART_BDL_WR(x, HW_UART_BDL_RD(x) ^ (v))) 00329 /*@}*/ 00330 00331 /* 00332 * Constants & macros for individual UART_BDL bitfields 00333 */ 00334 00335 /*! 00336 * @name Register UART_BDL, field SBR[7:0] (RW) 00337 * 00338 * The baud rate for the UART is determined by the 13 SBR fields. See Baud rate 00339 * generation for details. The baud rate generator is disabled until C2[TE] or 00340 * C2[RE] is set for the first time after reset.The baud rate generator is disabled 00341 * when SBR = 0. Writing to BDH has no effect without writing to BDL, because 00342 * writing to BDH puts the data in a temporary location until BDL is written. When 00343 * the 1/32 narrow pulse width is selected for infrared (IrDA), the baud rate 00344 * fields must be even, the least significant bit is 0. See MODEM register for more 00345 * details. 00346 */ 00347 /*@{*/ 00348 #define BP_UART_BDL_SBR (0U) /*!< Bit position for UART_BDL_SBR. */ 00349 #define BM_UART_BDL_SBR (0xFFU) /*!< Bit mask for UART_BDL_SBR. */ 00350 #define BS_UART_BDL_SBR (8U) /*!< Bit field size in bits for UART_BDL_SBR. */ 00351 00352 /*! @brief Read current value of the UART_BDL_SBR field. */ 00353 #define BR_UART_BDL_SBR(x) (HW_UART_BDL(x).U) 00354 00355 /*! @brief Format value for bitfield UART_BDL_SBR. */ 00356 #define BF_UART_BDL_SBR(v) ((uint8_t)((uint8_t)(v) << BP_UART_BDL_SBR) & BM_UART_BDL_SBR) 00357 00358 /*! @brief Set the SBR field to a new value. */ 00359 #define BW_UART_BDL_SBR(x, v) (HW_UART_BDL_WR(x, v)) 00360 /*@}*/ 00361 00362 /******************************************************************************* 00363 * HW_UART_C1 - UART Control Register 1 00364 ******************************************************************************/ 00365 00366 /*! 00367 * @brief HW_UART_C1 - UART Control Register 1 (RW) 00368 * 00369 * Reset value: 0x00U 00370 * 00371 * This read/write register controls various optional features of the UART 00372 * system. 00373 */ 00374 typedef union _hw_uart_c1 00375 { 00376 uint8_t U; 00377 struct _hw_uart_c1_bitfields 00378 { 00379 uint8_t PT : 1; /*!< [0] Parity Type */ 00380 uint8_t PE : 1; /*!< [1] Parity Enable */ 00381 uint8_t ILT : 1; /*!< [2] Idle Line Type Select */ 00382 uint8_t WAKE : 1; /*!< [3] Receiver Wakeup Method Select */ 00383 uint8_t M : 1; /*!< [4] 9-bit or 8-bit Mode Select */ 00384 uint8_t RSRC : 1; /*!< [5] Receiver Source Select */ 00385 uint8_t UARTSWAI : 1; /*!< [6] UART Stops in Wait Mode */ 00386 uint8_t LOOPS : 1; /*!< [7] Loop Mode Select */ 00387 } B; 00388 } hw_uart_c1_t; 00389 00390 /*! 00391 * @name Constants and macros for entire UART_C1 register 00392 */ 00393 /*@{*/ 00394 #define HW_UART_C1_ADDR(x) ((x) + 0x2U) 00395 00396 #define HW_UART_C1(x) (*(__IO hw_uart_c1_t *) HW_UART_C1_ADDR(x)) 00397 #define HW_UART_C1_RD(x) (ADDRESS_READ(hw_uart_c1_t, HW_UART_C1_ADDR(x))) 00398 #define HW_UART_C1_WR(x, v) (ADDRESS_WRITE(hw_uart_c1_t, HW_UART_C1_ADDR(x), v)) 00399 #define HW_UART_C1_SET(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) | (v))) 00400 #define HW_UART_C1_CLR(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) & ~(v))) 00401 #define HW_UART_C1_TOG(x, v) (HW_UART_C1_WR(x, HW_UART_C1_RD(x) ^ (v))) 00402 /*@}*/ 00403 00404 /* 00405 * Constants & macros for individual UART_C1 bitfields 00406 */ 00407 00408 /*! 00409 * @name Register UART_C1, field PT[0] (RW) 00410 * 00411 * Determines whether the UART generates and checks for even parity or odd 00412 * parity. With even parity, an even number of 1s clears the parity bit and an odd 00413 * number of 1s sets the parity bit. With odd parity, an odd number of 1s clears the 00414 * parity bit and an even number of 1s sets the parity bit. This field must be 00415 * cleared when C7816[ISO_7816E] is set/enabled. 00416 * 00417 * Values: 00418 * - 0 - Even parity. 00419 * - 1 - Odd parity. 00420 */ 00421 /*@{*/ 00422 #define BP_UART_C1_PT (0U) /*!< Bit position for UART_C1_PT. */ 00423 #define BM_UART_C1_PT (0x01U) /*!< Bit mask for UART_C1_PT. */ 00424 #define BS_UART_C1_PT (1U) /*!< Bit field size in bits for UART_C1_PT. */ 00425 00426 /*! @brief Read current value of the UART_C1_PT field. */ 00427 #define BR_UART_C1_PT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT))) 00428 00429 /*! @brief Format value for bitfield UART_C1_PT. */ 00430 #define BF_UART_C1_PT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PT) & BM_UART_C1_PT) 00431 00432 /*! @brief Set the PT field to a new value. */ 00433 #define BW_UART_C1_PT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PT), v)) 00434 /*@}*/ 00435 00436 /*! 00437 * @name Register UART_C1, field PE[1] (RW) 00438 * 00439 * Enables the parity function. When parity is enabled, parity function inserts 00440 * a parity bit in the bit position immediately preceding the stop bit. This 00441 * field must be set when C7816[ISO_7816E] is set/enabled. 00442 * 00443 * Values: 00444 * - 0 - Parity function disabled. 00445 * - 1 - Parity function enabled. 00446 */ 00447 /*@{*/ 00448 #define BP_UART_C1_PE (1U) /*!< Bit position for UART_C1_PE. */ 00449 #define BM_UART_C1_PE (0x02U) /*!< Bit mask for UART_C1_PE. */ 00450 #define BS_UART_C1_PE (1U) /*!< Bit field size in bits for UART_C1_PE. */ 00451 00452 /*! @brief Read current value of the UART_C1_PE field. */ 00453 #define BR_UART_C1_PE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE))) 00454 00455 /*! @brief Format value for bitfield UART_C1_PE. */ 00456 #define BF_UART_C1_PE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_PE) & BM_UART_C1_PE) 00457 00458 /*! @brief Set the PE field to a new value. */ 00459 #define BW_UART_C1_PE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_PE), v)) 00460 /*@}*/ 00461 00462 /*! 00463 * @name Register UART_C1, field ILT[2] (RW) 00464 * 00465 * Determines when the receiver starts counting logic 1s as idle character bits. 00466 * The count begins either after a valid start bit or after the stop bit. If the 00467 * count begins after the start bit, then a string of logic 1s preceding the 00468 * stop bit can cause false recognition of an idle character. Beginning the count 00469 * after the stop bit avoids false idle character recognition, but requires 00470 * properly synchronized transmissions. In case the UART is programmed with ILT = 1, a 00471 * logic of 1'b0 is automatically shifted after a received stop bit, therefore 00472 * resetting the idle count. In case the UART is programmed for IDLE line wakeup 00473 * (RWU = 1 and WAKE = 0), ILT has no effect on when the receiver starts counting 00474 * logic 1s as idle character bits. In idle line wakeup, an idle character is 00475 * recognized at anytime the receiver sees 10, 11, or 12 1s depending on the M, PE, 00476 * and C4[M10] fields. 00477 * 00478 * Values: 00479 * - 0 - Idle character bit count starts after start bit. 00480 * - 1 - Idle character bit count starts after stop bit. 00481 */ 00482 /*@{*/ 00483 #define BP_UART_C1_ILT (2U) /*!< Bit position for UART_C1_ILT. */ 00484 #define BM_UART_C1_ILT (0x04U) /*!< Bit mask for UART_C1_ILT. */ 00485 #define BS_UART_C1_ILT (1U) /*!< Bit field size in bits for UART_C1_ILT. */ 00486 00487 /*! @brief Read current value of the UART_C1_ILT field. */ 00488 #define BR_UART_C1_ILT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT))) 00489 00490 /*! @brief Format value for bitfield UART_C1_ILT. */ 00491 #define BF_UART_C1_ILT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_ILT) & BM_UART_C1_ILT) 00492 00493 /*! @brief Set the ILT field to a new value. */ 00494 #define BW_UART_C1_ILT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_ILT), v)) 00495 /*@}*/ 00496 00497 /*! 00498 * @name Register UART_C1, field WAKE[3] (RW) 00499 * 00500 * Determines which condition wakes the UART: Address mark in the most 00501 * significant bit position of a received data character, or An idle condition on the 00502 * receive pin input signal. 00503 * 00504 * Values: 00505 * - 0 - Idle line wakeup. 00506 * - 1 - Address mark wakeup. 00507 */ 00508 /*@{*/ 00509 #define BP_UART_C1_WAKE (3U) /*!< Bit position for UART_C1_WAKE. */ 00510 #define BM_UART_C1_WAKE (0x08U) /*!< Bit mask for UART_C1_WAKE. */ 00511 #define BS_UART_C1_WAKE (1U) /*!< Bit field size in bits for UART_C1_WAKE. */ 00512 00513 /*! @brief Read current value of the UART_C1_WAKE field. */ 00514 #define BR_UART_C1_WAKE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE))) 00515 00516 /*! @brief Format value for bitfield UART_C1_WAKE. */ 00517 #define BF_UART_C1_WAKE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_WAKE) & BM_UART_C1_WAKE) 00518 00519 /*! @brief Set the WAKE field to a new value. */ 00520 #define BW_UART_C1_WAKE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_WAKE), v)) 00521 /*@}*/ 00522 00523 /*! 00524 * @name Register UART_C1, field M[4] (RW) 00525 * 00526 * This field must be set when C7816[ISO_7816E] is set/enabled. 00527 * 00528 * Values: 00529 * - 0 - Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. 00530 * - 1 - Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. 00531 */ 00532 /*@{*/ 00533 #define BP_UART_C1_M (4U) /*!< Bit position for UART_C1_M. */ 00534 #define BM_UART_C1_M (0x10U) /*!< Bit mask for UART_C1_M. */ 00535 #define BS_UART_C1_M (1U) /*!< Bit field size in bits for UART_C1_M. */ 00536 00537 /*! @brief Read current value of the UART_C1_M field. */ 00538 #define BR_UART_C1_M(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M))) 00539 00540 /*! @brief Format value for bitfield UART_C1_M. */ 00541 #define BF_UART_C1_M(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_M) & BM_UART_C1_M) 00542 00543 /*! @brief Set the M field to a new value. */ 00544 #define BW_UART_C1_M(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_M), v)) 00545 /*@}*/ 00546 00547 /*! 00548 * @name Register UART_C1, field RSRC[5] (RW) 00549 * 00550 * This field has no meaning or effect unless the LOOPS field is set. When LOOPS 00551 * is set, the RSRC field determines the source for the receiver shift register 00552 * input. 00553 * 00554 * Values: 00555 * - 0 - Selects internal loop back mode. The receiver input is internally 00556 * connected to transmitter output. 00557 * - 1 - Single wire UART mode where the receiver input is connected to the 00558 * transmit pin input signal. 00559 */ 00560 /*@{*/ 00561 #define BP_UART_C1_RSRC (5U) /*!< Bit position for UART_C1_RSRC. */ 00562 #define BM_UART_C1_RSRC (0x20U) /*!< Bit mask for UART_C1_RSRC. */ 00563 #define BS_UART_C1_RSRC (1U) /*!< Bit field size in bits for UART_C1_RSRC. */ 00564 00565 /*! @brief Read current value of the UART_C1_RSRC field. */ 00566 #define BR_UART_C1_RSRC(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC))) 00567 00568 /*! @brief Format value for bitfield UART_C1_RSRC. */ 00569 #define BF_UART_C1_RSRC(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_RSRC) & BM_UART_C1_RSRC) 00570 00571 /*! @brief Set the RSRC field to a new value. */ 00572 #define BW_UART_C1_RSRC(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_RSRC), v)) 00573 /*@}*/ 00574 00575 /*! 00576 * @name Register UART_C1, field UARTSWAI[6] (RW) 00577 * 00578 * Values: 00579 * - 0 - UART clock continues to run in Wait mode. 00580 * - 1 - UART clock freezes while CPU is in Wait mode. 00581 */ 00582 /*@{*/ 00583 #define BP_UART_C1_UARTSWAI (6U) /*!< Bit position for UART_C1_UARTSWAI. */ 00584 #define BM_UART_C1_UARTSWAI (0x40U) /*!< Bit mask for UART_C1_UARTSWAI. */ 00585 #define BS_UART_C1_UARTSWAI (1U) /*!< Bit field size in bits for UART_C1_UARTSWAI. */ 00586 00587 /*! @brief Read current value of the UART_C1_UARTSWAI field. */ 00588 #define BR_UART_C1_UARTSWAI(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI))) 00589 00590 /*! @brief Format value for bitfield UART_C1_UARTSWAI. */ 00591 #define BF_UART_C1_UARTSWAI(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_UARTSWAI) & BM_UART_C1_UARTSWAI) 00592 00593 /*! @brief Set the UARTSWAI field to a new value. */ 00594 #define BW_UART_C1_UARTSWAI(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_UARTSWAI), v)) 00595 /*@}*/ 00596 00597 /*! 00598 * @name Register UART_C1, field LOOPS[7] (RW) 00599 * 00600 * When LOOPS is set, the RxD pin is disconnected from the UART and the 00601 * transmitter output is internally connected to the receiver input. The transmitter and 00602 * the receiver must be enabled to use the loop function. 00603 * 00604 * Values: 00605 * - 0 - Normal operation. 00606 * - 1 - Loop mode where transmitter output is internally connected to receiver 00607 * input. The receiver input is determined by RSRC. 00608 */ 00609 /*@{*/ 00610 #define BP_UART_C1_LOOPS (7U) /*!< Bit position for UART_C1_LOOPS. */ 00611 #define BM_UART_C1_LOOPS (0x80U) /*!< Bit mask for UART_C1_LOOPS. */ 00612 #define BS_UART_C1_LOOPS (1U) /*!< Bit field size in bits for UART_C1_LOOPS. */ 00613 00614 /*! @brief Read current value of the UART_C1_LOOPS field. */ 00615 #define BR_UART_C1_LOOPS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS))) 00616 00617 /*! @brief Format value for bitfield UART_C1_LOOPS. */ 00618 #define BF_UART_C1_LOOPS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C1_LOOPS) & BM_UART_C1_LOOPS) 00619 00620 /*! @brief Set the LOOPS field to a new value. */ 00621 #define BW_UART_C1_LOOPS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C1_ADDR(x), BP_UART_C1_LOOPS), v)) 00622 /*@}*/ 00623 00624 /******************************************************************************* 00625 * HW_UART_C2 - UART Control Register 2 00626 ******************************************************************************/ 00627 00628 /*! 00629 * @brief HW_UART_C2 - UART Control Register 2 (RW) 00630 * 00631 * Reset value: 0x00U 00632 * 00633 * This register can be read or written at any time. 00634 */ 00635 typedef union _hw_uart_c2 00636 { 00637 uint8_t U; 00638 struct _hw_uart_c2_bitfields 00639 { 00640 uint8_t SBK : 1; /*!< [0] Send Break */ 00641 uint8_t RWU : 1; /*!< [1] Receiver Wakeup Control */ 00642 uint8_t RE : 1; /*!< [2] Receiver Enable */ 00643 uint8_t TE : 1; /*!< [3] Transmitter Enable */ 00644 uint8_t ILIE : 1; /*!< [4] Idle Line Interrupt DMA Transfer Enable */ 00645 uint8_t RIE : 1; /*!< [5] Receiver Full Interrupt or DMA Transfer 00646 * Enable */ 00647 uint8_t TCIE : 1; /*!< [6] Transmission Complete Interrupt or DMA 00648 * Transfer Enable */ 00649 uint8_t TIE : 1; /*!< [7] Transmitter Interrupt or DMA Transfer 00650 * Enable. */ 00651 } B; 00652 } hw_uart_c2_t; 00653 00654 /*! 00655 * @name Constants and macros for entire UART_C2 register 00656 */ 00657 /*@{*/ 00658 #define HW_UART_C2_ADDR(x) ((x) + 0x3U) 00659 00660 #define HW_UART_C2(x) (*(__IO hw_uart_c2_t *) HW_UART_C2_ADDR(x)) 00661 #define HW_UART_C2_RD(x) (ADDRESS_READ(hw_uart_c2_t, HW_UART_C2_ADDR(x))) 00662 #define HW_UART_C2_WR(x, v) (ADDRESS_WRITE(hw_uart_c2_t, HW_UART_C2_ADDR(x), v)) 00663 #define HW_UART_C2_SET(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) | (v))) 00664 #define HW_UART_C2_CLR(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) & ~(v))) 00665 #define HW_UART_C2_TOG(x, v) (HW_UART_C2_WR(x, HW_UART_C2_RD(x) ^ (v))) 00666 /*@}*/ 00667 00668 /* 00669 * Constants & macros for individual UART_C2 bitfields 00670 */ 00671 00672 /*! 00673 * @name Register UART_C2, field SBK[0] (RW) 00674 * 00675 * Toggling SBK sends one break character from the following: See Transmitting 00676 * break characters for the number of logic 0s for the different configurations. 00677 * Toggling implies clearing the SBK field before the break character has finished 00678 * transmitting. As long as SBK is set, the transmitter continues to send 00679 * complete break characters (10, 11, or 12 bits, or 13 or 14 bits, or 15 or 16 bits). 00680 * Ensure that C2[TE] is asserted atleast 1 clock before assertion of this bit. 00681 * 10, 11, or 12 logic 0s if S2[BRK13] is cleared 13 or 14 logic 0s if S2[BRK13] 00682 * is set. 15 or 16 logic 0s if BDH[SBNS] is set. This field must be cleared when 00683 * C7816[ISO_7816E] is set. 00684 * 00685 * Values: 00686 * - 0 - Normal transmitter operation. 00687 * - 1 - Queue break characters to be sent. 00688 */ 00689 /*@{*/ 00690 #define BP_UART_C2_SBK (0U) /*!< Bit position for UART_C2_SBK. */ 00691 #define BM_UART_C2_SBK (0x01U) /*!< Bit mask for UART_C2_SBK. */ 00692 #define BS_UART_C2_SBK (1U) /*!< Bit field size in bits for UART_C2_SBK. */ 00693 00694 /*! @brief Read current value of the UART_C2_SBK field. */ 00695 #define BR_UART_C2_SBK(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK))) 00696 00697 /*! @brief Format value for bitfield UART_C2_SBK. */ 00698 #define BF_UART_C2_SBK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_SBK) & BM_UART_C2_SBK) 00699 00700 /*! @brief Set the SBK field to a new value. */ 00701 #define BW_UART_C2_SBK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_SBK), v)) 00702 /*@}*/ 00703 00704 /*! 00705 * @name Register UART_C2, field RWU[1] (RW) 00706 * 00707 * This field can be set to place the UART receiver in a standby state. RWU 00708 * automatically clears when an RWU event occurs, that is, an IDLE event when 00709 * C1[WAKE] is clear or an address match when C1[WAKE] is set. This field must be 00710 * cleared when C7816[ISO_7816E] is set. RWU must be set only with C1[WAKE] = 0 (wakeup 00711 * on idle) if the channel is currently not idle. This can be determined by 00712 * S2[RAF]. If the flag is set to wake up an IDLE event and the channel is already 00713 * idle, it is possible that the UART will discard data. This is because the data 00714 * must be received or a LIN break detected after an IDLE is detected before IDLE 00715 * is allowed to reasserted. 00716 * 00717 * Values: 00718 * - 0 - Normal operation. 00719 * - 1 - RWU enables the wakeup function and inhibits further receiver interrupt 00720 * requests. Normally, hardware wakes the receiver by automatically clearing 00721 * RWU. 00722 */ 00723 /*@{*/ 00724 #define BP_UART_C2_RWU (1U) /*!< Bit position for UART_C2_RWU. */ 00725 #define BM_UART_C2_RWU (0x02U) /*!< Bit mask for UART_C2_RWU. */ 00726 #define BS_UART_C2_RWU (1U) /*!< Bit field size in bits for UART_C2_RWU. */ 00727 00728 /*! @brief Read current value of the UART_C2_RWU field. */ 00729 #define BR_UART_C2_RWU(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU))) 00730 00731 /*! @brief Format value for bitfield UART_C2_RWU. */ 00732 #define BF_UART_C2_RWU(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RWU) & BM_UART_C2_RWU) 00733 00734 /*! @brief Set the RWU field to a new value. */ 00735 #define BW_UART_C2_RWU(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RWU), v)) 00736 /*@}*/ 00737 00738 /*! 00739 * @name Register UART_C2, field RE[2] (RW) 00740 * 00741 * Enables the UART receiver. 00742 * 00743 * Values: 00744 * - 0 - Receiver off. 00745 * - 1 - Receiver on. 00746 */ 00747 /*@{*/ 00748 #define BP_UART_C2_RE (2U) /*!< Bit position for UART_C2_RE. */ 00749 #define BM_UART_C2_RE (0x04U) /*!< Bit mask for UART_C2_RE. */ 00750 #define BS_UART_C2_RE (1U) /*!< Bit field size in bits for UART_C2_RE. */ 00751 00752 /*! @brief Read current value of the UART_C2_RE field. */ 00753 #define BR_UART_C2_RE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE))) 00754 00755 /*! @brief Format value for bitfield UART_C2_RE. */ 00756 #define BF_UART_C2_RE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RE) & BM_UART_C2_RE) 00757 00758 /*! @brief Set the RE field to a new value. */ 00759 #define BW_UART_C2_RE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RE), v)) 00760 /*@}*/ 00761 00762 /*! 00763 * @name Register UART_C2, field TE[3] (RW) 00764 * 00765 * Enables the UART transmitter. TE can be used to queue an idle preamble by 00766 * clearing and then setting TE. When C7816[ISO_7816E] is set/enabled and 00767 * C7816[TTYPE] = 1, this field is automatically cleared after the requested block has been 00768 * transmitted. This condition is detected when TL7816[TLEN] = 0 and four 00769 * additional characters are transmitted. 00770 * 00771 * Values: 00772 * - 0 - Transmitter off. 00773 * - 1 - Transmitter on. 00774 */ 00775 /*@{*/ 00776 #define BP_UART_C2_TE (3U) /*!< Bit position for UART_C2_TE. */ 00777 #define BM_UART_C2_TE (0x08U) /*!< Bit mask for UART_C2_TE. */ 00778 #define BS_UART_C2_TE (1U) /*!< Bit field size in bits for UART_C2_TE. */ 00779 00780 /*! @brief Read current value of the UART_C2_TE field. */ 00781 #define BR_UART_C2_TE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE))) 00782 00783 /*! @brief Format value for bitfield UART_C2_TE. */ 00784 #define BF_UART_C2_TE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TE) & BM_UART_C2_TE) 00785 00786 /*! @brief Set the TE field to a new value. */ 00787 #define BW_UART_C2_TE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TE), v)) 00788 /*@}*/ 00789 00790 /*! 00791 * @name Register UART_C2, field ILIE[4] (RW) 00792 * 00793 * Enables the idle line flag, S1[IDLE], to generate interrupt requestsor DMA 00794 * transfer requests based on the state of C5[ILDMAS]. 00795 * 00796 * Values: 00797 * - 0 - IDLE interrupt requests disabled. and DMA transfer 00798 * - 1 - IDLE interrupt requests enabled. or DMA transfer 00799 */ 00800 /*@{*/ 00801 #define BP_UART_C2_ILIE (4U) /*!< Bit position for UART_C2_ILIE. */ 00802 #define BM_UART_C2_ILIE (0x10U) /*!< Bit mask for UART_C2_ILIE. */ 00803 #define BS_UART_C2_ILIE (1U) /*!< Bit field size in bits for UART_C2_ILIE. */ 00804 00805 /*! @brief Read current value of the UART_C2_ILIE field. */ 00806 #define BR_UART_C2_ILIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE))) 00807 00808 /*! @brief Format value for bitfield UART_C2_ILIE. */ 00809 #define BF_UART_C2_ILIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_ILIE) & BM_UART_C2_ILIE) 00810 00811 /*! @brief Set the ILIE field to a new value. */ 00812 #define BW_UART_C2_ILIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_ILIE), v)) 00813 /*@}*/ 00814 00815 /*! 00816 * @name Register UART_C2, field RIE[5] (RW) 00817 * 00818 * Enables S1[RDRF] to generate interrupt requests or DMA transfer requests, 00819 * based on the state of C5[RDMAS]. 00820 * 00821 * Values: 00822 * - 0 - RDRF interrupt and DMA transfer requests disabled. 00823 * - 1 - RDRF interrupt or DMA transfer requests enabled. 00824 */ 00825 /*@{*/ 00826 #define BP_UART_C2_RIE (5U) /*!< Bit position for UART_C2_RIE. */ 00827 #define BM_UART_C2_RIE (0x20U) /*!< Bit mask for UART_C2_RIE. */ 00828 #define BS_UART_C2_RIE (1U) /*!< Bit field size in bits for UART_C2_RIE. */ 00829 00830 /*! @brief Read current value of the UART_C2_RIE field. */ 00831 #define BR_UART_C2_RIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE))) 00832 00833 /*! @brief Format value for bitfield UART_C2_RIE. */ 00834 #define BF_UART_C2_RIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_RIE) & BM_UART_C2_RIE) 00835 00836 /*! @brief Set the RIE field to a new value. */ 00837 #define BW_UART_C2_RIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_RIE), v)) 00838 /*@}*/ 00839 00840 /*! 00841 * @name Register UART_C2, field TCIE[6] (RW) 00842 * 00843 * Enables the transmission complete flag, S1[TC], to generate interrupt 00844 * requests . or DMA transfer requests based on the state of C5[TCDMAS] If C2[TCIE] and 00845 * C5[TCDMAS] are both set, then TIE must be cleared, and D[D] must not be 00846 * written unless servicing a DMA request. 00847 * 00848 * Values: 00849 * - 0 - TC interrupt and DMA transfer requests disabled. 00850 * - 1 - TC interrupt or DMA transfer requests enabled. 00851 */ 00852 /*@{*/ 00853 #define BP_UART_C2_TCIE (6U) /*!< Bit position for UART_C2_TCIE. */ 00854 #define BM_UART_C2_TCIE (0x40U) /*!< Bit mask for UART_C2_TCIE. */ 00855 #define BS_UART_C2_TCIE (1U) /*!< Bit field size in bits for UART_C2_TCIE. */ 00856 00857 /*! @brief Read current value of the UART_C2_TCIE field. */ 00858 #define BR_UART_C2_TCIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE))) 00859 00860 /*! @brief Format value for bitfield UART_C2_TCIE. */ 00861 #define BF_UART_C2_TCIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TCIE) & BM_UART_C2_TCIE) 00862 00863 /*! @brief Set the TCIE field to a new value. */ 00864 #define BW_UART_C2_TCIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TCIE), v)) 00865 /*@}*/ 00866 00867 /*! 00868 * @name Register UART_C2, field TIE[7] (RW) 00869 * 00870 * Enables S1[TDRE] to generate interrupt requests or DMA transfer requests, 00871 * based on the state of C5[TDMAS]. If C2[TIE] and C5[TDMAS] are both set, then TCIE 00872 * must be cleared, and D[D] must not be written unless servicing a DMA request. 00873 * 00874 * Values: 00875 * - 0 - TDRE interrupt and DMA transfer requests disabled. 00876 * - 1 - TDRE interrupt or DMA transfer requests enabled. 00877 */ 00878 /*@{*/ 00879 #define BP_UART_C2_TIE (7U) /*!< Bit position for UART_C2_TIE. */ 00880 #define BM_UART_C2_TIE (0x80U) /*!< Bit mask for UART_C2_TIE. */ 00881 #define BS_UART_C2_TIE (1U) /*!< Bit field size in bits for UART_C2_TIE. */ 00882 00883 /*! @brief Read current value of the UART_C2_TIE field. */ 00884 #define BR_UART_C2_TIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE))) 00885 00886 /*! @brief Format value for bitfield UART_C2_TIE. */ 00887 #define BF_UART_C2_TIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C2_TIE) & BM_UART_C2_TIE) 00888 00889 /*! @brief Set the TIE field to a new value. */ 00890 #define BW_UART_C2_TIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C2_ADDR(x), BP_UART_C2_TIE), v)) 00891 /*@}*/ 00892 00893 /******************************************************************************* 00894 * HW_UART_S1 - UART Status Register 1 00895 ******************************************************************************/ 00896 00897 /*! 00898 * @brief HW_UART_S1 - UART Status Register 1 (RO) 00899 * 00900 * Reset value: 0xC0U 00901 * 00902 * The S1 register provides inputs to the MCU for generation of UART interrupts 00903 * or DMA requests. This register can also be polled by the MCU to check the 00904 * status of its fields. To clear a flag, the status register should be read followed 00905 * by a read or write to D register, depending on the interrupt flag type. Other 00906 * instructions can be executed between the two steps as long the handling of 00907 * I/O is not compromised, but the order of operations is important for flag 00908 * clearing. When a flag is configured to trigger a DMA request, assertion of the 00909 * associated DMA done signal from the DMA controller clears the flag. If the 00910 * condition that results in the assertion of the flag, interrupt, or DMA request is not 00911 * resolved prior to clearing the flag, the flag, and interrupt/DMA request, 00912 * reasserts. For example, if the DMA or interrupt service routine fails to write 00913 * sufficient data to the transmit buffer to raise it above the watermark level, the 00914 * flag reasserts and generates another interrupt or DMA request. Reading an 00915 * empty data register to clear one of the flags of the S1 register causes the FIFO 00916 * pointers to become misaligned. A receive FIFO flush reinitializes the 00917 * pointers. A better way to prevent this situation is to always leave one byte in FIFO 00918 * and this byte will be read eventually in clearing the flag bit. 00919 */ 00920 typedef union _hw_uart_s1 00921 { 00922 uint8_t U; 00923 struct _hw_uart_s1_bitfields 00924 { 00925 uint8_t PF : 1; /*!< [0] Parity Error Flag */ 00926 uint8_t FE : 1; /*!< [1] Framing Error Flag */ 00927 uint8_t NF : 1; /*!< [2] Noise Flag */ 00928 uint8_t OR : 1; /*!< [3] Receiver Overrun Flag */ 00929 uint8_t IDLE : 1; /*!< [4] Idle Line Flag */ 00930 uint8_t RDRF : 1; /*!< [5] Receive Data Register Full Flag */ 00931 uint8_t TC : 1; /*!< [6] Transmit Complete Flag */ 00932 uint8_t TDRE : 1; /*!< [7] Transmit Data Register Empty Flag */ 00933 } B; 00934 } hw_uart_s1_t; 00935 00936 /*! 00937 * @name Constants and macros for entire UART_S1 register 00938 */ 00939 /*@{*/ 00940 #define HW_UART_S1_ADDR(x) ((x) + 0x4U) 00941 00942 #define HW_UART_S1(x) (*(__I hw_uart_s1_t *) HW_UART_S1_ADDR(x)) 00943 #define HW_UART_S1_RD(x) (ADDRESS_READ(hw_uart_s1_t, HW_UART_S1_ADDR(x))) 00944 /*@}*/ 00945 00946 /* 00947 * Constants & macros for individual UART_S1 bitfields 00948 */ 00949 00950 /*! 00951 * @name Register UART_S1, field PF[0] (RO) 00952 * 00953 * PF is set when PE is set and the parity of the received data does not match 00954 * its parity bit. The PF is not set in the case of an overrun condition. When PF 00955 * is set, it indicates only that a dataword was received with parity error since 00956 * the last time it was cleared. There is no guarantee that the first dataword 00957 * read from the receive buffer has a parity error or that there is only one 00958 * dataword in the buffer that was received with a parity error, unless the receive 00959 * buffer has a depth of one. To clear PF, read S1 and then read D., S2[LBKDE] is 00960 * disabled, Within the receive buffer structure the received dataword is tagged 00961 * if it is received with a parity error. This information is available by reading 00962 * the ED register prior to reading the D register. 00963 * 00964 * Values: 00965 * - 0 - No parity error detected since the last time this flag was cleared. If 00966 * the receive buffer has a depth greater than 1, then there may be data in 00967 * the receive buffer what was received with a parity error. 00968 * - 1 - At least one dataword was received with a parity error since the last 00969 * time this flag was cleared. 00970 */ 00971 /*@{*/ 00972 #define BP_UART_S1_PF (0U) /*!< Bit position for UART_S1_PF. */ 00973 #define BM_UART_S1_PF (0x01U) /*!< Bit mask for UART_S1_PF. */ 00974 #define BS_UART_S1_PF (1U) /*!< Bit field size in bits for UART_S1_PF. */ 00975 00976 /*! @brief Read current value of the UART_S1_PF field. */ 00977 #define BR_UART_S1_PF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_PF))) 00978 /*@}*/ 00979 00980 /*! 00981 * @name Register UART_S1, field FE[1] (RO) 00982 * 00983 * FE is set when a logic 0 is accepted as the stop bit. When BDH[SBNS] is set, 00984 * then FE will set when a logic 0 is accepted for either of the two stop bits. 00985 * FE does not set in the case of an overrun or while the LIN break detect feature 00986 * is enabled (S2[LBKDE] = 1). FE inhibits further data reception until it is 00987 * cleared. To clear FE, read S1 with FE set and then read D. The last data in the 00988 * receive buffer represents the data that was received with the frame error 00989 * enabled. Framing errors are not supported when 7816E is set/enabled. However, if 00990 * this flag is set, data is still not received in 7816 mode. 00991 * 00992 * Values: 00993 * - 0 - No framing error detected. 00994 * - 1 - Framing error. 00995 */ 00996 /*@{*/ 00997 #define BP_UART_S1_FE (1U) /*!< Bit position for UART_S1_FE. */ 00998 #define BM_UART_S1_FE (0x02U) /*!< Bit mask for UART_S1_FE. */ 00999 #define BS_UART_S1_FE (1U) /*!< Bit field size in bits for UART_S1_FE. */ 01000 01001 /*! @brief Read current value of the UART_S1_FE field. */ 01002 #define BR_UART_S1_FE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_FE))) 01003 /*@}*/ 01004 01005 /*! 01006 * @name Register UART_S1, field NF[2] (RO) 01007 * 01008 * NF is set when the UART detects noise on the receiver input. NF does not 01009 * become set in the case of an overrun or while the LIN break detect feature is 01010 * enabled (S2[LBKDE] = 1). When NF is set, it indicates only that a dataword has 01011 * been received with noise since the last time it was cleared. There is no 01012 * guarantee that the first dataword read from the receive buffer has noise or that there 01013 * is only one dataword in the buffer that was received with noise unless the 01014 * receive buffer has a depth of one. To clear NF, read S1 and then read D. 01015 * 01016 * Values: 01017 * - 0 - No noise detected since the last time this flag was cleared. If the 01018 * receive buffer has a depth greater than 1 then there may be data in the 01019 * receiver buffer that was received with noise. 01020 * - 1 - At least one dataword was received with noise detected since the last 01021 * time the flag was cleared. 01022 */ 01023 /*@{*/ 01024 #define BP_UART_S1_NF (2U) /*!< Bit position for UART_S1_NF. */ 01025 #define BM_UART_S1_NF (0x04U) /*!< Bit mask for UART_S1_NF. */ 01026 #define BS_UART_S1_NF (1U) /*!< Bit field size in bits for UART_S1_NF. */ 01027 01028 /*! @brief Read current value of the UART_S1_NF field. */ 01029 #define BR_UART_S1_NF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_NF))) 01030 /*@}*/ 01031 01032 /*! 01033 * @name Register UART_S1, field OR[3] (RO) 01034 * 01035 * OR is set when software fails to prevent the receive data register from 01036 * overflowing with data. The OR bit is set immediately after the stop bit has been 01037 * completely received for the dataword that overflows the buffer and all the other 01038 * error flags (FE, NF, and PF) are prevented from setting. The data in the 01039 * shift register is lost, but the data already in the UART data registers is not 01040 * affected. If the OR flag is set, no data is stored in the data buffer even if 01041 * sufficient room exists. Additionally, while the OR flag is set, the RDRF and IDLE 01042 * flags are blocked from asserting, that is, transition from an inactive to an 01043 * active state. To clear OR, read S1 when OR is set and then read D. See 01044 * functional description for more details regarding the operation of the OR bit.If 01045 * LBKDE is enabled and a LIN Break is detected, the OR field asserts if S2[LBKDIF] 01046 * is not cleared before the next data character is received. In 7816 mode, it is 01047 * possible to configure a NACK to be returned by programing C7816[ONACK]. 01048 * 01049 * Values: 01050 * - 0 - No overrun has occurred since the last time the flag was cleared. 01051 * - 1 - Overrun has occurred or the overrun flag has not been cleared since the 01052 * last overrun occured. 01053 */ 01054 /*@{*/ 01055 #define BP_UART_S1_OR (3U) /*!< Bit position for UART_S1_OR. */ 01056 #define BM_UART_S1_OR (0x08U) /*!< Bit mask for UART_S1_OR. */ 01057 #define BS_UART_S1_OR (1U) /*!< Bit field size in bits for UART_S1_OR. */ 01058 01059 /*! @brief Read current value of the UART_S1_OR field. */ 01060 #define BR_UART_S1_OR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_OR))) 01061 /*@}*/ 01062 01063 /*! 01064 * @name Register UART_S1, field IDLE[4] (RO) 01065 * 01066 * After the IDLE flag is cleared, a frame must be received (although not 01067 * necessarily stored in the data buffer, for example if C2[RWU] is set), or a LIN 01068 * break character must set the S2[LBKDIF] flag before an idle condition can set the 01069 * IDLE flag. To clear IDLE, read UART status S1 with IDLE set and then read D. 01070 * IDLE is set when either of the following appear on the receiver input: 10 01071 * consecutive logic 1s if C1[M] = 0 11 consecutive logic 1s if C1[M] = 1 and C4[M10] 01072 * = 0 12 consecutive logic 1s if C1[M] = 1, C4[M10] = 1, and C1[PE] = 1 Idle 01073 * detection is not supported when 7816E is set/enabled and hence this flag is 01074 * ignored. When RWU is set and WAKE is cleared, an idle line condition sets the IDLE 01075 * flag if RWUID is set, else the IDLE flag does not become set. 01076 * 01077 * Values: 01078 * - 0 - Receiver input is either active now or has never become active since 01079 * the IDLE flag was last cleared. 01080 * - 1 - Receiver input has become idle or the flag has not been cleared since 01081 * it last asserted. 01082 */ 01083 /*@{*/ 01084 #define BP_UART_S1_IDLE (4U) /*!< Bit position for UART_S1_IDLE. */ 01085 #define BM_UART_S1_IDLE (0x10U) /*!< Bit mask for UART_S1_IDLE. */ 01086 #define BS_UART_S1_IDLE (1U) /*!< Bit field size in bits for UART_S1_IDLE. */ 01087 01088 /*! @brief Read current value of the UART_S1_IDLE field. */ 01089 #define BR_UART_S1_IDLE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_IDLE))) 01090 /*@}*/ 01091 01092 /*! 01093 * @name Register UART_S1, field RDRF[5] (RO) 01094 * 01095 * RDRF is set when the number of datawords in the receive buffer is equal to or 01096 * more than the number indicated by RWFIFO[RXWATER]. A dataword that is in the 01097 * process of being received is not included in the count. To clear RDRF, read S1 01098 * when RDRF is set and then read D. For more efficient interrupt and DMA 01099 * operation, read all data except the final value from the buffer, using D/C3[T8]/ED. 01100 * Then read S1 and the final data value, resulting in the clearing of the RDRF 01101 * flag. Even if RDRF is set, data will continue to be received until an overrun 01102 * condition occurs.RDRF is prevented from setting while S2[LBKDE] is set. 01103 * Additionally, when S2[LBKDE] is set, the received datawords are stored in the receive 01104 * buffer but over-write each other. 01105 * 01106 * Values: 01107 * - 0 - The number of datawords in the receive buffer is less than the number 01108 * indicated by RXWATER. 01109 * - 1 - The number of datawords in the receive buffer is equal to or greater 01110 * than the number indicated by RXWATER at some point in time since this flag 01111 * was last cleared. 01112 */ 01113 /*@{*/ 01114 #define BP_UART_S1_RDRF (5U) /*!< Bit position for UART_S1_RDRF. */ 01115 #define BM_UART_S1_RDRF (0x20U) /*!< Bit mask for UART_S1_RDRF. */ 01116 #define BS_UART_S1_RDRF (1U) /*!< Bit field size in bits for UART_S1_RDRF. */ 01117 01118 /*! @brief Read current value of the UART_S1_RDRF field. */ 01119 #define BR_UART_S1_RDRF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_RDRF))) 01120 /*@}*/ 01121 01122 /*! 01123 * @name Register UART_S1, field TC[6] (RO) 01124 * 01125 * TC is set when the transmit buffer is empty and no data, preamble, or break 01126 * character is being transmitted. When TC is set, the transmit data output signal 01127 * becomes idle (logic 1). TC is cleared by reading S1 with TC set and then 01128 * doing one of the following: When C7816[ISO_7816E] is set/enabled, this field is 01129 * set after any NACK signal has been received, but prior to any corresponding 01130 * guard times expiring. Writing to D to transmit new data. Queuing a preamble by 01131 * clearing and then setting C2[TE]. Queuing a break character by writing 1 to SBK 01132 * in C2. 01133 * 01134 * Values: 01135 * - 0 - Transmitter active (sending data, a preamble, or a break). 01136 * - 1 - Transmitter idle (transmission activity complete). 01137 */ 01138 /*@{*/ 01139 #define BP_UART_S1_TC (6U) /*!< Bit position for UART_S1_TC. */ 01140 #define BM_UART_S1_TC (0x40U) /*!< Bit mask for UART_S1_TC. */ 01141 #define BS_UART_S1_TC (1U) /*!< Bit field size in bits for UART_S1_TC. */ 01142 01143 /*! @brief Read current value of the UART_S1_TC field. */ 01144 #define BR_UART_S1_TC(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TC))) 01145 /*@}*/ 01146 01147 /*! 01148 * @name Register UART_S1, field TDRE[7] (RO) 01149 * 01150 * TDRE will set when the number of datawords in the transmit buffer (D and 01151 * C3[T8])is equal to or less than the number indicated by TWFIFO[TXWATER]. A 01152 * character that is in the process of being transmitted is not included in the count. 01153 * To clear TDRE, read S1 when TDRE is set and then write to the UART data 01154 * register (D). For more efficient interrupt servicing, all data except the final value 01155 * to be written to the buffer must be written to D/C3[T8]. Then S1 can be read 01156 * before writing the final data value, resulting in the clearing of the TRDE 01157 * flag. This is more efficient because the TDRE reasserts until the watermark has 01158 * been exceeded. So, attempting to clear the TDRE with every write will be 01159 * ineffective until sufficient data has been written. 01160 * 01161 * Values: 01162 * - 0 - The amount of data in the transmit buffer is greater than the value 01163 * indicated by TWFIFO[TXWATER]. 01164 * - 1 - The amount of data in the transmit buffer is less than or equal to the 01165 * value indicated by TWFIFO[TXWATER] at some point in time since the flag 01166 * has been cleared. 01167 */ 01168 /*@{*/ 01169 #define BP_UART_S1_TDRE (7U) /*!< Bit position for UART_S1_TDRE. */ 01170 #define BM_UART_S1_TDRE (0x80U) /*!< Bit mask for UART_S1_TDRE. */ 01171 #define BS_UART_S1_TDRE (1U) /*!< Bit field size in bits for UART_S1_TDRE. */ 01172 01173 /*! @brief Read current value of the UART_S1_TDRE field. */ 01174 #define BR_UART_S1_TDRE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S1_ADDR(x), BP_UART_S1_TDRE))) 01175 /*@}*/ 01176 01177 /******************************************************************************* 01178 * HW_UART_S2 - UART Status Register 2 01179 ******************************************************************************/ 01180 01181 /*! 01182 * @brief HW_UART_S2 - UART Status Register 2 (RW) 01183 * 01184 * Reset value: 0x00U 01185 * 01186 * The S2 register provides inputs to the MCU for generation of UART interrupts 01187 * or DMA requests. Also, this register can be polled by the MCU to check the 01188 * status of these bits. This register can be read or written at any time, with the 01189 * exception of the MSBF and RXINV bits, which should be changed by the user only 01190 * between transmit and receive packets. 01191 */ 01192 typedef union _hw_uart_s2 01193 { 01194 uint8_t U; 01195 struct _hw_uart_s2_bitfields 01196 { 01197 uint8_t RAF : 1; /*!< [0] Receiver Active Flag */ 01198 uint8_t LBKDE : 1; /*!< [1] LIN Break Detection Enable */ 01199 uint8_t BRK13 : 1; /*!< [2] Break Transmit Character Length */ 01200 uint8_t RWUID : 1; /*!< [3] Receive Wakeup Idle Detect */ 01201 uint8_t RXINV : 1; /*!< [4] Receive Data Inversion */ 01202 uint8_t MSBF : 1; /*!< [5] Most Significant Bit First */ 01203 uint8_t RXEDGIF : 1; /*!< [6] RxD Pin Active Edge Interrupt Flag */ 01204 uint8_t LBKDIF : 1; /*!< [7] LIN Break Detect Interrupt Flag */ 01205 } B; 01206 } hw_uart_s2_t; 01207 01208 /*! 01209 * @name Constants and macros for entire UART_S2 register 01210 */ 01211 /*@{*/ 01212 #define HW_UART_S2_ADDR(x) ((x) + 0x5U) 01213 01214 #define HW_UART_S2(x) (*(__IO hw_uart_s2_t *) HW_UART_S2_ADDR(x)) 01215 #define HW_UART_S2_RD(x) (ADDRESS_READ(hw_uart_s2_t, HW_UART_S2_ADDR(x))) 01216 #define HW_UART_S2_WR(x, v) (ADDRESS_WRITE(hw_uart_s2_t, HW_UART_S2_ADDR(x), v)) 01217 #define HW_UART_S2_SET(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) | (v))) 01218 #define HW_UART_S2_CLR(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) & ~(v))) 01219 #define HW_UART_S2_TOG(x, v) (HW_UART_S2_WR(x, HW_UART_S2_RD(x) ^ (v))) 01220 /*@}*/ 01221 01222 /* 01223 * Constants & macros for individual UART_S2 bitfields 01224 */ 01225 01226 /*! 01227 * @name Register UART_S2, field RAF[0] (RO) 01228 * 01229 * RAF is set when the UART receiver detects a logic 0 during the RT1 time 01230 * period of the start bit search. RAF is cleared when the receiver detects an idle 01231 * character when C7816[ISO7816E] is cleared/disabled. When C7816[ISO7816E] is 01232 * enabled, the RAF is cleared if the C7816[TTYPE] = 0 expires or the C7816[TTYPE] = 01233 * 1 expires.In case C7816[ISO7816E] is set and C7816[TTYPE] = 0, it is possible 01234 * to configure the guard time to 12. However, if a NACK is required to be 01235 * transmitted, the data transfer actually takes 13 ETU with the 13th ETU slot being a 01236 * inactive buffer. Therefore, in this situation, the RAF may deassert one ETU 01237 * prior to actually being inactive. 01238 * 01239 * Values: 01240 * - 0 - UART receiver idle/inactive waiting for a start bit. 01241 * - 1 - UART receiver active, RxD input not idle. 01242 */ 01243 /*@{*/ 01244 #define BP_UART_S2_RAF (0U) /*!< Bit position for UART_S2_RAF. */ 01245 #define BM_UART_S2_RAF (0x01U) /*!< Bit mask for UART_S2_RAF. */ 01246 #define BS_UART_S2_RAF (1U) /*!< Bit field size in bits for UART_S2_RAF. */ 01247 01248 /*! @brief Read current value of the UART_S2_RAF field. */ 01249 #define BR_UART_S2_RAF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RAF))) 01250 /*@}*/ 01251 01252 /*! 01253 * @name Register UART_S2, field LBKDE[1] (RW) 01254 * 01255 * Enables the LIN Break detection feature. While LBKDE is set, S1[RDRF], 01256 * S1[NF], S1[FE], and S1[PF] are prevented from setting. When LBKDE is set, see . 01257 * Overrun operation LBKDE must be cleared when C7816[ISO7816E] is set. 01258 * 01259 * Values: 01260 * - 0 - Break character detection is disabled. 01261 * - 1 - Break character is detected at length of 11 bit times if C1[M] = 0 or 01262 * 12 bits time if C1[M] = 1. 01263 */ 01264 /*@{*/ 01265 #define BP_UART_S2_LBKDE (1U) /*!< Bit position for UART_S2_LBKDE. */ 01266 #define BM_UART_S2_LBKDE (0x02U) /*!< Bit mask for UART_S2_LBKDE. */ 01267 #define BS_UART_S2_LBKDE (1U) /*!< Bit field size in bits for UART_S2_LBKDE. */ 01268 01269 /*! @brief Read current value of the UART_S2_LBKDE field. */ 01270 #define BR_UART_S2_LBKDE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE))) 01271 01272 /*! @brief Format value for bitfield UART_S2_LBKDE. */ 01273 #define BF_UART_S2_LBKDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDE) & BM_UART_S2_LBKDE) 01274 01275 /*! @brief Set the LBKDE field to a new value. */ 01276 #define BW_UART_S2_LBKDE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDE), v)) 01277 /*@}*/ 01278 01279 /*! 01280 * @name Register UART_S2, field BRK13[2] (RW) 01281 * 01282 * Determines whether the transmit break character is 10, 11, or 12 bits long, 01283 * or 13 or 14 bits long. See for the length of the break character for the 01284 * different configurations. The detection of a framing error is not affected by this 01285 * field. Transmitting break characters 01286 * 01287 * Values: 01288 * - 0 - Break character is 10, 11, or 12 bits long. 01289 * - 1 - Break character is 13 or 14 bits long. 01290 */ 01291 /*@{*/ 01292 #define BP_UART_S2_BRK13 (2U) /*!< Bit position for UART_S2_BRK13. */ 01293 #define BM_UART_S2_BRK13 (0x04U) /*!< Bit mask for UART_S2_BRK13. */ 01294 #define BS_UART_S2_BRK13 (1U) /*!< Bit field size in bits for UART_S2_BRK13. */ 01295 01296 /*! @brief Read current value of the UART_S2_BRK13 field. */ 01297 #define BR_UART_S2_BRK13(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13))) 01298 01299 /*! @brief Format value for bitfield UART_S2_BRK13. */ 01300 #define BF_UART_S2_BRK13(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_BRK13) & BM_UART_S2_BRK13) 01301 01302 /*! @brief Set the BRK13 field to a new value. */ 01303 #define BW_UART_S2_BRK13(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_BRK13), v)) 01304 /*@}*/ 01305 01306 /*! 01307 * @name Register UART_S2, field RWUID[3] (RW) 01308 * 01309 * When RWU is set and WAKE is cleared, this field controls whether the idle 01310 * character that wakes the receiver sets S1[IDLE]. This field must be cleared when 01311 * C7816[ISO7816E] is set/enabled. 01312 * 01313 * Values: 01314 * - 0 - S1[IDLE] is not set upon detection of an idle character. 01315 * - 1 - S1[IDLE] is set upon detection of an idle character. 01316 */ 01317 /*@{*/ 01318 #define BP_UART_S2_RWUID (3U) /*!< Bit position for UART_S2_RWUID. */ 01319 #define BM_UART_S2_RWUID (0x08U) /*!< Bit mask for UART_S2_RWUID. */ 01320 #define BS_UART_S2_RWUID (1U) /*!< Bit field size in bits for UART_S2_RWUID. */ 01321 01322 /*! @brief Read current value of the UART_S2_RWUID field. */ 01323 #define BR_UART_S2_RWUID(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID))) 01324 01325 /*! @brief Format value for bitfield UART_S2_RWUID. */ 01326 #define BF_UART_S2_RWUID(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RWUID) & BM_UART_S2_RWUID) 01327 01328 /*! @brief Set the RWUID field to a new value. */ 01329 #define BW_UART_S2_RWUID(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RWUID), v)) 01330 /*@}*/ 01331 01332 /*! 01333 * @name Register UART_S2, field RXINV[4] (RW) 01334 * 01335 * Setting this field reverses the polarity of the received data input. In NRZ 01336 * format, a one is represented by a mark and a zero is represented by a space for 01337 * normal polarity, and the opposite for inverted polarity. In IrDA format, a 01338 * zero is represented by short high pulse in the middle of a bit time remaining 01339 * idle low for a one for normal polarity. A zero is represented by a short low 01340 * pulse in the middle of a bit time remaining idle high for a one for inverted 01341 * polarity. This field is automatically set when C7816[INIT] and C7816[ISO7816E] are 01342 * enabled and an initial character is detected in T = 0 protocol mode. Setting 01343 * RXINV inverts the RxD input for data bits, start and stop bits, break, and 01344 * idle. When C7816[ISO7816E] is set/enabled, only the data bits and the parity bit 01345 * are inverted. 01346 * 01347 * Values: 01348 * - 0 - Receive data is not inverted. 01349 * - 1 - Receive data is inverted. 01350 */ 01351 /*@{*/ 01352 #define BP_UART_S2_RXINV (4U) /*!< Bit position for UART_S2_RXINV. */ 01353 #define BM_UART_S2_RXINV (0x10U) /*!< Bit mask for UART_S2_RXINV. */ 01354 #define BS_UART_S2_RXINV (1U) /*!< Bit field size in bits for UART_S2_RXINV. */ 01355 01356 /*! @brief Read current value of the UART_S2_RXINV field. */ 01357 #define BR_UART_S2_RXINV(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV))) 01358 01359 /*! @brief Format value for bitfield UART_S2_RXINV. */ 01360 #define BF_UART_S2_RXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXINV) & BM_UART_S2_RXINV) 01361 01362 /*! @brief Set the RXINV field to a new value. */ 01363 #define BW_UART_S2_RXINV(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXINV), v)) 01364 /*@}*/ 01365 01366 /*! 01367 * @name Register UART_S2, field MSBF[5] (RW) 01368 * 01369 * Setting this field reverses the order of the bits that are transmitted and 01370 * received on the wire. This field does not affect the polarity of the bits, the 01371 * location of the parity bit, or the location of the start or stop bits. This 01372 * field is automatically set when C7816[INIT] and C7816[ISO7816E] are enabled and 01373 * an initial character is detected in T = 0 protocol mode. 01374 * 01375 * Values: 01376 * - 0 - LSB (bit0) is the first bit that is transmitted following the start 01377 * bit. Further, the first bit received after the start bit is identified as 01378 * bit0. 01379 * - 1 - MSB (bit8, bit7 or bit6) is the first bit that is transmitted following 01380 * the start bit, depending on the setting of C1[M] and C1[PE]. Further, the 01381 * first bit received after the start bit is identified as bit8, bit7, or 01382 * bit6, depending on the setting of C1[M] and C1[PE]. 01383 */ 01384 /*@{*/ 01385 #define BP_UART_S2_MSBF (5U) /*!< Bit position for UART_S2_MSBF. */ 01386 #define BM_UART_S2_MSBF (0x20U) /*!< Bit mask for UART_S2_MSBF. */ 01387 #define BS_UART_S2_MSBF (1U) /*!< Bit field size in bits for UART_S2_MSBF. */ 01388 01389 /*! @brief Read current value of the UART_S2_MSBF field. */ 01390 #define BR_UART_S2_MSBF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF))) 01391 01392 /*! @brief Format value for bitfield UART_S2_MSBF. */ 01393 #define BF_UART_S2_MSBF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_MSBF) & BM_UART_S2_MSBF) 01394 01395 /*! @brief Set the MSBF field to a new value. */ 01396 #define BW_UART_S2_MSBF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_MSBF), v)) 01397 /*@}*/ 01398 01399 /*! 01400 * @name Register UART_S2, field RXEDGIF[6] (W1C) 01401 * 01402 * RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is 01403 * falling if RXINV = 0, and rising if RXINV=1. RXEDGIF is cleared by writing a 1 01404 * to it. See for additional details. RXEDGIF description The active edge is 01405 * detected only in two wire mode and on receiving data coming from the RxD pin. 01406 * 01407 * Values: 01408 * - 0 - No active edge on the receive pin has occurred. 01409 * - 1 - An active edge on the receive pin has occurred. 01410 */ 01411 /*@{*/ 01412 #define BP_UART_S2_RXEDGIF (6U) /*!< Bit position for UART_S2_RXEDGIF. */ 01413 #define BM_UART_S2_RXEDGIF (0x40U) /*!< Bit mask for UART_S2_RXEDGIF. */ 01414 #define BS_UART_S2_RXEDGIF (1U) /*!< Bit field size in bits for UART_S2_RXEDGIF. */ 01415 01416 /*! @brief Read current value of the UART_S2_RXEDGIF field. */ 01417 #define BR_UART_S2_RXEDGIF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF))) 01418 01419 /*! @brief Format value for bitfield UART_S2_RXEDGIF. */ 01420 #define BF_UART_S2_RXEDGIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_RXEDGIF) & BM_UART_S2_RXEDGIF) 01421 01422 /*! @brief Set the RXEDGIF field to a new value. */ 01423 #define BW_UART_S2_RXEDGIF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_RXEDGIF), v)) 01424 /*@}*/ 01425 01426 /*! 01427 * @name Register UART_S2, field LBKDIF[7] (W1C) 01428 * 01429 * LBKDIF is set when LBKDE is set and a LIN break character is detected on the 01430 * receiver input. The LIN break characters are 11 consecutive logic 0s if C1[M] 01431 * = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF is set after receiving the 01432 * last LIN break character. LBKDIF is cleared by writing a 1 to it. 01433 * 01434 * Values: 01435 * - 0 - No LIN break character detected. 01436 * - 1 - LIN break character detected. 01437 */ 01438 /*@{*/ 01439 #define BP_UART_S2_LBKDIF (7U) /*!< Bit position for UART_S2_LBKDIF. */ 01440 #define BM_UART_S2_LBKDIF (0x80U) /*!< Bit mask for UART_S2_LBKDIF. */ 01441 #define BS_UART_S2_LBKDIF (1U) /*!< Bit field size in bits for UART_S2_LBKDIF. */ 01442 01443 /*! @brief Read current value of the UART_S2_LBKDIF field. */ 01444 #define BR_UART_S2_LBKDIF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF))) 01445 01446 /*! @brief Format value for bitfield UART_S2_LBKDIF. */ 01447 #define BF_UART_S2_LBKDIF(v) ((uint8_t)((uint8_t)(v) << BP_UART_S2_LBKDIF) & BM_UART_S2_LBKDIF) 01448 01449 /*! @brief Set the LBKDIF field to a new value. */ 01450 #define BW_UART_S2_LBKDIF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_S2_ADDR(x), BP_UART_S2_LBKDIF), v)) 01451 /*@}*/ 01452 01453 /******************************************************************************* 01454 * HW_UART_C3 - UART Control Register 3 01455 ******************************************************************************/ 01456 01457 /*! 01458 * @brief HW_UART_C3 - UART Control Register 3 (RW) 01459 * 01460 * Reset value: 0x00U 01461 * 01462 * Writing R8 does not have any effect. TXDIR and TXINV can be changed only 01463 * between transmit and receive packets. 01464 */ 01465 typedef union _hw_uart_c3 01466 { 01467 uint8_t U; 01468 struct _hw_uart_c3_bitfields 01469 { 01470 uint8_t PEIE : 1; /*!< [0] Parity Error Interrupt Enable */ 01471 uint8_t FEIE : 1; /*!< [1] Framing Error Interrupt Enable */ 01472 uint8_t NEIE : 1; /*!< [2] Noise Error Interrupt Enable */ 01473 uint8_t ORIE : 1; /*!< [3] Overrun Error Interrupt Enable */ 01474 uint8_t TXINV : 1; /*!< [4] Transmit Data Inversion. */ 01475 uint8_t TXDIR : 1; /*!< [5] Transmitter Pin Data Direction in 01476 * Single-Wire mode */ 01477 uint8_t T8 : 1; /*!< [6] Transmit Bit 8 */ 01478 uint8_t R8 : 1; /*!< [7] Received Bit 8 */ 01479 } B; 01480 } hw_uart_c3_t; 01481 01482 /*! 01483 * @name Constants and macros for entire UART_C3 register 01484 */ 01485 /*@{*/ 01486 #define HW_UART_C3_ADDR(x) ((x) + 0x6U) 01487 01488 #define HW_UART_C3(x) (*(__IO hw_uart_c3_t *) HW_UART_C3_ADDR(x)) 01489 #define HW_UART_C3_RD(x) (ADDRESS_READ(hw_uart_c3_t, HW_UART_C3_ADDR(x))) 01490 #define HW_UART_C3_WR(x, v) (ADDRESS_WRITE(hw_uart_c3_t, HW_UART_C3_ADDR(x), v)) 01491 #define HW_UART_C3_SET(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) | (v))) 01492 #define HW_UART_C3_CLR(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) & ~(v))) 01493 #define HW_UART_C3_TOG(x, v) (HW_UART_C3_WR(x, HW_UART_C3_RD(x) ^ (v))) 01494 /*@}*/ 01495 01496 /* 01497 * Constants & macros for individual UART_C3 bitfields 01498 */ 01499 01500 /*! 01501 * @name Register UART_C3, field PEIE[0] (RW) 01502 * 01503 * Enables the parity error flag, S1[PF], to generate interrupt requests. 01504 * 01505 * Values: 01506 * - 0 - PF interrupt requests are disabled. 01507 * - 1 - PF interrupt requests are enabled. 01508 */ 01509 /*@{*/ 01510 #define BP_UART_C3_PEIE (0U) /*!< Bit position for UART_C3_PEIE. */ 01511 #define BM_UART_C3_PEIE (0x01U) /*!< Bit mask for UART_C3_PEIE. */ 01512 #define BS_UART_C3_PEIE (1U) /*!< Bit field size in bits for UART_C3_PEIE. */ 01513 01514 /*! @brief Read current value of the UART_C3_PEIE field. */ 01515 #define BR_UART_C3_PEIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE))) 01516 01517 /*! @brief Format value for bitfield UART_C3_PEIE. */ 01518 #define BF_UART_C3_PEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_PEIE) & BM_UART_C3_PEIE) 01519 01520 /*! @brief Set the PEIE field to a new value. */ 01521 #define BW_UART_C3_PEIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_PEIE), v)) 01522 /*@}*/ 01523 01524 /*! 01525 * @name Register UART_C3, field FEIE[1] (RW) 01526 * 01527 * Enables the framing error flag, S1[FE], to generate interrupt requests. 01528 * 01529 * Values: 01530 * - 0 - FE interrupt requests are disabled. 01531 * - 1 - FE interrupt requests are enabled. 01532 */ 01533 /*@{*/ 01534 #define BP_UART_C3_FEIE (1U) /*!< Bit position for UART_C3_FEIE. */ 01535 #define BM_UART_C3_FEIE (0x02U) /*!< Bit mask for UART_C3_FEIE. */ 01536 #define BS_UART_C3_FEIE (1U) /*!< Bit field size in bits for UART_C3_FEIE. */ 01537 01538 /*! @brief Read current value of the UART_C3_FEIE field. */ 01539 #define BR_UART_C3_FEIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE))) 01540 01541 /*! @brief Format value for bitfield UART_C3_FEIE. */ 01542 #define BF_UART_C3_FEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_FEIE) & BM_UART_C3_FEIE) 01543 01544 /*! @brief Set the FEIE field to a new value. */ 01545 #define BW_UART_C3_FEIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_FEIE), v)) 01546 /*@}*/ 01547 01548 /*! 01549 * @name Register UART_C3, field NEIE[2] (RW) 01550 * 01551 * Enables the noise flag, S1[NF], to generate interrupt requests. 01552 * 01553 * Values: 01554 * - 0 - NF interrupt requests are disabled. 01555 * - 1 - NF interrupt requests are enabled. 01556 */ 01557 /*@{*/ 01558 #define BP_UART_C3_NEIE (2U) /*!< Bit position for UART_C3_NEIE. */ 01559 #define BM_UART_C3_NEIE (0x04U) /*!< Bit mask for UART_C3_NEIE. */ 01560 #define BS_UART_C3_NEIE (1U) /*!< Bit field size in bits for UART_C3_NEIE. */ 01561 01562 /*! @brief Read current value of the UART_C3_NEIE field. */ 01563 #define BR_UART_C3_NEIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE))) 01564 01565 /*! @brief Format value for bitfield UART_C3_NEIE. */ 01566 #define BF_UART_C3_NEIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_NEIE) & BM_UART_C3_NEIE) 01567 01568 /*! @brief Set the NEIE field to a new value. */ 01569 #define BW_UART_C3_NEIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_NEIE), v)) 01570 /*@}*/ 01571 01572 /*! 01573 * @name Register UART_C3, field ORIE[3] (RW) 01574 * 01575 * Enables the overrun error flag, S1[OR], to generate interrupt requests. 01576 * 01577 * Values: 01578 * - 0 - OR interrupts are disabled. 01579 * - 1 - OR interrupt requests are enabled. 01580 */ 01581 /*@{*/ 01582 #define BP_UART_C3_ORIE (3U) /*!< Bit position for UART_C3_ORIE. */ 01583 #define BM_UART_C3_ORIE (0x08U) /*!< Bit mask for UART_C3_ORIE. */ 01584 #define BS_UART_C3_ORIE (1U) /*!< Bit field size in bits for UART_C3_ORIE. */ 01585 01586 /*! @brief Read current value of the UART_C3_ORIE field. */ 01587 #define BR_UART_C3_ORIE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE))) 01588 01589 /*! @brief Format value for bitfield UART_C3_ORIE. */ 01590 #define BF_UART_C3_ORIE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_ORIE) & BM_UART_C3_ORIE) 01591 01592 /*! @brief Set the ORIE field to a new value. */ 01593 #define BW_UART_C3_ORIE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_ORIE), v)) 01594 /*@}*/ 01595 01596 /*! 01597 * @name Register UART_C3, field TXINV[4] (RW) 01598 * 01599 * Setting this field reverses the polarity of the transmitted data output. In 01600 * NRZ format, a one is represented by a mark and a zero is represented by a space 01601 * for normal polarity, and the opposite for inverted polarity. In IrDA format, 01602 * a zero is represented by short high pulse in the middle of a bit time 01603 * remaining idle low for a one for normal polarity, and a zero is represented by short 01604 * low pulse in the middle of a bit time remaining idle high for a one for 01605 * inverted polarity. This field is automatically set when C7816[INIT] and 01606 * C7816[ISO7816E] are enabled and an initial character is detected in T = 0 protocol mode. 01607 * Setting TXINV inverts all transmitted values, including idle, break, start, and 01608 * stop bits. In loop mode, if TXINV is set, the receiver gets the transmit 01609 * inversion bit when RXINV is disabled. When C7816[ISO7816E] is set/enabled then only 01610 * the transmitted data bits and parity bit are inverted. 01611 * 01612 * Values: 01613 * - 0 - Transmit data is not inverted. 01614 * - 1 - Transmit data is inverted. 01615 */ 01616 /*@{*/ 01617 #define BP_UART_C3_TXINV (4U) /*!< Bit position for UART_C3_TXINV. */ 01618 #define BM_UART_C3_TXINV (0x10U) /*!< Bit mask for UART_C3_TXINV. */ 01619 #define BS_UART_C3_TXINV (1U) /*!< Bit field size in bits for UART_C3_TXINV. */ 01620 01621 /*! @brief Read current value of the UART_C3_TXINV field. */ 01622 #define BR_UART_C3_TXINV(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV))) 01623 01624 /*! @brief Format value for bitfield UART_C3_TXINV. */ 01625 #define BF_UART_C3_TXINV(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXINV) & BM_UART_C3_TXINV) 01626 01627 /*! @brief Set the TXINV field to a new value. */ 01628 #define BW_UART_C3_TXINV(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXINV), v)) 01629 /*@}*/ 01630 01631 /*! 01632 * @name Register UART_C3, field TXDIR[5] (RW) 01633 * 01634 * Determines whether the TXD pin is used as an input or output in the 01635 * single-wire mode of operation. This field is relevant only to the single wire mode. 01636 * When C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 1, this field is 01637 * automatically cleared after the requested block is transmitted. This condition is 01638 * detected when TL7816[TLEN] = 0 and 4 additional characters are transmitted. 01639 * Additionally, if C7816[ISO7816E] is set/enabled and C7816[TTYPE] = 0 and a NACK is 01640 * being transmitted, the hardware automatically overrides this field as needed. In 01641 * this situation, TXDIR does not reflect the temporary state associated with 01642 * the NACK. 01643 * 01644 * Values: 01645 * - 0 - TXD pin is an input in single wire mode. 01646 * - 1 - TXD pin is an output in single wire mode. 01647 */ 01648 /*@{*/ 01649 #define BP_UART_C3_TXDIR (5U) /*!< Bit position for UART_C3_TXDIR. */ 01650 #define BM_UART_C3_TXDIR (0x20U) /*!< Bit mask for UART_C3_TXDIR. */ 01651 #define BS_UART_C3_TXDIR (1U) /*!< Bit field size in bits for UART_C3_TXDIR. */ 01652 01653 /*! @brief Read current value of the UART_C3_TXDIR field. */ 01654 #define BR_UART_C3_TXDIR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR))) 01655 01656 /*! @brief Format value for bitfield UART_C3_TXDIR. */ 01657 #define BF_UART_C3_TXDIR(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_TXDIR) & BM_UART_C3_TXDIR) 01658 01659 /*! @brief Set the TXDIR field to a new value. */ 01660 #define BW_UART_C3_TXDIR(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_TXDIR), v)) 01661 /*@}*/ 01662 01663 /*! 01664 * @name Register UART_C3, field T8[6] (RW) 01665 * 01666 * T8 is the ninth data bit transmitted when the UART is configured for 9-bit 01667 * data format, that is, if C1[M] = 1 or C4[M10] = 1. If the value of T8 is the 01668 * same as in the previous transmission, T8 does not have to be rewritten. The same 01669 * value is transmitted until T8 is rewritten. To correctly transmit the 9th bit, 01670 * write UARTx_C3[T8] to the desired value, then write the UARTx_D register with 01671 * the remaining data. 01672 */ 01673 /*@{*/ 01674 #define BP_UART_C3_T8 (6U) /*!< Bit position for UART_C3_T8. */ 01675 #define BM_UART_C3_T8 (0x40U) /*!< Bit mask for UART_C3_T8. */ 01676 #define BS_UART_C3_T8 (1U) /*!< Bit field size in bits for UART_C3_T8. */ 01677 01678 /*! @brief Read current value of the UART_C3_T8 field. */ 01679 #define BR_UART_C3_T8(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8))) 01680 01681 /*! @brief Format value for bitfield UART_C3_T8. */ 01682 #define BF_UART_C3_T8(v) ((uint8_t)((uint8_t)(v) << BP_UART_C3_T8) & BM_UART_C3_T8) 01683 01684 /*! @brief Set the T8 field to a new value. */ 01685 #define BW_UART_C3_T8(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_T8), v)) 01686 /*@}*/ 01687 01688 /*! 01689 * @name Register UART_C3, field R8[7] (RO) 01690 * 01691 * R8 is the ninth data bit received when the UART is configured for 9-bit data 01692 * format, that is, if C1[M] = 1 or C4[M10] = 1. The R8 value corresponds to the 01693 * current data value in the UARTx_D register. To read the 9th bit, read the 01694 * value of UARTx_C3[R8], then read the UARTx_D register. 01695 */ 01696 /*@{*/ 01697 #define BP_UART_C3_R8 (7U) /*!< Bit position for UART_C3_R8. */ 01698 #define BM_UART_C3_R8 (0x80U) /*!< Bit mask for UART_C3_R8. */ 01699 #define BS_UART_C3_R8 (1U) /*!< Bit field size in bits for UART_C3_R8. */ 01700 01701 /*! @brief Read current value of the UART_C3_R8 field. */ 01702 #define BR_UART_C3_R8(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C3_ADDR(x), BP_UART_C3_R8))) 01703 /*@}*/ 01704 01705 /******************************************************************************* 01706 * HW_UART_D - UART Data Register 01707 ******************************************************************************/ 01708 01709 /*! 01710 * @brief HW_UART_D - UART Data Register (RW) 01711 * 01712 * Reset value: 0x00U 01713 * 01714 * This register is actually two separate registers. Reads return the contents 01715 * of the read-only receive data register and writes go to the write-only transmit 01716 * data register. In 8-bit or 9-bit data format, only UART data register (D) 01717 * needs to be accessed to clear the S1[RDRF] bit (assuming receiver buffer level is 01718 * less than RWFIFO[RXWATER]). The C3 register needs to be read, prior to the D 01719 * register, only if the ninth bit of data needs to be captured. Similarly, the 01720 * ED register needs to be read, prior to the D register, only if the additional 01721 * flag data for the dataword needs to be captured. In the normal 8-bit mode (M 01722 * bit cleared) if the parity is enabled, you get seven data bits and one parity 01723 * bit. That one parity bit is loaded into the D register. So, for the data bits, 01724 * mask off the parity bit from the value you read out of this register. When 01725 * transmitting in 9-bit data format and using 8-bit write instructions, write first 01726 * to transmit bit 8 in UART control register 3 (C3[T8]), then D. A write to 01727 * C3[T8] stores the data in a temporary register. If D register is written first, 01728 * and then the new data on data bus is stored in D, the temporary value written by 01729 * the last write to C3[T8] gets stored in the C3[T8] register. 01730 */ 01731 typedef union _hw_uart_d 01732 { 01733 uint8_t U; 01734 struct _hw_uart_d_bitfields 01735 { 01736 uint8_t RT : 8; /*!< [7:0] */ 01737 } B; 01738 } hw_uart_d_t; 01739 01740 /*! 01741 * @name Constants and macros for entire UART_D register 01742 */ 01743 /*@{*/ 01744 #define HW_UART_D_ADDR(x) ((x) + 0x7U) 01745 01746 #define HW_UART_D(x) (*(__IO hw_uart_d_t *) HW_UART_D_ADDR(x)) 01747 #define HW_UART_D_RD(x) (ADDRESS_READ(hw_uart_d_t, HW_UART_D_ADDR(x))) 01748 #define HW_UART_D_WR(x, v) (ADDRESS_WRITE(hw_uart_d_t, HW_UART_D_ADDR(x), v)) 01749 #define HW_UART_D_SET(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) | (v))) 01750 #define HW_UART_D_CLR(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) & ~(v))) 01751 #define HW_UART_D_TOG(x, v) (HW_UART_D_WR(x, HW_UART_D_RD(x) ^ (v))) 01752 /*@}*/ 01753 01754 /* 01755 * Constants & macros for individual UART_D bitfields 01756 */ 01757 01758 /*! 01759 * @name Register UART_D, field RT[7:0] (RW) 01760 * 01761 * Reads return the contents of the read-only receive data register and writes 01762 * go to the write-only transmit data register. 01763 */ 01764 /*@{*/ 01765 #define BP_UART_D_RT (0U) /*!< Bit position for UART_D_RT. */ 01766 #define BM_UART_D_RT (0xFFU) /*!< Bit mask for UART_D_RT. */ 01767 #define BS_UART_D_RT (8U) /*!< Bit field size in bits for UART_D_RT. */ 01768 01769 /*! @brief Read current value of the UART_D_RT field. */ 01770 #define BR_UART_D_RT(x) (HW_UART_D(x).U) 01771 01772 /*! @brief Format value for bitfield UART_D_RT. */ 01773 #define BF_UART_D_RT(v) ((uint8_t)((uint8_t)(v) << BP_UART_D_RT) & BM_UART_D_RT) 01774 01775 /*! @brief Set the RT field to a new value. */ 01776 #define BW_UART_D_RT(x, v) (HW_UART_D_WR(x, v)) 01777 /*@}*/ 01778 01779 /******************************************************************************* 01780 * HW_UART_MA1 - UART Match Address Registers 1 01781 ******************************************************************************/ 01782 01783 /*! 01784 * @brief HW_UART_MA1 - UART Match Address Registers 1 (RW) 01785 * 01786 * Reset value: 0x00U 01787 * 01788 * The MA1 and MA2 registers are compared to input data addresses when the most 01789 * significant bit is set and the associated C4[MAEN] field is set. If a match 01790 * occurs, the following data is transferred to the data register. If a match 01791 * fails, the following data is discarded. These registers can be read and written at 01792 * anytime. 01793 */ 01794 typedef union _hw_uart_ma1 01795 { 01796 uint8_t U; 01797 struct _hw_uart_ma1_bitfields 01798 { 01799 uint8_t MA : 8; /*!< [7:0] Match Address */ 01800 } B; 01801 } hw_uart_ma1_t; 01802 01803 /*! 01804 * @name Constants and macros for entire UART_MA1 register 01805 */ 01806 /*@{*/ 01807 #define HW_UART_MA1_ADDR(x) ((x) + 0x8U) 01808 01809 #define HW_UART_MA1(x) (*(__IO hw_uart_ma1_t *) HW_UART_MA1_ADDR(x)) 01810 #define HW_UART_MA1_RD(x) (ADDRESS_READ(hw_uart_ma1_t, HW_UART_MA1_ADDR(x))) 01811 #define HW_UART_MA1_WR(x, v) (ADDRESS_WRITE(hw_uart_ma1_t, HW_UART_MA1_ADDR(x), v)) 01812 #define HW_UART_MA1_SET(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) | (v))) 01813 #define HW_UART_MA1_CLR(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) & ~(v))) 01814 #define HW_UART_MA1_TOG(x, v) (HW_UART_MA1_WR(x, HW_UART_MA1_RD(x) ^ (v))) 01815 /*@}*/ 01816 01817 /* 01818 * Constants & macros for individual UART_MA1 bitfields 01819 */ 01820 01821 /*! 01822 * @name Register UART_MA1, field MA[7:0] (RW) 01823 */ 01824 /*@{*/ 01825 #define BP_UART_MA1_MA (0U) /*!< Bit position for UART_MA1_MA. */ 01826 #define BM_UART_MA1_MA (0xFFU) /*!< Bit mask for UART_MA1_MA. */ 01827 #define BS_UART_MA1_MA (8U) /*!< Bit field size in bits for UART_MA1_MA. */ 01828 01829 /*! @brief Read current value of the UART_MA1_MA field. */ 01830 #define BR_UART_MA1_MA(x) (HW_UART_MA1(x).U) 01831 01832 /*! @brief Format value for bitfield UART_MA1_MA. */ 01833 #define BF_UART_MA1_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA1_MA) & BM_UART_MA1_MA) 01834 01835 /*! @brief Set the MA field to a new value. */ 01836 #define BW_UART_MA1_MA(x, v) (HW_UART_MA1_WR(x, v)) 01837 /*@}*/ 01838 01839 /******************************************************************************* 01840 * HW_UART_MA2 - UART Match Address Registers 2 01841 ******************************************************************************/ 01842 01843 /*! 01844 * @brief HW_UART_MA2 - UART Match Address Registers 2 (RW) 01845 * 01846 * Reset value: 0x00U 01847 * 01848 * These registers can be read and written at anytime. The MA1 and MA2 registers 01849 * are compared to input data addresses when the most significant bit is set and 01850 * the associated C4[MAEN] field is set. If a match occurs, the following data 01851 * is transferred to the data register. If a match fails, the following data is 01852 * discarded. 01853 */ 01854 typedef union _hw_uart_ma2 01855 { 01856 uint8_t U; 01857 struct _hw_uart_ma2_bitfields 01858 { 01859 uint8_t MA : 8; /*!< [7:0] Match Address */ 01860 } B; 01861 } hw_uart_ma2_t; 01862 01863 /*! 01864 * @name Constants and macros for entire UART_MA2 register 01865 */ 01866 /*@{*/ 01867 #define HW_UART_MA2_ADDR(x) ((x) + 0x9U) 01868 01869 #define HW_UART_MA2(x) (*(__IO hw_uart_ma2_t *) HW_UART_MA2_ADDR(x)) 01870 #define HW_UART_MA2_RD(x) (ADDRESS_READ(hw_uart_ma2_t, HW_UART_MA2_ADDR(x))) 01871 #define HW_UART_MA2_WR(x, v) (ADDRESS_WRITE(hw_uart_ma2_t, HW_UART_MA2_ADDR(x), v)) 01872 #define HW_UART_MA2_SET(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) | (v))) 01873 #define HW_UART_MA2_CLR(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) & ~(v))) 01874 #define HW_UART_MA2_TOG(x, v) (HW_UART_MA2_WR(x, HW_UART_MA2_RD(x) ^ (v))) 01875 /*@}*/ 01876 01877 /* 01878 * Constants & macros for individual UART_MA2 bitfields 01879 */ 01880 01881 /*! 01882 * @name Register UART_MA2, field MA[7:0] (RW) 01883 */ 01884 /*@{*/ 01885 #define BP_UART_MA2_MA (0U) /*!< Bit position for UART_MA2_MA. */ 01886 #define BM_UART_MA2_MA (0xFFU) /*!< Bit mask for UART_MA2_MA. */ 01887 #define BS_UART_MA2_MA (8U) /*!< Bit field size in bits for UART_MA2_MA. */ 01888 01889 /*! @brief Read current value of the UART_MA2_MA field. */ 01890 #define BR_UART_MA2_MA(x) (HW_UART_MA2(x).U) 01891 01892 /*! @brief Format value for bitfield UART_MA2_MA. */ 01893 #define BF_UART_MA2_MA(v) ((uint8_t)((uint8_t)(v) << BP_UART_MA2_MA) & BM_UART_MA2_MA) 01894 01895 /*! @brief Set the MA field to a new value. */ 01896 #define BW_UART_MA2_MA(x, v) (HW_UART_MA2_WR(x, v)) 01897 /*@}*/ 01898 01899 /******************************************************************************* 01900 * HW_UART_C4 - UART Control Register 4 01901 ******************************************************************************/ 01902 01903 /*! 01904 * @brief HW_UART_C4 - UART Control Register 4 (RW) 01905 * 01906 * Reset value: 0x00U 01907 */ 01908 typedef union _hw_uart_c4 01909 { 01910 uint8_t U; 01911 struct _hw_uart_c4_bitfields 01912 { 01913 uint8_t BRFA : 5; /*!< [4:0] Baud Rate Fine Adjust */ 01914 uint8_t M10 : 1; /*!< [5] 10-bit Mode select */ 01915 uint8_t MAEN2 : 1; /*!< [6] Match Address Mode Enable 2 */ 01916 uint8_t MAEN1 : 1; /*!< [7] Match Address Mode Enable 1 */ 01917 } B; 01918 } hw_uart_c4_t; 01919 01920 /*! 01921 * @name Constants and macros for entire UART_C4 register 01922 */ 01923 /*@{*/ 01924 #define HW_UART_C4_ADDR(x) ((x) + 0xAU) 01925 01926 #define HW_UART_C4(x) (*(__IO hw_uart_c4_t *) HW_UART_C4_ADDR(x)) 01927 #define HW_UART_C4_RD(x) (ADDRESS_READ(hw_uart_c4_t, HW_UART_C4_ADDR(x))) 01928 #define HW_UART_C4_WR(x, v) (ADDRESS_WRITE(hw_uart_c4_t, HW_UART_C4_ADDR(x), v)) 01929 #define HW_UART_C4_SET(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) | (v))) 01930 #define HW_UART_C4_CLR(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) & ~(v))) 01931 #define HW_UART_C4_TOG(x, v) (HW_UART_C4_WR(x, HW_UART_C4_RD(x) ^ (v))) 01932 /*@}*/ 01933 01934 /* 01935 * Constants & macros for individual UART_C4 bitfields 01936 */ 01937 01938 /*! 01939 * @name Register UART_C4, field BRFA[4:0] (RW) 01940 * 01941 * This bit field is used to add more timing resolution to the average baud 01942 * frequency, in increments of 1/32. See Baud rate generation for more information. 01943 */ 01944 /*@{*/ 01945 #define BP_UART_C4_BRFA (0U) /*!< Bit position for UART_C4_BRFA. */ 01946 #define BM_UART_C4_BRFA (0x1FU) /*!< Bit mask for UART_C4_BRFA. */ 01947 #define BS_UART_C4_BRFA (5U) /*!< Bit field size in bits for UART_C4_BRFA. */ 01948 01949 /*! @brief Read current value of the UART_C4_BRFA field. */ 01950 #define BR_UART_C4_BRFA(x) (UNION_READ(hw_uart_c4_t, HW_UART_C4_ADDR(x), U, B.BRFA)) 01951 01952 /*! @brief Format value for bitfield UART_C4_BRFA. */ 01953 #define BF_UART_C4_BRFA(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_BRFA) & BM_UART_C4_BRFA) 01954 01955 /*! @brief Set the BRFA field to a new value. */ 01956 #define BW_UART_C4_BRFA(x, v) (HW_UART_C4_WR(x, (HW_UART_C4_RD(x) & ~BM_UART_C4_BRFA) | BF_UART_C4_BRFA(v))) 01957 /*@}*/ 01958 01959 /*! 01960 * @name Register UART_C4, field M10[5] (RW) 01961 * 01962 * Causes a tenth, non-memory mapped bit to be part of the serial transmission. 01963 * This tenth bit is generated and interpreted as a parity bit. The M10 field 01964 * does not affect the LIN send or detect break behavior. If M10 is set, then both 01965 * C1[M] and C1[PE] must also be set. This field must be cleared when 01966 * C7816[ISO7816E] is set/enabled. See Data format (non ISO-7816) for more information. 01967 * 01968 * Values: 01969 * - 0 - The parity bit is the ninth bit in the serial transmission. 01970 * - 1 - The parity bit is the tenth bit in the serial transmission. 01971 */ 01972 /*@{*/ 01973 #define BP_UART_C4_M10 (5U) /*!< Bit position for UART_C4_M10. */ 01974 #define BM_UART_C4_M10 (0x20U) /*!< Bit mask for UART_C4_M10. */ 01975 #define BS_UART_C4_M10 (1U) /*!< Bit field size in bits for UART_C4_M10. */ 01976 01977 /*! @brief Read current value of the UART_C4_M10 field. */ 01978 #define BR_UART_C4_M10(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10))) 01979 01980 /*! @brief Format value for bitfield UART_C4_M10. */ 01981 #define BF_UART_C4_M10(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_M10) & BM_UART_C4_M10) 01982 01983 /*! @brief Set the M10 field to a new value. */ 01984 #define BW_UART_C4_M10(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_M10), v)) 01985 /*@}*/ 01986 01987 /*! 01988 * @name Register UART_C4, field MAEN2[6] (RW) 01989 * 01990 * See Match address operation for more information. 01991 * 01992 * Values: 01993 * - 0 - All data received is transferred to the data buffer if MAEN1 is cleared. 01994 * - 1 - All data received with the most significant bit cleared, is discarded. 01995 * All data received with the most significant bit set, is compared with 01996 * contents of MA2 register. If no match occurs, the data is discarded. If a 01997 * match occurs, data is transferred to the data buffer. This field must be 01998 * cleared when C7816[ISO7816E] is set/enabled. 01999 */ 02000 /*@{*/ 02001 #define BP_UART_C4_MAEN2 (6U) /*!< Bit position for UART_C4_MAEN2. */ 02002 #define BM_UART_C4_MAEN2 (0x40U) /*!< Bit mask for UART_C4_MAEN2. */ 02003 #define BS_UART_C4_MAEN2 (1U) /*!< Bit field size in bits for UART_C4_MAEN2. */ 02004 02005 /*! @brief Read current value of the UART_C4_MAEN2 field. */ 02006 #define BR_UART_C4_MAEN2(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2))) 02007 02008 /*! @brief Format value for bitfield UART_C4_MAEN2. */ 02009 #define BF_UART_C4_MAEN2(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN2) & BM_UART_C4_MAEN2) 02010 02011 /*! @brief Set the MAEN2 field to a new value. */ 02012 #define BW_UART_C4_MAEN2(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN2), v)) 02013 /*@}*/ 02014 02015 /*! 02016 * @name Register UART_C4, field MAEN1[7] (RW) 02017 * 02018 * See Match address operation for more information. 02019 * 02020 * Values: 02021 * - 0 - All data received is transferred to the data buffer if MAEN2 is cleared. 02022 * - 1 - All data received with the most significant bit cleared, is discarded. 02023 * All data received with the most significant bit set, is compared with 02024 * contents of MA1 register. If no match occurs, the data is discarded. If match 02025 * occurs, data is transferred to the data buffer. This field must be cleared 02026 * when C7816[ISO7816E] is set/enabled. 02027 */ 02028 /*@{*/ 02029 #define BP_UART_C4_MAEN1 (7U) /*!< Bit position for UART_C4_MAEN1. */ 02030 #define BM_UART_C4_MAEN1 (0x80U) /*!< Bit mask for UART_C4_MAEN1. */ 02031 #define BS_UART_C4_MAEN1 (1U) /*!< Bit field size in bits for UART_C4_MAEN1. */ 02032 02033 /*! @brief Read current value of the UART_C4_MAEN1 field. */ 02034 #define BR_UART_C4_MAEN1(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1))) 02035 02036 /*! @brief Format value for bitfield UART_C4_MAEN1. */ 02037 #define BF_UART_C4_MAEN1(v) ((uint8_t)((uint8_t)(v) << BP_UART_C4_MAEN1) & BM_UART_C4_MAEN1) 02038 02039 /*! @brief Set the MAEN1 field to a new value. */ 02040 #define BW_UART_C4_MAEN1(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C4_ADDR(x), BP_UART_C4_MAEN1), v)) 02041 /*@}*/ 02042 02043 /******************************************************************************* 02044 * HW_UART_C5 - UART Control Register 5 02045 ******************************************************************************/ 02046 02047 /*! 02048 * @brief HW_UART_C5 - UART Control Register 5 (RW) 02049 * 02050 * Reset value: 0x00U 02051 */ 02052 typedef union _hw_uart_c5 02053 { 02054 uint8_t U; 02055 struct _hw_uart_c5_bitfields 02056 { 02057 uint8_t RESERVED0 : 3; /*!< [2:0] */ 02058 uint8_t LBKDDMAS : 1; /*!< [3] LIN Break Detect DMA Select Bit */ 02059 uint8_t ILDMAS : 1; /*!< [4] Idle Line DMA Select */ 02060 uint8_t RDMAS : 1; /*!< [5] Receiver Full DMA Select */ 02061 uint8_t TCDMAS : 1; /*!< [6] Transmission Complete DMA Select */ 02062 uint8_t TDMAS : 1; /*!< [7] Transmitter DMA Select */ 02063 } B; 02064 } hw_uart_c5_t; 02065 02066 /*! 02067 * @name Constants and macros for entire UART_C5 register 02068 */ 02069 /*@{*/ 02070 #define HW_UART_C5_ADDR(x) ((x) + 0xBU) 02071 02072 #define HW_UART_C5(x) (*(__IO hw_uart_c5_t *) HW_UART_C5_ADDR(x)) 02073 #define HW_UART_C5_RD(x) (ADDRESS_READ(hw_uart_c5_t, HW_UART_C5_ADDR(x))) 02074 #define HW_UART_C5_WR(x, v) (ADDRESS_WRITE(hw_uart_c5_t, HW_UART_C5_ADDR(x), v)) 02075 #define HW_UART_C5_SET(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) | (v))) 02076 #define HW_UART_C5_CLR(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) & ~(v))) 02077 #define HW_UART_C5_TOG(x, v) (HW_UART_C5_WR(x, HW_UART_C5_RD(x) ^ (v))) 02078 /*@}*/ 02079 02080 /* 02081 * Constants & macros for individual UART_C5 bitfields 02082 */ 02083 02084 /*! 02085 * @name Register UART_C5, field LBKDDMAS[3] (RW) 02086 * 02087 * Configures the LIN break detect flag, S2[LBKDIF], to generate interrupt or 02088 * DMA requests if BDH[LBKDIE] is set. If BDH[LBKDIE] is cleared, and S2[LBKDIF] is 02089 * set, the LBKDIF DMA and LBKDIF interrupt signals are not asserted, regardless 02090 * of the state of LBKDDMAS. 02091 * 02092 * Values: 02093 * - 0 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF interrupt signal is 02094 * asserted to request an interrupt service. 02095 * - 1 - If BDH[LBKDIE] and S2[LBKDIF] are set, the LBKDIF DMA request signal is 02096 * asserted to request a DMA transfer. 02097 */ 02098 /*@{*/ 02099 #define BP_UART_C5_LBKDDMAS (3U) /*!< Bit position for UART_C5_LBKDDMAS. */ 02100 #define BM_UART_C5_LBKDDMAS (0x08U) /*!< Bit mask for UART_C5_LBKDDMAS. */ 02101 #define BS_UART_C5_LBKDDMAS (1U) /*!< Bit field size in bits for UART_C5_LBKDDMAS. */ 02102 02103 /*! @brief Read current value of the UART_C5_LBKDDMAS field. */ 02104 #define BR_UART_C5_LBKDDMAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS))) 02105 02106 /*! @brief Format value for bitfield UART_C5_LBKDDMAS. */ 02107 #define BF_UART_C5_LBKDDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_LBKDDMAS) & BM_UART_C5_LBKDDMAS) 02108 02109 /*! @brief Set the LBKDDMAS field to a new value. */ 02110 #define BW_UART_C5_LBKDDMAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_LBKDDMAS), v)) 02111 /*@}*/ 02112 02113 /*! 02114 * @name Register UART_C5, field ILDMAS[4] (RW) 02115 * 02116 * Configures the idle line flag, S1[IDLE], to generate interrupt or DMA 02117 * requests if C2[ILIE] is set. If C2[ILIE] is cleared, and S1[IDLE] is set, the IDLE 02118 * DMA and IDLE interrupt request signals are not asserted, regardless of the state 02119 * of ILDMAS. 02120 * 02121 * Values: 02122 * - 0 - If C2[ILIE] and S1[IDLE] are set, the IDLE interrupt request signal is 02123 * asserted to request an interrupt service. 02124 * - 1 - If C2[ILIE] and S1[IDLE] are set, the IDLE DMA request signal is 02125 * asserted to request a DMA transfer. 02126 */ 02127 /*@{*/ 02128 #define BP_UART_C5_ILDMAS (4U) /*!< Bit position for UART_C5_ILDMAS. */ 02129 #define BM_UART_C5_ILDMAS (0x10U) /*!< Bit mask for UART_C5_ILDMAS. */ 02130 #define BS_UART_C5_ILDMAS (1U) /*!< Bit field size in bits for UART_C5_ILDMAS. */ 02131 02132 /*! @brief Read current value of the UART_C5_ILDMAS field. */ 02133 #define BR_UART_C5_ILDMAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS))) 02134 02135 /*! @brief Format value for bitfield UART_C5_ILDMAS. */ 02136 #define BF_UART_C5_ILDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_ILDMAS) & BM_UART_C5_ILDMAS) 02137 02138 /*! @brief Set the ILDMAS field to a new value. */ 02139 #define BW_UART_C5_ILDMAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_ILDMAS), v)) 02140 /*@}*/ 02141 02142 /*! 02143 * @name Register UART_C5, field RDMAS[5] (RW) 02144 * 02145 * Configures the receiver data register full flag, S1[RDRF], to generate 02146 * interrupt or DMA requests if C2[RIE] is set. If C2[RIE] is cleared, and S1[RDRF] is 02147 * set, the RDRF DMA and RDFR interrupt request signals are not asserted, 02148 * regardless of the state of RDMAS. 02149 * 02150 * Values: 02151 * - 0 - If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is 02152 * asserted to request an interrupt service. 02153 * - 1 - If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is 02154 * asserted to request a DMA transfer. 02155 */ 02156 /*@{*/ 02157 #define BP_UART_C5_RDMAS (5U) /*!< Bit position for UART_C5_RDMAS. */ 02158 #define BM_UART_C5_RDMAS (0x20U) /*!< Bit mask for UART_C5_RDMAS. */ 02159 #define BS_UART_C5_RDMAS (1U) /*!< Bit field size in bits for UART_C5_RDMAS. */ 02160 02161 /*! @brief Read current value of the UART_C5_RDMAS field. */ 02162 #define BR_UART_C5_RDMAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS))) 02163 02164 /*! @brief Format value for bitfield UART_C5_RDMAS. */ 02165 #define BF_UART_C5_RDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_RDMAS) & BM_UART_C5_RDMAS) 02166 02167 /*! @brief Set the RDMAS field to a new value. */ 02168 #define BW_UART_C5_RDMAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_RDMAS), v)) 02169 /*@}*/ 02170 02171 /*! 02172 * @name Register UART_C5, field TCDMAS[6] (RW) 02173 * 02174 * Configures the transmission complete flag, S1[TC], to generate interrupt or 02175 * DMA requests if C2[TCIE] is set. If C2[TCIE] is cleared, the TC DMA and TC 02176 * interrupt request signals are not asserted when the S1[TC] flag is set, regardless 02177 * of the state of TCDMAS. If C2[TCIE] and TCDMAS are both set, then C2[TIE] 02178 * must be cleared, and D must not be written unless a DMA request is being serviced. 02179 * 02180 * Values: 02181 * - 0 - If C2[TCIE] is set and the S1[TC] flag is set, the TC interrupt request 02182 * signal is asserted to request an interrupt service. 02183 * - 1 - If C2[TCIE] is set and the S1[TC] flag is set, the TC DMA request 02184 * signal is asserted to request a DMA transfer. 02185 */ 02186 /*@{*/ 02187 #define BP_UART_C5_TCDMAS (6U) /*!< Bit position for UART_C5_TCDMAS. */ 02188 #define BM_UART_C5_TCDMAS (0x40U) /*!< Bit mask for UART_C5_TCDMAS. */ 02189 #define BS_UART_C5_TCDMAS (1U) /*!< Bit field size in bits for UART_C5_TCDMAS. */ 02190 02191 /*! @brief Read current value of the UART_C5_TCDMAS field. */ 02192 #define BR_UART_C5_TCDMAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS))) 02193 02194 /*! @brief Format value for bitfield UART_C5_TCDMAS. */ 02195 #define BF_UART_C5_TCDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TCDMAS) & BM_UART_C5_TCDMAS) 02196 02197 /*! @brief Set the TCDMAS field to a new value. */ 02198 #define BW_UART_C5_TCDMAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TCDMAS), v)) 02199 /*@}*/ 02200 02201 /*! 02202 * @name Register UART_C5, field TDMAS[7] (RW) 02203 * 02204 * Configures the transmit data register empty flag, S1[TDRE], to generate 02205 * interrupt or DMA requests if C2[TIE] is set. If C2[TIE] is cleared, TDRE DMA and 02206 * TDRE interrupt request signals are not asserted when the TDRE flag is set, 02207 * regardless of the state of TDMAS. If C2[TIE] and TDMAS are both set, then C2[TCIE] 02208 * must be cleared, and D must not be written unless a DMA request is being 02209 * serviced. 02210 * 02211 * Values: 02212 * - 0 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt 02213 * request signal is asserted to request interrupt service. 02214 * - 1 - If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request 02215 * signal is asserted to request a DMA transfer. 02216 */ 02217 /*@{*/ 02218 #define BP_UART_C5_TDMAS (7U) /*!< Bit position for UART_C5_TDMAS. */ 02219 #define BM_UART_C5_TDMAS (0x80U) /*!< Bit mask for UART_C5_TDMAS. */ 02220 #define BS_UART_C5_TDMAS (1U) /*!< Bit field size in bits for UART_C5_TDMAS. */ 02221 02222 /*! @brief Read current value of the UART_C5_TDMAS field. */ 02223 #define BR_UART_C5_TDMAS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS))) 02224 02225 /*! @brief Format value for bitfield UART_C5_TDMAS. */ 02226 #define BF_UART_C5_TDMAS(v) ((uint8_t)((uint8_t)(v) << BP_UART_C5_TDMAS) & BM_UART_C5_TDMAS) 02227 02228 /*! @brief Set the TDMAS field to a new value. */ 02229 #define BW_UART_C5_TDMAS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C5_ADDR(x), BP_UART_C5_TDMAS), v)) 02230 /*@}*/ 02231 02232 /******************************************************************************* 02233 * HW_UART_ED - UART Extended Data Register 02234 ******************************************************************************/ 02235 02236 /*! 02237 * @brief HW_UART_ED - UART Extended Data Register (RO) 02238 * 02239 * Reset value: 0x00U 02240 * 02241 * This register contains additional information flags that are stored with a 02242 * received dataword. This register may be read at any time but contains valid data 02243 * only if there is a dataword in the receive FIFO. The data contained in this 02244 * register represents additional information regarding the conditions on which a 02245 * dataword was received. The importance of this data varies with the 02246 * application, and in some cases maybe completely optional. These fields automatically 02247 * update to reflect the conditions of the next dataword whenever D is read. If 02248 * S1[NF] and S1[PF] have not been set since the last time the receive buffer was 02249 * empty, the NOISY and PARITYE fields will be zero. 02250 */ 02251 typedef union _hw_uart_ed 02252 { 02253 uint8_t U; 02254 struct _hw_uart_ed_bitfields 02255 { 02256 uint8_t RESERVED0 : 6; /*!< [5:0] */ 02257 uint8_t PARITYE : 1; /*!< [6] */ 02258 uint8_t NOISY : 1; /*!< [7] */ 02259 } B; 02260 } hw_uart_ed_t; 02261 02262 /*! 02263 * @name Constants and macros for entire UART_ED register 02264 */ 02265 /*@{*/ 02266 #define HW_UART_ED_ADDR(x) ((x) + 0xCU) 02267 02268 #define HW_UART_ED(x) (*(__I hw_uart_ed_t *) HW_UART_ED_ADDR(x)) 02269 #define HW_UART_ED_RD(x) (ADDRESS_READ(hw_uart_ed_t, HW_UART_ED_ADDR(x))) 02270 /*@}*/ 02271 02272 /* 02273 * Constants & macros for individual UART_ED bitfields 02274 */ 02275 02276 /*! 02277 * @name Register UART_ED, field PARITYE[6] (RO) 02278 * 02279 * The current received dataword contained in D and C3[R8] was received with a 02280 * parity error. 02281 * 02282 * Values: 02283 * - 0 - The dataword was received without a parity error. 02284 * - 1 - The dataword was received with a parity error. 02285 */ 02286 /*@{*/ 02287 #define BP_UART_ED_PARITYE (6U) /*!< Bit position for UART_ED_PARITYE. */ 02288 #define BM_UART_ED_PARITYE (0x40U) /*!< Bit mask for UART_ED_PARITYE. */ 02289 #define BS_UART_ED_PARITYE (1U) /*!< Bit field size in bits for UART_ED_PARITYE. */ 02290 02291 /*! @brief Read current value of the UART_ED_PARITYE field. */ 02292 #define BR_UART_ED_PARITYE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_ED_ADDR(x), BP_UART_ED_PARITYE))) 02293 /*@}*/ 02294 02295 /*! 02296 * @name Register UART_ED, field NOISY[7] (RO) 02297 * 02298 * The current received dataword contained in D and C3[R8] was received with 02299 * noise. 02300 * 02301 * Values: 02302 * - 0 - The dataword was received without noise. 02303 * - 1 - The data was received with noise. 02304 */ 02305 /*@{*/ 02306 #define BP_UART_ED_NOISY (7U) /*!< Bit position for UART_ED_NOISY. */ 02307 #define BM_UART_ED_NOISY (0x80U) /*!< Bit mask for UART_ED_NOISY. */ 02308 #define BS_UART_ED_NOISY (1U) /*!< Bit field size in bits for UART_ED_NOISY. */ 02309 02310 /*! @brief Read current value of the UART_ED_NOISY field. */ 02311 #define BR_UART_ED_NOISY(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_ED_ADDR(x), BP_UART_ED_NOISY))) 02312 /*@}*/ 02313 02314 /******************************************************************************* 02315 * HW_UART_MODEM - UART Modem Register 02316 ******************************************************************************/ 02317 02318 /*! 02319 * @brief HW_UART_MODEM - UART Modem Register (RW) 02320 * 02321 * Reset value: 0x00U 02322 * 02323 * The MODEM register controls options for setting the modem configuration. 02324 * RXRTSE, TXRTSPOL, TXRTSE, and TXCTSE must all be cleared when C7816[ISO7816EN] is 02325 * enabled. This will cause the RTS to deassert during ISO-7816 wait times. The 02326 * ISO-7816 protocol does not use the RTS and CTS signals. 02327 */ 02328 typedef union _hw_uart_modem 02329 { 02330 uint8_t U; 02331 struct _hw_uart_modem_bitfields 02332 { 02333 uint8_t TXCTSE : 1; /*!< [0] Transmitter clear-to-send enable */ 02334 uint8_t TXRTSE : 1; /*!< [1] Transmitter request-to-send enable */ 02335 uint8_t TXRTSPOL : 1; /*!< [2] Transmitter request-to-send polarity */ 02336 uint8_t RXRTSE : 1; /*!< [3] Receiver request-to-send enable */ 02337 uint8_t RESERVED0 : 4; /*!< [7:4] */ 02338 } B; 02339 } hw_uart_modem_t; 02340 02341 /*! 02342 * @name Constants and macros for entire UART_MODEM register 02343 */ 02344 /*@{*/ 02345 #define HW_UART_MODEM_ADDR(x) ((x) + 0xDU) 02346 02347 #define HW_UART_MODEM(x) (*(__IO hw_uart_modem_t *) HW_UART_MODEM_ADDR(x)) 02348 #define HW_UART_MODEM_RD(x) (ADDRESS_READ(hw_uart_modem_t, HW_UART_MODEM_ADDR(x))) 02349 #define HW_UART_MODEM_WR(x, v) (ADDRESS_WRITE(hw_uart_modem_t, HW_UART_MODEM_ADDR(x), v)) 02350 #define HW_UART_MODEM_SET(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) | (v))) 02351 #define HW_UART_MODEM_CLR(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) & ~(v))) 02352 #define HW_UART_MODEM_TOG(x, v) (HW_UART_MODEM_WR(x, HW_UART_MODEM_RD(x) ^ (v))) 02353 /*@}*/ 02354 02355 /* 02356 * Constants & macros for individual UART_MODEM bitfields 02357 */ 02358 02359 /*! 02360 * @name Register UART_MODEM, field TXCTSE[0] (RW) 02361 * 02362 * TXCTSE controls the operation of the transmitter. TXCTSE can be set 02363 * independently from the state of TXRTSE and RXRTSE. 02364 * 02365 * Values: 02366 * - 0 - CTS has no effect on the transmitter. 02367 * - 1 - Enables clear-to-send operation. The transmitter checks the state of 02368 * CTS each time it is ready to send a character. If CTS is asserted, the 02369 * character is sent. If CTS is deasserted, the signal TXD remains in the mark 02370 * state and transmission is delayed until CTS is asserted. Changes in CTS as a 02371 * character is being sent do not affect its transmission. 02372 */ 02373 /*@{*/ 02374 #define BP_UART_MODEM_TXCTSE (0U) /*!< Bit position for UART_MODEM_TXCTSE. */ 02375 #define BM_UART_MODEM_TXCTSE (0x01U) /*!< Bit mask for UART_MODEM_TXCTSE. */ 02376 #define BS_UART_MODEM_TXCTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXCTSE. */ 02377 02378 /*! @brief Read current value of the UART_MODEM_TXCTSE field. */ 02379 #define BR_UART_MODEM_TXCTSE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE))) 02380 02381 /*! @brief Format value for bitfield UART_MODEM_TXCTSE. */ 02382 #define BF_UART_MODEM_TXCTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXCTSE) & BM_UART_MODEM_TXCTSE) 02383 02384 /*! @brief Set the TXCTSE field to a new value. */ 02385 #define BW_UART_MODEM_TXCTSE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXCTSE), v)) 02386 /*@}*/ 02387 02388 /*! 02389 * @name Register UART_MODEM, field TXRTSE[1] (RW) 02390 * 02391 * Controls RTS before and after a transmission. 02392 * 02393 * Values: 02394 * - 0 - The transmitter has no effect on RTS. 02395 * - 1 - When a character is placed into an empty transmitter data buffer , RTS 02396 * asserts one bit time before the start bit is transmitted. RTS deasserts 02397 * one bit time after all characters in the transmitter data buffer and shift 02398 * register are completely sent, including the last stop bit. (FIFO) (FIFO) 02399 */ 02400 /*@{*/ 02401 #define BP_UART_MODEM_TXRTSE (1U) /*!< Bit position for UART_MODEM_TXRTSE. */ 02402 #define BM_UART_MODEM_TXRTSE (0x02U) /*!< Bit mask for UART_MODEM_TXRTSE. */ 02403 #define BS_UART_MODEM_TXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSE. */ 02404 02405 /*! @brief Read current value of the UART_MODEM_TXRTSE field. */ 02406 #define BR_UART_MODEM_TXRTSE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE))) 02407 02408 /*! @brief Format value for bitfield UART_MODEM_TXRTSE. */ 02409 #define BF_UART_MODEM_TXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSE) & BM_UART_MODEM_TXRTSE) 02410 02411 /*! @brief Set the TXRTSE field to a new value. */ 02412 #define BW_UART_MODEM_TXRTSE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSE), v)) 02413 /*@}*/ 02414 02415 /*! 02416 * @name Register UART_MODEM, field TXRTSPOL[2] (RW) 02417 * 02418 * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the 02419 * polarity of the receiver RTS. RTS will remain negated in the active low state 02420 * unless TXRTSE is set. 02421 * 02422 * Values: 02423 * - 0 - Transmitter RTS is active low. 02424 * - 1 - Transmitter RTS is active high. 02425 */ 02426 /*@{*/ 02427 #define BP_UART_MODEM_TXRTSPOL (2U) /*!< Bit position for UART_MODEM_TXRTSPOL. */ 02428 #define BM_UART_MODEM_TXRTSPOL (0x04U) /*!< Bit mask for UART_MODEM_TXRTSPOL. */ 02429 #define BS_UART_MODEM_TXRTSPOL (1U) /*!< Bit field size in bits for UART_MODEM_TXRTSPOL. */ 02430 02431 /*! @brief Read current value of the UART_MODEM_TXRTSPOL field. */ 02432 #define BR_UART_MODEM_TXRTSPOL(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL))) 02433 02434 /*! @brief Format value for bitfield UART_MODEM_TXRTSPOL. */ 02435 #define BF_UART_MODEM_TXRTSPOL(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_TXRTSPOL) & BM_UART_MODEM_TXRTSPOL) 02436 02437 /*! @brief Set the TXRTSPOL field to a new value. */ 02438 #define BW_UART_MODEM_TXRTSPOL(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_TXRTSPOL), v)) 02439 /*@}*/ 02440 02441 /*! 02442 * @name Register UART_MODEM, field RXRTSE[3] (RW) 02443 * 02444 * Allows the RTS output to control the CTS input of the transmitting device to 02445 * prevent receiver overrun. Do not set both RXRTSE and TXRTSE. 02446 * 02447 * Values: 02448 * - 0 - The receiver has no effect on RTS. 02449 * - 1 - RTS is deasserted if the number of characters in the receiver data 02450 * register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted 02451 * when the number of characters in the receiver data register (FIFO) is less 02452 * than RWFIFO[RXWATER]. 02453 */ 02454 /*@{*/ 02455 #define BP_UART_MODEM_RXRTSE (3U) /*!< Bit position for UART_MODEM_RXRTSE. */ 02456 #define BM_UART_MODEM_RXRTSE (0x08U) /*!< Bit mask for UART_MODEM_RXRTSE. */ 02457 #define BS_UART_MODEM_RXRTSE (1U) /*!< Bit field size in bits for UART_MODEM_RXRTSE. */ 02458 02459 /*! @brief Read current value of the UART_MODEM_RXRTSE field. */ 02460 #define BR_UART_MODEM_RXRTSE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE))) 02461 02462 /*! @brief Format value for bitfield UART_MODEM_RXRTSE. */ 02463 #define BF_UART_MODEM_RXRTSE(v) ((uint8_t)((uint8_t)(v) << BP_UART_MODEM_RXRTSE) & BM_UART_MODEM_RXRTSE) 02464 02465 /*! @brief Set the RXRTSE field to a new value. */ 02466 #define BW_UART_MODEM_RXRTSE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_MODEM_ADDR(x), BP_UART_MODEM_RXRTSE), v)) 02467 /*@}*/ 02468 02469 /******************************************************************************* 02470 * HW_UART_IR - UART Infrared Register 02471 ******************************************************************************/ 02472 02473 /*! 02474 * @brief HW_UART_IR - UART Infrared Register (RW) 02475 * 02476 * Reset value: 0x00U 02477 * 02478 * The IR register controls options for setting the infrared configuration. 02479 */ 02480 typedef union _hw_uart_ir 02481 { 02482 uint8_t U; 02483 struct _hw_uart_ir_bitfields 02484 { 02485 uint8_t TNP : 2; /*!< [1:0] Transmitter narrow pulse */ 02486 uint8_t IREN : 1; /*!< [2] Infrared enable */ 02487 uint8_t RESERVED0 : 5; /*!< [7:3] */ 02488 } B; 02489 } hw_uart_ir_t; 02490 02491 /*! 02492 * @name Constants and macros for entire UART_IR register 02493 */ 02494 /*@{*/ 02495 #define HW_UART_IR_ADDR(x) ((x) + 0xEU) 02496 02497 #define HW_UART_IR(x) (*(__IO hw_uart_ir_t *) HW_UART_IR_ADDR(x)) 02498 #define HW_UART_IR_RD(x) (ADDRESS_READ(hw_uart_ir_t, HW_UART_IR_ADDR(x))) 02499 #define HW_UART_IR_WR(x, v) (ADDRESS_WRITE(hw_uart_ir_t, HW_UART_IR_ADDR(x), v)) 02500 #define HW_UART_IR_SET(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) | (v))) 02501 #define HW_UART_IR_CLR(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) & ~(v))) 02502 #define HW_UART_IR_TOG(x, v) (HW_UART_IR_WR(x, HW_UART_IR_RD(x) ^ (v))) 02503 /*@}*/ 02504 02505 /* 02506 * Constants & macros for individual UART_IR bitfields 02507 */ 02508 02509 /*! 02510 * @name Register UART_IR, field TNP[1:0] (RW) 02511 * 02512 * Enables whether the UART transmits a 1/16, 3/16, 1/32, or 1/4 narrow pulse. 02513 * 02514 * Values: 02515 * - 00 - 3/16. 02516 * - 01 - 1/16. 02517 * - 10 - 1/32. 02518 * - 11 - 1/4. 02519 */ 02520 /*@{*/ 02521 #define BP_UART_IR_TNP (0U) /*!< Bit position for UART_IR_TNP. */ 02522 #define BM_UART_IR_TNP (0x03U) /*!< Bit mask for UART_IR_TNP. */ 02523 #define BS_UART_IR_TNP (2U) /*!< Bit field size in bits for UART_IR_TNP. */ 02524 02525 /*! @brief Read current value of the UART_IR_TNP field. */ 02526 #define BR_UART_IR_TNP(x) (UNION_READ(hw_uart_ir_t, HW_UART_IR_ADDR(x), U, B.TNP)) 02527 02528 /*! @brief Format value for bitfield UART_IR_TNP. */ 02529 #define BF_UART_IR_TNP(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_TNP) & BM_UART_IR_TNP) 02530 02531 /*! @brief Set the TNP field to a new value. */ 02532 #define BW_UART_IR_TNP(x, v) (HW_UART_IR_WR(x, (HW_UART_IR_RD(x) & ~BM_UART_IR_TNP) | BF_UART_IR_TNP(v))) 02533 /*@}*/ 02534 02535 /*! 02536 * @name Register UART_IR, field IREN[2] (RW) 02537 * 02538 * Enables/disables the infrared modulation/demodulation. 02539 * 02540 * Values: 02541 * - 0 - IR disabled. 02542 * - 1 - IR enabled. 02543 */ 02544 /*@{*/ 02545 #define BP_UART_IR_IREN (2U) /*!< Bit position for UART_IR_IREN. */ 02546 #define BM_UART_IR_IREN (0x04U) /*!< Bit mask for UART_IR_IREN. */ 02547 #define BS_UART_IR_IREN (1U) /*!< Bit field size in bits for UART_IR_IREN. */ 02548 02549 /*! @brief Read current value of the UART_IR_IREN field. */ 02550 #define BR_UART_IR_IREN(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN))) 02551 02552 /*! @brief Format value for bitfield UART_IR_IREN. */ 02553 #define BF_UART_IR_IREN(v) ((uint8_t)((uint8_t)(v) << BP_UART_IR_IREN) & BM_UART_IR_IREN) 02554 02555 /*! @brief Set the IREN field to a new value. */ 02556 #define BW_UART_IR_IREN(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IR_ADDR(x), BP_UART_IR_IREN), v)) 02557 /*@}*/ 02558 02559 /******************************************************************************* 02560 * HW_UART_PFIFO - UART FIFO Parameters 02561 ******************************************************************************/ 02562 02563 /*! 02564 * @brief HW_UART_PFIFO - UART FIFO Parameters (RW) 02565 * 02566 * Reset value: 0x00U 02567 * 02568 * This register provides the ability for the programmer to turn on and off FIFO 02569 * functionality. It also provides the size of the FIFO that has been 02570 * implemented. This register may be read at any time. This register must be written only 02571 * when C2[RE] and C2[TE] are cleared/not set and when the data buffer/FIFO is 02572 * empty. 02573 */ 02574 typedef union _hw_uart_pfifo 02575 { 02576 uint8_t U; 02577 struct _hw_uart_pfifo_bitfields 02578 { 02579 uint8_t RXFIFOSIZE : 3; /*!< [2:0] Receive FIFO. Buffer Depth */ 02580 uint8_t RXFE : 1; /*!< [3] Receive FIFO Enable */ 02581 uint8_t TXFIFOSIZE : 3; /*!< [6:4] Transmit FIFO. Buffer Depth */ 02582 uint8_t TXFE : 1; /*!< [7] Transmit FIFO Enable */ 02583 } B; 02584 } hw_uart_pfifo_t; 02585 02586 /*! 02587 * @name Constants and macros for entire UART_PFIFO register 02588 */ 02589 /*@{*/ 02590 #define HW_UART_PFIFO_ADDR(x) ((x) + 0x10U) 02591 02592 #define HW_UART_PFIFO(x) (*(__IO hw_uart_pfifo_t *) HW_UART_PFIFO_ADDR(x)) 02593 #define HW_UART_PFIFO_RD(x) (ADDRESS_READ(hw_uart_pfifo_t, HW_UART_PFIFO_ADDR(x))) 02594 #define HW_UART_PFIFO_WR(x, v) (ADDRESS_WRITE(hw_uart_pfifo_t, HW_UART_PFIFO_ADDR(x), v)) 02595 #define HW_UART_PFIFO_SET(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) | (v))) 02596 #define HW_UART_PFIFO_CLR(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) & ~(v))) 02597 #define HW_UART_PFIFO_TOG(x, v) (HW_UART_PFIFO_WR(x, HW_UART_PFIFO_RD(x) ^ (v))) 02598 /*@}*/ 02599 02600 /* 02601 * Constants & macros for individual UART_PFIFO bitfields 02602 */ 02603 02604 /*! 02605 * @name Register UART_PFIFO, field RXFIFOSIZE[2:0] (RO) 02606 * 02607 * The maximum number of receive datawords that can be stored in the receive 02608 * buffer before an overrun occurs. This field is read only. 02609 * 02610 * Values: 02611 * - 000 - Receive FIFO/Buffer depth = 1 dataword. 02612 * - 001 - Receive FIFO/Buffer depth = 4 datawords. 02613 * - 010 - Receive FIFO/Buffer depth = 8 datawords. 02614 * - 011 - Receive FIFO/Buffer depth = 16 datawords. 02615 * - 100 - Receive FIFO/Buffer depth = 32 datawords. 02616 * - 101 - Receive FIFO/Buffer depth = 64 datawords. 02617 * - 110 - Receive FIFO/Buffer depth = 128 datawords. 02618 * - 111 - Reserved. 02619 */ 02620 /*@{*/ 02621 #define BP_UART_PFIFO_RXFIFOSIZE (0U) /*!< Bit position for UART_PFIFO_RXFIFOSIZE. */ 02622 #define BM_UART_PFIFO_RXFIFOSIZE (0x07U) /*!< Bit mask for UART_PFIFO_RXFIFOSIZE. */ 02623 #define BS_UART_PFIFO_RXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_RXFIFOSIZE. */ 02624 02625 /*! @brief Read current value of the UART_PFIFO_RXFIFOSIZE field. */ 02626 #define BR_UART_PFIFO_RXFIFOSIZE(x) (UNION_READ(hw_uart_pfifo_t, HW_UART_PFIFO_ADDR(x), U, B.RXFIFOSIZE)) 02627 /*@}*/ 02628 02629 /*! 02630 * @name Register UART_PFIFO, field RXFE[3] (RW) 02631 * 02632 * When this field is set, the built in FIFO structure for the receive buffer is 02633 * enabled. The size of the FIFO structure is indicated by the RXFIFOSIZE field. 02634 * If this field is not set, the receive buffer operates as a FIFO of depth one 02635 * dataword regardless of the value in RXFIFOSIZE. Both C2[TE] and C2[RE] must be 02636 * cleared prior to changing this field. Additionally, TXFLUSH and RXFLUSH 02637 * commands must be issued immediately after changing this field. 02638 * 02639 * Values: 02640 * - 0 - Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 02641 * - 1 - Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 02642 */ 02643 /*@{*/ 02644 #define BP_UART_PFIFO_RXFE (3U) /*!< Bit position for UART_PFIFO_RXFE. */ 02645 #define BM_UART_PFIFO_RXFE (0x08U) /*!< Bit mask for UART_PFIFO_RXFE. */ 02646 #define BS_UART_PFIFO_RXFE (1U) /*!< Bit field size in bits for UART_PFIFO_RXFE. */ 02647 02648 /*! @brief Read current value of the UART_PFIFO_RXFE field. */ 02649 #define BR_UART_PFIFO_RXFE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE))) 02650 02651 /*! @brief Format value for bitfield UART_PFIFO_RXFE. */ 02652 #define BF_UART_PFIFO_RXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_RXFE) & BM_UART_PFIFO_RXFE) 02653 02654 /*! @brief Set the RXFE field to a new value. */ 02655 #define BW_UART_PFIFO_RXFE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_RXFE), v)) 02656 /*@}*/ 02657 02658 /*! 02659 * @name Register UART_PFIFO, field TXFIFOSIZE[6:4] (RO) 02660 * 02661 * The maximum number of transmit datawords that can be stored in the transmit 02662 * buffer. This field is read only. 02663 * 02664 * Values: 02665 * - 000 - Transmit FIFO/Buffer depth = 1 dataword. 02666 * - 001 - Transmit FIFO/Buffer depth = 4 datawords. 02667 * - 010 - Transmit FIFO/Buffer depth = 8 datawords. 02668 * - 011 - Transmit FIFO/Buffer depth = 16 datawords. 02669 * - 100 - Transmit FIFO/Buffer depth = 32 datawords. 02670 * - 101 - Transmit FIFO/Buffer depth = 64 datawords. 02671 * - 110 - Transmit FIFO/Buffer depth = 128 datawords. 02672 * - 111 - Reserved. 02673 */ 02674 /*@{*/ 02675 #define BP_UART_PFIFO_TXFIFOSIZE (4U) /*!< Bit position for UART_PFIFO_TXFIFOSIZE. */ 02676 #define BM_UART_PFIFO_TXFIFOSIZE (0x70U) /*!< Bit mask for UART_PFIFO_TXFIFOSIZE. */ 02677 #define BS_UART_PFIFO_TXFIFOSIZE (3U) /*!< Bit field size in bits for UART_PFIFO_TXFIFOSIZE. */ 02678 02679 /*! @brief Read current value of the UART_PFIFO_TXFIFOSIZE field. */ 02680 #define BR_UART_PFIFO_TXFIFOSIZE(x) (UNION_READ(hw_uart_pfifo_t, HW_UART_PFIFO_ADDR(x), U, B.TXFIFOSIZE)) 02681 /*@}*/ 02682 02683 /*! 02684 * @name Register UART_PFIFO, field TXFE[7] (RW) 02685 * 02686 * When this field is set, the built in FIFO structure for the transmit buffer 02687 * is enabled. The size of the FIFO structure is indicated by TXFIFOSIZE. If this 02688 * field is not set, the transmit buffer operates as a FIFO of depth one dataword 02689 * regardless of the value in TXFIFOSIZE. Both C2[TE] and C2[RE] must be cleared 02690 * prior to changing this field. Additionally, TXFLUSH and RXFLUSH commands must 02691 * be issued immediately after changing this field. 02692 * 02693 * Values: 02694 * - 0 - Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 02695 * - 1 - Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 02696 */ 02697 /*@{*/ 02698 #define BP_UART_PFIFO_TXFE (7U) /*!< Bit position for UART_PFIFO_TXFE. */ 02699 #define BM_UART_PFIFO_TXFE (0x80U) /*!< Bit mask for UART_PFIFO_TXFE. */ 02700 #define BS_UART_PFIFO_TXFE (1U) /*!< Bit field size in bits for UART_PFIFO_TXFE. */ 02701 02702 /*! @brief Read current value of the UART_PFIFO_TXFE field. */ 02703 #define BR_UART_PFIFO_TXFE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE))) 02704 02705 /*! @brief Format value for bitfield UART_PFIFO_TXFE. */ 02706 #define BF_UART_PFIFO_TXFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_PFIFO_TXFE) & BM_UART_PFIFO_TXFE) 02707 02708 /*! @brief Set the TXFE field to a new value. */ 02709 #define BW_UART_PFIFO_TXFE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_PFIFO_ADDR(x), BP_UART_PFIFO_TXFE), v)) 02710 /*@}*/ 02711 02712 /******************************************************************************* 02713 * HW_UART_CFIFO - UART FIFO Control Register 02714 ******************************************************************************/ 02715 02716 /*! 02717 * @brief HW_UART_CFIFO - UART FIFO Control Register (RW) 02718 * 02719 * Reset value: 0x00U 02720 * 02721 * This register provides the ability to program various control fields for FIFO 02722 * operation. This register may be read or written at any time. Note that 02723 * writing to TXFLUSH and RXFLUSH may result in data loss and requires careful action 02724 * to prevent unintended/unpredictable behavior. Therefore, it is recommended that 02725 * TE and RE be cleared prior to flushing the corresponding FIFO. 02726 */ 02727 typedef union _hw_uart_cfifo 02728 { 02729 uint8_t U; 02730 struct _hw_uart_cfifo_bitfields 02731 { 02732 uint8_t RXUFE : 1; /*!< [0] Receive FIFO Underflow Interrupt Enable */ 02733 uint8_t TXOFE : 1; /*!< [1] Transmit FIFO Overflow Interrupt Enable */ 02734 uint8_t RXOFE : 1; /*!< [2] Receive FIFO Overflow Interrupt Enable */ 02735 uint8_t RESERVED0 : 3; /*!< [5:3] */ 02736 uint8_t RXFLUSH : 1; /*!< [6] Receive FIFO/Buffer Flush */ 02737 uint8_t TXFLUSH : 1; /*!< [7] Transmit FIFO/Buffer Flush */ 02738 } B; 02739 } hw_uart_cfifo_t; 02740 02741 /*! 02742 * @name Constants and macros for entire UART_CFIFO register 02743 */ 02744 /*@{*/ 02745 #define HW_UART_CFIFO_ADDR(x) ((x) + 0x11U) 02746 02747 #define HW_UART_CFIFO(x) (*(__IO hw_uart_cfifo_t *) HW_UART_CFIFO_ADDR(x)) 02748 #define HW_UART_CFIFO_RD(x) (ADDRESS_READ(hw_uart_cfifo_t, HW_UART_CFIFO_ADDR(x))) 02749 #define HW_UART_CFIFO_WR(x, v) (ADDRESS_WRITE(hw_uart_cfifo_t, HW_UART_CFIFO_ADDR(x), v)) 02750 #define HW_UART_CFIFO_SET(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) | (v))) 02751 #define HW_UART_CFIFO_CLR(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) & ~(v))) 02752 #define HW_UART_CFIFO_TOG(x, v) (HW_UART_CFIFO_WR(x, HW_UART_CFIFO_RD(x) ^ (v))) 02753 /*@}*/ 02754 02755 /* 02756 * Constants & macros for individual UART_CFIFO bitfields 02757 */ 02758 02759 /*! 02760 * @name Register UART_CFIFO, field RXUFE[0] (RW) 02761 * 02762 * When this field is set, the RXUF flag generates an interrupt to the host. 02763 * 02764 * Values: 02765 * - 0 - RXUF flag does not generate an interrupt to the host. 02766 * - 1 - RXUF flag generates an interrupt to the host. 02767 */ 02768 /*@{*/ 02769 #define BP_UART_CFIFO_RXUFE (0U) /*!< Bit position for UART_CFIFO_RXUFE. */ 02770 #define BM_UART_CFIFO_RXUFE (0x01U) /*!< Bit mask for UART_CFIFO_RXUFE. */ 02771 #define BS_UART_CFIFO_RXUFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXUFE. */ 02772 02773 /*! @brief Read current value of the UART_CFIFO_RXUFE field. */ 02774 #define BR_UART_CFIFO_RXUFE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE))) 02775 02776 /*! @brief Format value for bitfield UART_CFIFO_RXUFE. */ 02777 #define BF_UART_CFIFO_RXUFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXUFE) & BM_UART_CFIFO_RXUFE) 02778 02779 /*! @brief Set the RXUFE field to a new value. */ 02780 #define BW_UART_CFIFO_RXUFE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXUFE), v)) 02781 /*@}*/ 02782 02783 /*! 02784 * @name Register UART_CFIFO, field TXOFE[1] (RW) 02785 * 02786 * When this field is set, the TXOF flag generates an interrupt to the host. 02787 * 02788 * Values: 02789 * - 0 - TXOF flag does not generate an interrupt to the host. 02790 * - 1 - TXOF flag generates an interrupt to the host. 02791 */ 02792 /*@{*/ 02793 #define BP_UART_CFIFO_TXOFE (1U) /*!< Bit position for UART_CFIFO_TXOFE. */ 02794 #define BM_UART_CFIFO_TXOFE (0x02U) /*!< Bit mask for UART_CFIFO_TXOFE. */ 02795 #define BS_UART_CFIFO_TXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_TXOFE. */ 02796 02797 /*! @brief Read current value of the UART_CFIFO_TXOFE field. */ 02798 #define BR_UART_CFIFO_TXOFE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE))) 02799 02800 /*! @brief Format value for bitfield UART_CFIFO_TXOFE. */ 02801 #define BF_UART_CFIFO_TXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXOFE) & BM_UART_CFIFO_TXOFE) 02802 02803 /*! @brief Set the TXOFE field to a new value. */ 02804 #define BW_UART_CFIFO_TXOFE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXOFE), v)) 02805 /*@}*/ 02806 02807 /*! 02808 * @name Register UART_CFIFO, field RXOFE[2] (RW) 02809 * 02810 * When this field is set, the RXOF flag generates an interrupt to the host. 02811 * 02812 * Values: 02813 * - 0 - RXOF flag does not generate an interrupt to the host. 02814 * - 1 - RXOF flag generates an interrupt to the host. 02815 */ 02816 /*@{*/ 02817 #define BP_UART_CFIFO_RXOFE (2U) /*!< Bit position for UART_CFIFO_RXOFE. */ 02818 #define BM_UART_CFIFO_RXOFE (0x04U) /*!< Bit mask for UART_CFIFO_RXOFE. */ 02819 #define BS_UART_CFIFO_RXOFE (1U) /*!< Bit field size in bits for UART_CFIFO_RXOFE. */ 02820 02821 /*! @brief Read current value of the UART_CFIFO_RXOFE field. */ 02822 #define BR_UART_CFIFO_RXOFE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE))) 02823 02824 /*! @brief Format value for bitfield UART_CFIFO_RXOFE. */ 02825 #define BF_UART_CFIFO_RXOFE(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXOFE) & BM_UART_CFIFO_RXOFE) 02826 02827 /*! @brief Set the RXOFE field to a new value. */ 02828 #define BW_UART_CFIFO_RXOFE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXOFE), v)) 02829 /*@}*/ 02830 02831 /*! 02832 * @name Register UART_CFIFO, field RXFLUSH[6] (WORZ) 02833 * 02834 * Writing to this field causes all data that is stored in the receive 02835 * FIFO/buffer to be flushed. This does not affect data that is in the receive shift 02836 * register. 02837 * 02838 * Values: 02839 * - 0 - No flush operation occurs. 02840 * - 1 - All data in the receive FIFO/buffer is cleared out. 02841 */ 02842 /*@{*/ 02843 #define BP_UART_CFIFO_RXFLUSH (6U) /*!< Bit position for UART_CFIFO_RXFLUSH. */ 02844 #define BM_UART_CFIFO_RXFLUSH (0x40U) /*!< Bit mask for UART_CFIFO_RXFLUSH. */ 02845 #define BS_UART_CFIFO_RXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_RXFLUSH. */ 02846 02847 /*! @brief Format value for bitfield UART_CFIFO_RXFLUSH. */ 02848 #define BF_UART_CFIFO_RXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_RXFLUSH) & BM_UART_CFIFO_RXFLUSH) 02849 02850 /*! @brief Set the RXFLUSH field to a new value. */ 02851 #define BW_UART_CFIFO_RXFLUSH(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_RXFLUSH), v)) 02852 /*@}*/ 02853 02854 /*! 02855 * @name Register UART_CFIFO, field TXFLUSH[7] (WORZ) 02856 * 02857 * Writing to this field causes all data that is stored in the transmit 02858 * FIFO/buffer to be flushed. This does not affect data that is in the transmit shift 02859 * register. 02860 * 02861 * Values: 02862 * - 0 - No flush operation occurs. 02863 * - 1 - All data in the transmit FIFO/Buffer is cleared out. 02864 */ 02865 /*@{*/ 02866 #define BP_UART_CFIFO_TXFLUSH (7U) /*!< Bit position for UART_CFIFO_TXFLUSH. */ 02867 #define BM_UART_CFIFO_TXFLUSH (0x80U) /*!< Bit mask for UART_CFIFO_TXFLUSH. */ 02868 #define BS_UART_CFIFO_TXFLUSH (1U) /*!< Bit field size in bits for UART_CFIFO_TXFLUSH. */ 02869 02870 /*! @brief Format value for bitfield UART_CFIFO_TXFLUSH. */ 02871 #define BF_UART_CFIFO_TXFLUSH(v) ((uint8_t)((uint8_t)(v) << BP_UART_CFIFO_TXFLUSH) & BM_UART_CFIFO_TXFLUSH) 02872 02873 /*! @brief Set the TXFLUSH field to a new value. */ 02874 #define BW_UART_CFIFO_TXFLUSH(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_CFIFO_ADDR(x), BP_UART_CFIFO_TXFLUSH), v)) 02875 /*@}*/ 02876 02877 /******************************************************************************* 02878 * HW_UART_SFIFO - UART FIFO Status Register 02879 ******************************************************************************/ 02880 02881 /*! 02882 * @brief HW_UART_SFIFO - UART FIFO Status Register (RW) 02883 * 02884 * Reset value: 0xC0U 02885 * 02886 * This register provides status information regarding the transmit and receiver 02887 * buffers/FIFOs, including interrupt information. This register may be written 02888 * to or read at any time. 02889 */ 02890 typedef union _hw_uart_sfifo 02891 { 02892 uint8_t U; 02893 struct _hw_uart_sfifo_bitfields 02894 { 02895 uint8_t RXUF : 1; /*!< [0] Receiver Buffer Underflow Flag */ 02896 uint8_t TXOF : 1; /*!< [1] Transmitter Buffer Overflow Flag */ 02897 uint8_t RXOF : 1; /*!< [2] Receiver Buffer Overflow Flag */ 02898 uint8_t RESERVED0 : 3; /*!< [5:3] */ 02899 uint8_t RXEMPT : 1; /*!< [6] Receive Buffer/FIFO Empty */ 02900 uint8_t TXEMPT : 1; /*!< [7] Transmit Buffer/FIFO Empty */ 02901 } B; 02902 } hw_uart_sfifo_t; 02903 02904 /*! 02905 * @name Constants and macros for entire UART_SFIFO register 02906 */ 02907 /*@{*/ 02908 #define HW_UART_SFIFO_ADDR(x) ((x) + 0x12U) 02909 02910 #define HW_UART_SFIFO(x) (*(__IO hw_uart_sfifo_t *) HW_UART_SFIFO_ADDR(x)) 02911 #define HW_UART_SFIFO_RD(x) (ADDRESS_READ(hw_uart_sfifo_t, HW_UART_SFIFO_ADDR(x))) 02912 #define HW_UART_SFIFO_WR(x, v) (ADDRESS_WRITE(hw_uart_sfifo_t, HW_UART_SFIFO_ADDR(x), v)) 02913 #define HW_UART_SFIFO_SET(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) | (v))) 02914 #define HW_UART_SFIFO_CLR(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) & ~(v))) 02915 #define HW_UART_SFIFO_TOG(x, v) (HW_UART_SFIFO_WR(x, HW_UART_SFIFO_RD(x) ^ (v))) 02916 /*@}*/ 02917 02918 /* 02919 * Constants & macros for individual UART_SFIFO bitfields 02920 */ 02921 02922 /*! 02923 * @name Register UART_SFIFO, field RXUF[0] (W1C) 02924 * 02925 * Indicates that more data has been read from the receive buffer than was 02926 * present. This field will assert regardless of the value of CFIFO[RXUFE]. However, 02927 * an interrupt will be issued to the host only if CFIFO[RXUFE] is set. This flag 02928 * is cleared by writing a 1. 02929 * 02930 * Values: 02931 * - 0 - No receive buffer underflow has occurred since the last time the flag 02932 * was cleared. 02933 * - 1 - At least one receive buffer underflow has occurred since the last time 02934 * the flag was cleared. 02935 */ 02936 /*@{*/ 02937 #define BP_UART_SFIFO_RXUF (0U) /*!< Bit position for UART_SFIFO_RXUF. */ 02938 #define BM_UART_SFIFO_RXUF (0x01U) /*!< Bit mask for UART_SFIFO_RXUF. */ 02939 #define BS_UART_SFIFO_RXUF (1U) /*!< Bit field size in bits for UART_SFIFO_RXUF. */ 02940 02941 /*! @brief Read current value of the UART_SFIFO_RXUF field. */ 02942 #define BR_UART_SFIFO_RXUF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF))) 02943 02944 /*! @brief Format value for bitfield UART_SFIFO_RXUF. */ 02945 #define BF_UART_SFIFO_RXUF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXUF) & BM_UART_SFIFO_RXUF) 02946 02947 /*! @brief Set the RXUF field to a new value. */ 02948 #define BW_UART_SFIFO_RXUF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXUF), v)) 02949 /*@}*/ 02950 02951 /*! 02952 * @name Register UART_SFIFO, field TXOF[1] (W1C) 02953 * 02954 * Indicates that more data has been written to the transmit buffer than it can 02955 * hold. This field will assert regardless of the value of CFIFO[TXOFE]. However, 02956 * an interrupt will be issued to the host only if CFIFO[TXOFE] is set. This 02957 * flag is cleared by writing a 1. 02958 * 02959 * Values: 02960 * - 0 - No transmit buffer overflow has occurred since the last time the flag 02961 * was cleared. 02962 * - 1 - At least one transmit buffer overflow has occurred since the last time 02963 * the flag was cleared. 02964 */ 02965 /*@{*/ 02966 #define BP_UART_SFIFO_TXOF (1U) /*!< Bit position for UART_SFIFO_TXOF. */ 02967 #define BM_UART_SFIFO_TXOF (0x02U) /*!< Bit mask for UART_SFIFO_TXOF. */ 02968 #define BS_UART_SFIFO_TXOF (1U) /*!< Bit field size in bits for UART_SFIFO_TXOF. */ 02969 02970 /*! @brief Read current value of the UART_SFIFO_TXOF field. */ 02971 #define BR_UART_SFIFO_TXOF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF))) 02972 02973 /*! @brief Format value for bitfield UART_SFIFO_TXOF. */ 02974 #define BF_UART_SFIFO_TXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_TXOF) & BM_UART_SFIFO_TXOF) 02975 02976 /*! @brief Set the TXOF field to a new value. */ 02977 #define BW_UART_SFIFO_TXOF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXOF), v)) 02978 /*@}*/ 02979 02980 /*! 02981 * @name Register UART_SFIFO, field RXOF[2] (W1C) 02982 * 02983 * Indicates that more data has been written to the receive buffer than it can 02984 * hold. This field will assert regardless of the value of CFIFO[RXOFE]. However, 02985 * an interrupt will be issued to the host only if CFIFO[RXOFE] is set. This flag 02986 * is cleared by writing a 1. 02987 * 02988 * Values: 02989 * - 0 - No receive buffer overflow has occurred since the last time the flag 02990 * was cleared. 02991 * - 1 - At least one receive buffer overflow has occurred since the last time 02992 * the flag was cleared. 02993 */ 02994 /*@{*/ 02995 #define BP_UART_SFIFO_RXOF (2U) /*!< Bit position for UART_SFIFO_RXOF. */ 02996 #define BM_UART_SFIFO_RXOF (0x04U) /*!< Bit mask for UART_SFIFO_RXOF. */ 02997 #define BS_UART_SFIFO_RXOF (1U) /*!< Bit field size in bits for UART_SFIFO_RXOF. */ 02998 02999 /*! @brief Read current value of the UART_SFIFO_RXOF field. */ 03000 #define BR_UART_SFIFO_RXOF(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF))) 03001 03002 /*! @brief Format value for bitfield UART_SFIFO_RXOF. */ 03003 #define BF_UART_SFIFO_RXOF(v) ((uint8_t)((uint8_t)(v) << BP_UART_SFIFO_RXOF) & BM_UART_SFIFO_RXOF) 03004 03005 /*! @brief Set the RXOF field to a new value. */ 03006 #define BW_UART_SFIFO_RXOF(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXOF), v)) 03007 /*@}*/ 03008 03009 /*! 03010 * @name Register UART_SFIFO, field RXEMPT[6] (RO) 03011 * 03012 * Asserts when there is no data in the receive FIFO/Buffer. This field does not 03013 * take into account data that is in the receive shift register. 03014 * 03015 * Values: 03016 * - 0 - Receive buffer is not empty. 03017 * - 1 - Receive buffer is empty. 03018 */ 03019 /*@{*/ 03020 #define BP_UART_SFIFO_RXEMPT (6U) /*!< Bit position for UART_SFIFO_RXEMPT. */ 03021 #define BM_UART_SFIFO_RXEMPT (0x40U) /*!< Bit mask for UART_SFIFO_RXEMPT. */ 03022 #define BS_UART_SFIFO_RXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_RXEMPT. */ 03023 03024 /*! @brief Read current value of the UART_SFIFO_RXEMPT field. */ 03025 #define BR_UART_SFIFO_RXEMPT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_RXEMPT))) 03026 /*@}*/ 03027 03028 /*! 03029 * @name Register UART_SFIFO, field TXEMPT[7] (RO) 03030 * 03031 * Asserts when there is no data in the Transmit FIFO/buffer. This field does 03032 * not take into account data that is in the transmit shift register. 03033 * 03034 * Values: 03035 * - 0 - Transmit buffer is not empty. 03036 * - 1 - Transmit buffer is empty. 03037 */ 03038 /*@{*/ 03039 #define BP_UART_SFIFO_TXEMPT (7U) /*!< Bit position for UART_SFIFO_TXEMPT. */ 03040 #define BM_UART_SFIFO_TXEMPT (0x80U) /*!< Bit mask for UART_SFIFO_TXEMPT. */ 03041 #define BS_UART_SFIFO_TXEMPT (1U) /*!< Bit field size in bits for UART_SFIFO_TXEMPT. */ 03042 03043 /*! @brief Read current value of the UART_SFIFO_TXEMPT field. */ 03044 #define BR_UART_SFIFO_TXEMPT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_SFIFO_ADDR(x), BP_UART_SFIFO_TXEMPT))) 03045 /*@}*/ 03046 03047 /******************************************************************************* 03048 * HW_UART_TWFIFO - UART FIFO Transmit Watermark 03049 ******************************************************************************/ 03050 03051 /*! 03052 * @brief HW_UART_TWFIFO - UART FIFO Transmit Watermark (RW) 03053 * 03054 * Reset value: 0x00U 03055 * 03056 * This register provides the ability to set a programmable threshold for 03057 * notification of needing additional transmit data. This register may be read at any 03058 * time but must be written only when C2[TE] is not set. Changing the value of the 03059 * watermark will not clear the S1[TDRE] flag. 03060 */ 03061 typedef union _hw_uart_twfifo 03062 { 03063 uint8_t U; 03064 struct _hw_uart_twfifo_bitfields 03065 { 03066 uint8_t TXWATER : 8; /*!< [7:0] Transmit Watermark */ 03067 } B; 03068 } hw_uart_twfifo_t; 03069 03070 /*! 03071 * @name Constants and macros for entire UART_TWFIFO register 03072 */ 03073 /*@{*/ 03074 #define HW_UART_TWFIFO_ADDR(x) ((x) + 0x13U) 03075 03076 #define HW_UART_TWFIFO(x) (*(__IO hw_uart_twfifo_t *) HW_UART_TWFIFO_ADDR(x)) 03077 #define HW_UART_TWFIFO_RD(x) (ADDRESS_READ(hw_uart_twfifo_t, HW_UART_TWFIFO_ADDR(x))) 03078 #define HW_UART_TWFIFO_WR(x, v) (ADDRESS_WRITE(hw_uart_twfifo_t, HW_UART_TWFIFO_ADDR(x), v)) 03079 #define HW_UART_TWFIFO_SET(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) | (v))) 03080 #define HW_UART_TWFIFO_CLR(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) & ~(v))) 03081 #define HW_UART_TWFIFO_TOG(x, v) (HW_UART_TWFIFO_WR(x, HW_UART_TWFIFO_RD(x) ^ (v))) 03082 /*@}*/ 03083 03084 /* 03085 * Constants & macros for individual UART_TWFIFO bitfields 03086 */ 03087 03088 /*! 03089 * @name Register UART_TWFIFO, field TXWATER[7:0] (RW) 03090 * 03091 * When the number of datawords in the transmit FIFO/buffer is equal to or less 03092 * than the value in this register field, an interrupt via S1[TDRE] or a DMA 03093 * request via C5[TDMAS] is generated as determined by C5[TDMAS] and C2[TIE]. For 03094 * proper operation, the value in TXWATER must be set to be less than the size of 03095 * the transmit buffer/FIFO size as indicated by PFIFO[TXFIFOSIZE] and PFIFO[TXFE]. 03096 */ 03097 /*@{*/ 03098 #define BP_UART_TWFIFO_TXWATER (0U) /*!< Bit position for UART_TWFIFO_TXWATER. */ 03099 #define BM_UART_TWFIFO_TXWATER (0xFFU) /*!< Bit mask for UART_TWFIFO_TXWATER. */ 03100 #define BS_UART_TWFIFO_TXWATER (8U) /*!< Bit field size in bits for UART_TWFIFO_TXWATER. */ 03101 03102 /*! @brief Read current value of the UART_TWFIFO_TXWATER field. */ 03103 #define BR_UART_TWFIFO_TXWATER(x) (HW_UART_TWFIFO(x).U) 03104 03105 /*! @brief Format value for bitfield UART_TWFIFO_TXWATER. */ 03106 #define BF_UART_TWFIFO_TXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_TWFIFO_TXWATER) & BM_UART_TWFIFO_TXWATER) 03107 03108 /*! @brief Set the TXWATER field to a new value. */ 03109 #define BW_UART_TWFIFO_TXWATER(x, v) (HW_UART_TWFIFO_WR(x, v)) 03110 /*@}*/ 03111 03112 /******************************************************************************* 03113 * HW_UART_TCFIFO - UART FIFO Transmit Count 03114 ******************************************************************************/ 03115 03116 /*! 03117 * @brief HW_UART_TCFIFO - UART FIFO Transmit Count (RO) 03118 * 03119 * Reset value: 0x00U 03120 * 03121 * This is a read only register that indicates how many datawords are currently 03122 * in the transmit buffer/FIFO. It may be read at any time. 03123 */ 03124 typedef union _hw_uart_tcfifo 03125 { 03126 uint8_t U; 03127 struct _hw_uart_tcfifo_bitfields 03128 { 03129 uint8_t TXCOUNT : 8; /*!< [7:0] Transmit Counter */ 03130 } B; 03131 } hw_uart_tcfifo_t; 03132 03133 /*! 03134 * @name Constants and macros for entire UART_TCFIFO register 03135 */ 03136 /*@{*/ 03137 #define HW_UART_TCFIFO_ADDR(x) ((x) + 0x14U) 03138 03139 #define HW_UART_TCFIFO(x) (*(__I hw_uart_tcfifo_t *) HW_UART_TCFIFO_ADDR(x)) 03140 #define HW_UART_TCFIFO_RD(x) (ADDRESS_READ(hw_uart_tcfifo_t, HW_UART_TCFIFO_ADDR(x))) 03141 /*@}*/ 03142 03143 /* 03144 * Constants & macros for individual UART_TCFIFO bitfields 03145 */ 03146 03147 /*! 03148 * @name Register UART_TCFIFO, field TXCOUNT[7:0] (RO) 03149 * 03150 * The value in this register indicates the number of datawords that are in the 03151 * transmit FIFO/buffer. If a dataword is being transmitted, that is, in the 03152 * transmit shift register, it is not included in the count. This value may be used 03153 * in conjunction with PFIFO[TXFIFOSIZE] to calculate how much room is left in the 03154 * transmit FIFO/buffer. 03155 */ 03156 /*@{*/ 03157 #define BP_UART_TCFIFO_TXCOUNT (0U) /*!< Bit position for UART_TCFIFO_TXCOUNT. */ 03158 #define BM_UART_TCFIFO_TXCOUNT (0xFFU) /*!< Bit mask for UART_TCFIFO_TXCOUNT. */ 03159 #define BS_UART_TCFIFO_TXCOUNT (8U) /*!< Bit field size in bits for UART_TCFIFO_TXCOUNT. */ 03160 03161 /*! @brief Read current value of the UART_TCFIFO_TXCOUNT field. */ 03162 #define BR_UART_TCFIFO_TXCOUNT(x) (HW_UART_TCFIFO(x).U) 03163 /*@}*/ 03164 03165 /******************************************************************************* 03166 * HW_UART_RWFIFO - UART FIFO Receive Watermark 03167 ******************************************************************************/ 03168 03169 /*! 03170 * @brief HW_UART_RWFIFO - UART FIFO Receive Watermark (RW) 03171 * 03172 * Reset value: 0x01U 03173 * 03174 * This register provides the ability to set a programmable threshold for 03175 * notification of the need to remove data from the receiver FIFO/buffer. This register 03176 * may be read at any time but must be written only when C2[RE] is not asserted. 03177 * Changing the value in this register will not clear S1[RDRF]. 03178 */ 03179 typedef union _hw_uart_rwfifo 03180 { 03181 uint8_t U; 03182 struct _hw_uart_rwfifo_bitfields 03183 { 03184 uint8_t RXWATER : 8; /*!< [7:0] Receive Watermark */ 03185 } B; 03186 } hw_uart_rwfifo_t; 03187 03188 /*! 03189 * @name Constants and macros for entire UART_RWFIFO register 03190 */ 03191 /*@{*/ 03192 #define HW_UART_RWFIFO_ADDR(x) ((x) + 0x15U) 03193 03194 #define HW_UART_RWFIFO(x) (*(__IO hw_uart_rwfifo_t *) HW_UART_RWFIFO_ADDR(x)) 03195 #define HW_UART_RWFIFO_RD(x) (ADDRESS_READ(hw_uart_rwfifo_t, HW_UART_RWFIFO_ADDR(x))) 03196 #define HW_UART_RWFIFO_WR(x, v) (ADDRESS_WRITE(hw_uart_rwfifo_t, HW_UART_RWFIFO_ADDR(x), v)) 03197 #define HW_UART_RWFIFO_SET(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) | (v))) 03198 #define HW_UART_RWFIFO_CLR(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) & ~(v))) 03199 #define HW_UART_RWFIFO_TOG(x, v) (HW_UART_RWFIFO_WR(x, HW_UART_RWFIFO_RD(x) ^ (v))) 03200 /*@}*/ 03201 03202 /* 03203 * Constants & macros for individual UART_RWFIFO bitfields 03204 */ 03205 03206 /*! 03207 * @name Register UART_RWFIFO, field RXWATER[7:0] (RW) 03208 * 03209 * When the number of datawords in the receive FIFO/buffer is equal to or 03210 * greater than the value in this register field, an interrupt via S1[RDRF] or a DMA 03211 * request via C5[RDMAS] is generated as determined by C5[RDMAS] and C2[RIE]. For 03212 * proper operation, the value in RXWATER must be set to be less than the receive 03213 * FIFO/buffer size as indicated by PFIFO[RXFIFOSIZE] and PFIFO[RXFE] and must be 03214 * greater than 0. 03215 */ 03216 /*@{*/ 03217 #define BP_UART_RWFIFO_RXWATER (0U) /*!< Bit position for UART_RWFIFO_RXWATER. */ 03218 #define BM_UART_RWFIFO_RXWATER (0xFFU) /*!< Bit mask for UART_RWFIFO_RXWATER. */ 03219 #define BS_UART_RWFIFO_RXWATER (8U) /*!< Bit field size in bits for UART_RWFIFO_RXWATER. */ 03220 03221 /*! @brief Read current value of the UART_RWFIFO_RXWATER field. */ 03222 #define BR_UART_RWFIFO_RXWATER(x) (HW_UART_RWFIFO(x).U) 03223 03224 /*! @brief Format value for bitfield UART_RWFIFO_RXWATER. */ 03225 #define BF_UART_RWFIFO_RXWATER(v) ((uint8_t)((uint8_t)(v) << BP_UART_RWFIFO_RXWATER) & BM_UART_RWFIFO_RXWATER) 03226 03227 /*! @brief Set the RXWATER field to a new value. */ 03228 #define BW_UART_RWFIFO_RXWATER(x, v) (HW_UART_RWFIFO_WR(x, v)) 03229 /*@}*/ 03230 03231 /******************************************************************************* 03232 * HW_UART_RCFIFO - UART FIFO Receive Count 03233 ******************************************************************************/ 03234 03235 /*! 03236 * @brief HW_UART_RCFIFO - UART FIFO Receive Count (RO) 03237 * 03238 * Reset value: 0x00U 03239 * 03240 * This is a read only register that indicates how many datawords are currently 03241 * in the receive FIFO/buffer. It may be read at any time. 03242 */ 03243 typedef union _hw_uart_rcfifo 03244 { 03245 uint8_t U; 03246 struct _hw_uart_rcfifo_bitfields 03247 { 03248 uint8_t RXCOUNT : 8; /*!< [7:0] Receive Counter */ 03249 } B; 03250 } hw_uart_rcfifo_t; 03251 03252 /*! 03253 * @name Constants and macros for entire UART_RCFIFO register 03254 */ 03255 /*@{*/ 03256 #define HW_UART_RCFIFO_ADDR(x) ((x) + 0x16U) 03257 03258 #define HW_UART_RCFIFO(x) (*(__I hw_uart_rcfifo_t *) HW_UART_RCFIFO_ADDR(x)) 03259 #define HW_UART_RCFIFO_RD(x) (ADDRESS_READ(hw_uart_rcfifo_t, HW_UART_RCFIFO_ADDR(x))) 03260 /*@}*/ 03261 03262 /* 03263 * Constants & macros for individual UART_RCFIFO bitfields 03264 */ 03265 03266 /*! 03267 * @name Register UART_RCFIFO, field RXCOUNT[7:0] (RO) 03268 * 03269 * The value in this register indicates the number of datawords that are in the 03270 * receive FIFO/buffer. If a dataword is being received, that is, in the receive 03271 * shift register, it is not included in the count. This value may be used in 03272 * conjunction with PFIFO[RXFIFOSIZE] to calculate how much room is left in the 03273 * receive FIFO/buffer. 03274 */ 03275 /*@{*/ 03276 #define BP_UART_RCFIFO_RXCOUNT (0U) /*!< Bit position for UART_RCFIFO_RXCOUNT. */ 03277 #define BM_UART_RCFIFO_RXCOUNT (0xFFU) /*!< Bit mask for UART_RCFIFO_RXCOUNT. */ 03278 #define BS_UART_RCFIFO_RXCOUNT (8U) /*!< Bit field size in bits for UART_RCFIFO_RXCOUNT. */ 03279 03280 /*! @brief Read current value of the UART_RCFIFO_RXCOUNT field. */ 03281 #define BR_UART_RCFIFO_RXCOUNT(x) (HW_UART_RCFIFO(x).U) 03282 /*@}*/ 03283 03284 /******************************************************************************* 03285 * HW_UART_C7816 - UART 7816 Control Register 03286 ******************************************************************************/ 03287 03288 /*! 03289 * @brief HW_UART_C7816 - UART 7816 Control Register (RW) 03290 * 03291 * Reset value: 0x00U 03292 * 03293 * The C7816 register is the primary control register for ISO-7816 specific 03294 * functionality. This register is specific to 7816 functionality and the values in 03295 * this register have no effect on UART operation and should be ignored if 03296 * ISO_7816E is not set/enabled. This register may be read at any time but values must 03297 * be changed only when ISO_7816E is not set. 03298 */ 03299 typedef union _hw_uart_c7816 03300 { 03301 uint8_t U; 03302 struct _hw_uart_c7816_bitfields 03303 { 03304 uint8_t ISO_7816E : 1; /*!< [0] ISO-7816 Functionality Enabled */ 03305 uint8_t TTYPE : 1; /*!< [1] Transfer Type */ 03306 uint8_t INIT : 1; /*!< [2] Detect Initial Character */ 03307 uint8_t ANACK : 1; /*!< [3] Generate NACK on Error */ 03308 uint8_t ONACK : 1; /*!< [4] Generate NACK on Overflow */ 03309 uint8_t RESERVED0 : 3; /*!< [7:5] */ 03310 } B; 03311 } hw_uart_c7816_t; 03312 03313 /*! 03314 * @name Constants and macros for entire UART_C7816 register 03315 */ 03316 /*@{*/ 03317 #define HW_UART_C7816_ADDR(x) ((x) + 0x18U) 03318 03319 #define HW_UART_C7816(x) (*(__IO hw_uart_c7816_t *) HW_UART_C7816_ADDR(x)) 03320 #define HW_UART_C7816_RD(x) (ADDRESS_READ(hw_uart_c7816_t, HW_UART_C7816_ADDR(x))) 03321 #define HW_UART_C7816_WR(x, v) (ADDRESS_WRITE(hw_uart_c7816_t, HW_UART_C7816_ADDR(x), v)) 03322 #define HW_UART_C7816_SET(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) | (v))) 03323 #define HW_UART_C7816_CLR(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) & ~(v))) 03324 #define HW_UART_C7816_TOG(x, v) (HW_UART_C7816_WR(x, HW_UART_C7816_RD(x) ^ (v))) 03325 /*@}*/ 03326 03327 /* 03328 * Constants & macros for individual UART_C7816 bitfields 03329 */ 03330 03331 /*! 03332 * @name Register UART_C7816, field ISO_7816E[0] (RW) 03333 * 03334 * Indicates that the UART is operating according to the ISO-7816 protocol. This 03335 * field must be modified only when no transmit or receive is occurring. If this 03336 * field is changed during a data transfer, the data being transmitted or 03337 * received may be transferred incorrectly. 03338 * 03339 * Values: 03340 * - 0 - ISO-7816 functionality is turned off/not enabled. 03341 * - 1 - ISO-7816 functionality is turned on/enabled. 03342 */ 03343 /*@{*/ 03344 #define BP_UART_C7816_ISO_7816E (0U) /*!< Bit position for UART_C7816_ISO_7816E. */ 03345 #define BM_UART_C7816_ISO_7816E (0x01U) /*!< Bit mask for UART_C7816_ISO_7816E. */ 03346 #define BS_UART_C7816_ISO_7816E (1U) /*!< Bit field size in bits for UART_C7816_ISO_7816E. */ 03347 03348 /*! @brief Read current value of the UART_C7816_ISO_7816E field. */ 03349 #define BR_UART_C7816_ISO_7816E(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E))) 03350 03351 /*! @brief Format value for bitfield UART_C7816_ISO_7816E. */ 03352 #define BF_UART_C7816_ISO_7816E(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ISO_7816E) & BM_UART_C7816_ISO_7816E) 03353 03354 /*! @brief Set the ISO_7816E field to a new value. */ 03355 #define BW_UART_C7816_ISO_7816E(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ISO_7816E), v)) 03356 /*@}*/ 03357 03358 /*! 03359 * @name Register UART_C7816, field TTYPE[1] (RW) 03360 * 03361 * Indicates the transfer protocol being used. See ISO-7816 / smartcard support 03362 * for more details. 03363 * 03364 * Values: 03365 * - 0 - T = 0 per the ISO-7816 specification. 03366 * - 1 - T = 1 per the ISO-7816 specification. 03367 */ 03368 /*@{*/ 03369 #define BP_UART_C7816_TTYPE (1U) /*!< Bit position for UART_C7816_TTYPE. */ 03370 #define BM_UART_C7816_TTYPE (0x02U) /*!< Bit mask for UART_C7816_TTYPE. */ 03371 #define BS_UART_C7816_TTYPE (1U) /*!< Bit field size in bits for UART_C7816_TTYPE. */ 03372 03373 /*! @brief Read current value of the UART_C7816_TTYPE field. */ 03374 #define BR_UART_C7816_TTYPE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE))) 03375 03376 /*! @brief Format value for bitfield UART_C7816_TTYPE. */ 03377 #define BF_UART_C7816_TTYPE(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_TTYPE) & BM_UART_C7816_TTYPE) 03378 03379 /*! @brief Set the TTYPE field to a new value. */ 03380 #define BW_UART_C7816_TTYPE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_TTYPE), v)) 03381 /*@}*/ 03382 03383 /*! 03384 * @name Register UART_C7816, field INIT[2] (RW) 03385 * 03386 * When this field is set, all received characters are searched for a valid 03387 * initial character. If an invalid initial character is identified, and ANACK is 03388 * set, a NACK is sent. All received data is discarded and error flags blocked 03389 * (S1[NF], S1[OR], S1[FE], S1[PF], IS7816[WT], IS7816[CWT], IS7816[BWT], IS7816[GTV]) 03390 * until a valid initial character is detected. Upon detecting a valid initial 03391 * character, the configuration values S2[MSBF], C3[TXINV], and S2[RXINV] are 03392 * automatically updated to reflect the initial character that was received. The 03393 * actual INIT data value is not stored in the receive buffer. Additionally, upon 03394 * detection of a valid initial character, IS7816[INITD] is set and an interrupt 03395 * issued as programmed by IE7816[INITDE]. When a valid initial character is 03396 * detected, INIT is automatically cleared. This Initial Character Detect feature is 03397 * supported only in T = 0 protocol mode. 03398 * 03399 * Values: 03400 * - 0 - Normal operating mode. Receiver does not seek to identify initial 03401 * character. 03402 * - 1 - Receiver searches for initial character. 03403 */ 03404 /*@{*/ 03405 #define BP_UART_C7816_INIT (2U) /*!< Bit position for UART_C7816_INIT. */ 03406 #define BM_UART_C7816_INIT (0x04U) /*!< Bit mask for UART_C7816_INIT. */ 03407 #define BS_UART_C7816_INIT (1U) /*!< Bit field size in bits for UART_C7816_INIT. */ 03408 03409 /*! @brief Read current value of the UART_C7816_INIT field. */ 03410 #define BR_UART_C7816_INIT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT))) 03411 03412 /*! @brief Format value for bitfield UART_C7816_INIT. */ 03413 #define BF_UART_C7816_INIT(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_INIT) & BM_UART_C7816_INIT) 03414 03415 /*! @brief Set the INIT field to a new value. */ 03416 #define BW_UART_C7816_INIT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_INIT), v)) 03417 /*@}*/ 03418 03419 /*! 03420 * @name Register UART_C7816, field ANACK[3] (RW) 03421 * 03422 * When this field is set, the receiver automatically generates a NACK response 03423 * if a parity error occurs or if INIT is set and an invalid initial character is 03424 * detected. A NACK is generated only if TTYPE = 0. If ANACK is set, the UART 03425 * attempts to retransmit the data indefinitely. To stop retransmission attempts, 03426 * clear C2[TE] or ISO_7816E and do not set until S1[TC] sets C2[TE] again. 03427 * 03428 * Values: 03429 * - 0 - No NACK is automatically generated. 03430 * - 1 - A NACK is automatically generated if a parity error is detected or if 03431 * an invalid initial character is detected. 03432 */ 03433 /*@{*/ 03434 #define BP_UART_C7816_ANACK (3U) /*!< Bit position for UART_C7816_ANACK. */ 03435 #define BM_UART_C7816_ANACK (0x08U) /*!< Bit mask for UART_C7816_ANACK. */ 03436 #define BS_UART_C7816_ANACK (1U) /*!< Bit field size in bits for UART_C7816_ANACK. */ 03437 03438 /*! @brief Read current value of the UART_C7816_ANACK field. */ 03439 #define BR_UART_C7816_ANACK(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK))) 03440 03441 /*! @brief Format value for bitfield UART_C7816_ANACK. */ 03442 #define BF_UART_C7816_ANACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ANACK) & BM_UART_C7816_ANACK) 03443 03444 /*! @brief Set the ANACK field to a new value. */ 03445 #define BW_UART_C7816_ANACK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ANACK), v)) 03446 /*@}*/ 03447 03448 /*! 03449 * @name Register UART_C7816, field ONACK[4] (RW) 03450 * 03451 * When this field is set, the receiver automatically generates a NACK response 03452 * if a receive buffer overrun occurs, as indicated by S1[OR]. In many systems, 03453 * this results in the transmitter resending the packet that overflowed until the 03454 * retransmit threshold for that transmitter is reached. A NACK is generated only 03455 * if TTYPE=0. This field operates independently of ANACK. See . Overrun NACK 03456 * considerations 03457 * 03458 * Values: 03459 * - 0 - The received data does not generate a NACK when the receipt of the data 03460 * results in an overflow event. 03461 * - 1 - If the receiver buffer overflows, a NACK is automatically sent on a 03462 * received character. 03463 */ 03464 /*@{*/ 03465 #define BP_UART_C7816_ONACK (4U) /*!< Bit position for UART_C7816_ONACK. */ 03466 #define BM_UART_C7816_ONACK (0x10U) /*!< Bit mask for UART_C7816_ONACK. */ 03467 #define BS_UART_C7816_ONACK (1U) /*!< Bit field size in bits for UART_C7816_ONACK. */ 03468 03469 /*! @brief Read current value of the UART_C7816_ONACK field. */ 03470 #define BR_UART_C7816_ONACK(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK))) 03471 03472 /*! @brief Format value for bitfield UART_C7816_ONACK. */ 03473 #define BF_UART_C7816_ONACK(v) ((uint8_t)((uint8_t)(v) << BP_UART_C7816_ONACK) & BM_UART_C7816_ONACK) 03474 03475 /*! @brief Set the ONACK field to a new value. */ 03476 #define BW_UART_C7816_ONACK(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_C7816_ADDR(x), BP_UART_C7816_ONACK), v)) 03477 /*@}*/ 03478 03479 /******************************************************************************* 03480 * HW_UART_IE7816 - UART 7816 Interrupt Enable Register 03481 ******************************************************************************/ 03482 03483 /*! 03484 * @brief HW_UART_IE7816 - UART 7816 Interrupt Enable Register (RW) 03485 * 03486 * Reset value: 0x00U 03487 * 03488 * The IE7816 register controls which flags result in an interrupt being issued. 03489 * This register is specific to 7816 functionality, the corresponding flags that 03490 * drive the interrupts are not asserted when 7816E is not set/enabled. However, 03491 * these flags may remain set if they are asserted while 7816E was set and not 03492 * subsequently cleared. This register may be read or written to at any time. 03493 */ 03494 typedef union _hw_uart_ie7816 03495 { 03496 uint8_t U; 03497 struct _hw_uart_ie7816_bitfields 03498 { 03499 uint8_t RXTE : 1; /*!< [0] Receive Threshold Exceeded Interrupt 03500 * Enable */ 03501 uint8_t TXTE : 1; /*!< [1] Transmit Threshold Exceeded Interrupt 03502 * Enable */ 03503 uint8_t GTVE : 1; /*!< [2] Guard Timer Violated Interrupt Enable */ 03504 uint8_t RESERVED0 : 1; /*!< [3] */ 03505 uint8_t INITDE : 1; /*!< [4] Initial Character Detected Interrupt 03506 * Enable */ 03507 uint8_t BWTE : 1; /*!< [5] Block Wait Timer Interrupt Enable */ 03508 uint8_t CWTE : 1; /*!< [6] Character Wait Timer Interrupt Enable */ 03509 uint8_t WTE : 1; /*!< [7] Wait Timer Interrupt Enable */ 03510 } B; 03511 } hw_uart_ie7816_t; 03512 03513 /*! 03514 * @name Constants and macros for entire UART_IE7816 register 03515 */ 03516 /*@{*/ 03517 #define HW_UART_IE7816_ADDR(x) ((x) + 0x19U) 03518 03519 #define HW_UART_IE7816(x) (*(__IO hw_uart_ie7816_t *) HW_UART_IE7816_ADDR(x)) 03520 #define HW_UART_IE7816_RD(x) (ADDRESS_READ(hw_uart_ie7816_t, HW_UART_IE7816_ADDR(x))) 03521 #define HW_UART_IE7816_WR(x, v) (ADDRESS_WRITE(hw_uart_ie7816_t, HW_UART_IE7816_ADDR(x), v)) 03522 #define HW_UART_IE7816_SET(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) | (v))) 03523 #define HW_UART_IE7816_CLR(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) & ~(v))) 03524 #define HW_UART_IE7816_TOG(x, v) (HW_UART_IE7816_WR(x, HW_UART_IE7816_RD(x) ^ (v))) 03525 /*@}*/ 03526 03527 /* 03528 * Constants & macros for individual UART_IE7816 bitfields 03529 */ 03530 03531 /*! 03532 * @name Register UART_IE7816, field RXTE[0] (RW) 03533 * 03534 * Values: 03535 * - 0 - The assertion of IS7816[RXT] does not result in the generation of an 03536 * interrupt. 03537 * - 1 - The assertion of IS7816[RXT] results in the generation of an interrupt. 03538 */ 03539 /*@{*/ 03540 #define BP_UART_IE7816_RXTE (0U) /*!< Bit position for UART_IE7816_RXTE. */ 03541 #define BM_UART_IE7816_RXTE (0x01U) /*!< Bit mask for UART_IE7816_RXTE. */ 03542 #define BS_UART_IE7816_RXTE (1U) /*!< Bit field size in bits for UART_IE7816_RXTE. */ 03543 03544 /*! @brief Read current value of the UART_IE7816_RXTE field. */ 03545 #define BR_UART_IE7816_RXTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE))) 03546 03547 /*! @brief Format value for bitfield UART_IE7816_RXTE. */ 03548 #define BF_UART_IE7816_RXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_RXTE) & BM_UART_IE7816_RXTE) 03549 03550 /*! @brief Set the RXTE field to a new value. */ 03551 #define BW_UART_IE7816_RXTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_RXTE), v)) 03552 /*@}*/ 03553 03554 /*! 03555 * @name Register UART_IE7816, field TXTE[1] (RW) 03556 * 03557 * Values: 03558 * - 0 - The assertion of IS7816[TXT] does not result in the generation of an 03559 * interrupt. 03560 * - 1 - The assertion of IS7816[TXT] results in the generation of an interrupt. 03561 */ 03562 /*@{*/ 03563 #define BP_UART_IE7816_TXTE (1U) /*!< Bit position for UART_IE7816_TXTE. */ 03564 #define BM_UART_IE7816_TXTE (0x02U) /*!< Bit mask for UART_IE7816_TXTE. */ 03565 #define BS_UART_IE7816_TXTE (1U) /*!< Bit field size in bits for UART_IE7816_TXTE. */ 03566 03567 /*! @brief Read current value of the UART_IE7816_TXTE field. */ 03568 #define BR_UART_IE7816_TXTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE))) 03569 03570 /*! @brief Format value for bitfield UART_IE7816_TXTE. */ 03571 #define BF_UART_IE7816_TXTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_TXTE) & BM_UART_IE7816_TXTE) 03572 03573 /*! @brief Set the TXTE field to a new value. */ 03574 #define BW_UART_IE7816_TXTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_TXTE), v)) 03575 /*@}*/ 03576 03577 /*! 03578 * @name Register UART_IE7816, field GTVE[2] (RW) 03579 * 03580 * Values: 03581 * - 0 - The assertion of IS7816[GTV] does not result in the generation of an 03582 * interrupt. 03583 * - 1 - The assertion of IS7816[GTV] results in the generation of an interrupt. 03584 */ 03585 /*@{*/ 03586 #define BP_UART_IE7816_GTVE (2U) /*!< Bit position for UART_IE7816_GTVE. */ 03587 #define BM_UART_IE7816_GTVE (0x04U) /*!< Bit mask for UART_IE7816_GTVE. */ 03588 #define BS_UART_IE7816_GTVE (1U) /*!< Bit field size in bits for UART_IE7816_GTVE. */ 03589 03590 /*! @brief Read current value of the UART_IE7816_GTVE field. */ 03591 #define BR_UART_IE7816_GTVE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE))) 03592 03593 /*! @brief Format value for bitfield UART_IE7816_GTVE. */ 03594 #define BF_UART_IE7816_GTVE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_GTVE) & BM_UART_IE7816_GTVE) 03595 03596 /*! @brief Set the GTVE field to a new value. */ 03597 #define BW_UART_IE7816_GTVE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_GTVE), v)) 03598 /*@}*/ 03599 03600 /*! 03601 * @name Register UART_IE7816, field INITDE[4] (RW) 03602 * 03603 * Values: 03604 * - 0 - The assertion of IS7816[INITD] does not result in the generation of an 03605 * interrupt. 03606 * - 1 - The assertion of IS7816[INITD] results in the generation of an 03607 * interrupt. 03608 */ 03609 /*@{*/ 03610 #define BP_UART_IE7816_INITDE (4U) /*!< Bit position for UART_IE7816_INITDE. */ 03611 #define BM_UART_IE7816_INITDE (0x10U) /*!< Bit mask for UART_IE7816_INITDE. */ 03612 #define BS_UART_IE7816_INITDE (1U) /*!< Bit field size in bits for UART_IE7816_INITDE. */ 03613 03614 /*! @brief Read current value of the UART_IE7816_INITDE field. */ 03615 #define BR_UART_IE7816_INITDE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE))) 03616 03617 /*! @brief Format value for bitfield UART_IE7816_INITDE. */ 03618 #define BF_UART_IE7816_INITDE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_INITDE) & BM_UART_IE7816_INITDE) 03619 03620 /*! @brief Set the INITDE field to a new value. */ 03621 #define BW_UART_IE7816_INITDE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_INITDE), v)) 03622 /*@}*/ 03623 03624 /*! 03625 * @name Register UART_IE7816, field BWTE[5] (RW) 03626 * 03627 * Values: 03628 * - 0 - The assertion of IS7816[BWT] does not result in the generation of an 03629 * interrupt. 03630 * - 1 - The assertion of IS7816[BWT] results in the generation of an interrupt. 03631 */ 03632 /*@{*/ 03633 #define BP_UART_IE7816_BWTE (5U) /*!< Bit position for UART_IE7816_BWTE. */ 03634 #define BM_UART_IE7816_BWTE (0x20U) /*!< Bit mask for UART_IE7816_BWTE. */ 03635 #define BS_UART_IE7816_BWTE (1U) /*!< Bit field size in bits for UART_IE7816_BWTE. */ 03636 03637 /*! @brief Read current value of the UART_IE7816_BWTE field. */ 03638 #define BR_UART_IE7816_BWTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE))) 03639 03640 /*! @brief Format value for bitfield UART_IE7816_BWTE. */ 03641 #define BF_UART_IE7816_BWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_BWTE) & BM_UART_IE7816_BWTE) 03642 03643 /*! @brief Set the BWTE field to a new value. */ 03644 #define BW_UART_IE7816_BWTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_BWTE), v)) 03645 /*@}*/ 03646 03647 /*! 03648 * @name Register UART_IE7816, field CWTE[6] (RW) 03649 * 03650 * Values: 03651 * - 0 - The assertion of IS7816[CWT] does not result in the generation of an 03652 * interrupt. 03653 * - 1 - The assertion of IS7816[CWT] results in the generation of an interrupt. 03654 */ 03655 /*@{*/ 03656 #define BP_UART_IE7816_CWTE (6U) /*!< Bit position for UART_IE7816_CWTE. */ 03657 #define BM_UART_IE7816_CWTE (0x40U) /*!< Bit mask for UART_IE7816_CWTE. */ 03658 #define BS_UART_IE7816_CWTE (1U) /*!< Bit field size in bits for UART_IE7816_CWTE. */ 03659 03660 /*! @brief Read current value of the UART_IE7816_CWTE field. */ 03661 #define BR_UART_IE7816_CWTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE))) 03662 03663 /*! @brief Format value for bitfield UART_IE7816_CWTE. */ 03664 #define BF_UART_IE7816_CWTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_CWTE) & BM_UART_IE7816_CWTE) 03665 03666 /*! @brief Set the CWTE field to a new value. */ 03667 #define BW_UART_IE7816_CWTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_CWTE), v)) 03668 /*@}*/ 03669 03670 /*! 03671 * @name Register UART_IE7816, field WTE[7] (RW) 03672 * 03673 * Values: 03674 * - 0 - The assertion of IS7816[WT] does not result in the generation of an 03675 * interrupt. 03676 * - 1 - The assertion of IS7816[WT] results in the generation of an interrupt. 03677 */ 03678 /*@{*/ 03679 #define BP_UART_IE7816_WTE (7U) /*!< Bit position for UART_IE7816_WTE. */ 03680 #define BM_UART_IE7816_WTE (0x80U) /*!< Bit mask for UART_IE7816_WTE. */ 03681 #define BS_UART_IE7816_WTE (1U) /*!< Bit field size in bits for UART_IE7816_WTE. */ 03682 03683 /*! @brief Read current value of the UART_IE7816_WTE field. */ 03684 #define BR_UART_IE7816_WTE(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE))) 03685 03686 /*! @brief Format value for bitfield UART_IE7816_WTE. */ 03687 #define BF_UART_IE7816_WTE(v) ((uint8_t)((uint8_t)(v) << BP_UART_IE7816_WTE) & BM_UART_IE7816_WTE) 03688 03689 /*! @brief Set the WTE field to a new value. */ 03690 #define BW_UART_IE7816_WTE(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IE7816_ADDR(x), BP_UART_IE7816_WTE), v)) 03691 /*@}*/ 03692 03693 /******************************************************************************* 03694 * HW_UART_IS7816 - UART 7816 Interrupt Status Register 03695 ******************************************************************************/ 03696 03697 /*! 03698 * @brief HW_UART_IS7816 - UART 7816 Interrupt Status Register (RW) 03699 * 03700 * Reset value: 0x00U 03701 * 03702 * The IS7816 register provides a mechanism to read and clear the interrupt 03703 * flags. All flags/interrupts are cleared by writing a 1 to the field location. 03704 * Writing a 0 has no effect. All bits are "sticky", meaning they indicate that only 03705 * the flag condition that occurred since the last time the bit was cleared, not 03706 * that the condition currently exists. The status flags are set regardless of 03707 * whether the corresponding field in the IE7816 is set or cleared. The IE7816 03708 * controls only if an interrupt is issued to the host processor. This register is 03709 * specific to 7816 functionality and the values in this register have no affect on 03710 * UART operation and should be ignored if 7816E is not set/enabled. This 03711 * register may be read or written at anytime. 03712 */ 03713 typedef union _hw_uart_is7816 03714 { 03715 uint8_t U; 03716 struct _hw_uart_is7816_bitfields 03717 { 03718 uint8_t RXT : 1; /*!< [0] Receive Threshold Exceeded Interrupt */ 03719 uint8_t TXT : 1; /*!< [1] Transmit Threshold Exceeded Interrupt */ 03720 uint8_t GTV : 1; /*!< [2] Guard Timer Violated Interrupt */ 03721 uint8_t RESERVED0 : 1; /*!< [3] */ 03722 uint8_t INITD : 1; /*!< [4] Initial Character Detected Interrupt */ 03723 uint8_t BWT : 1; /*!< [5] Block Wait Timer Interrupt */ 03724 uint8_t CWT : 1; /*!< [6] Character Wait Timer Interrupt */ 03725 uint8_t WT : 1; /*!< [7] Wait Timer Interrupt */ 03726 } B; 03727 } hw_uart_is7816_t; 03728 03729 /*! 03730 * @name Constants and macros for entire UART_IS7816 register 03731 */ 03732 /*@{*/ 03733 #define HW_UART_IS7816_ADDR(x) ((x) + 0x1AU) 03734 03735 #define HW_UART_IS7816(x) (*(__IO hw_uart_is7816_t *) HW_UART_IS7816_ADDR(x)) 03736 #define HW_UART_IS7816_RD(x) (ADDRESS_READ(hw_uart_is7816_t, HW_UART_IS7816_ADDR(x))) 03737 #define HW_UART_IS7816_WR(x, v) (ADDRESS_WRITE(hw_uart_is7816_t, HW_UART_IS7816_ADDR(x), v)) 03738 #define HW_UART_IS7816_SET(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) | (v))) 03739 #define HW_UART_IS7816_CLR(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) & ~(v))) 03740 #define HW_UART_IS7816_TOG(x, v) (HW_UART_IS7816_WR(x, HW_UART_IS7816_RD(x) ^ (v))) 03741 /*@}*/ 03742 03743 /* 03744 * Constants & macros for individual UART_IS7816 bitfields 03745 */ 03746 03747 /*! 03748 * @name Register UART_IS7816, field RXT[0] (W1C) 03749 * 03750 * Indicates that there are more than ET7816[RXTHRESHOLD] consecutive NACKS 03751 * generated in response to parity errors on received data. This flag requires ANACK 03752 * to be set. Additionally, this flag asserts only when C7816[TTYPE] = 0. 03753 * Clearing this field also resets the counter keeping track of consecutive NACKS. The 03754 * UART will continue to attempt to receive data regardless of whether this flag 03755 * is set. If 7816E is cleared/disabled, RE is cleared/disabled, C7816[TTYPE] = 1, 03756 * or packet is received without needing to issue a NACK, the internal NACK 03757 * detection counter is cleared and the count restarts from zero on the next 03758 * transmitted NACK. This interrupt is cleared by writing 1. 03759 * 03760 * Values: 03761 * - 0 - The number of consecutive NACKS generated as a result of parity errors 03762 * and buffer overruns is less than or equal to the value in 03763 * ET7816[RXTHRESHOLD]. 03764 * - 1 - The number of consecutive NACKS generated as a result of parity errors 03765 * and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. 03766 */ 03767 /*@{*/ 03768 #define BP_UART_IS7816_RXT (0U) /*!< Bit position for UART_IS7816_RXT. */ 03769 #define BM_UART_IS7816_RXT (0x01U) /*!< Bit mask for UART_IS7816_RXT. */ 03770 #define BS_UART_IS7816_RXT (1U) /*!< Bit field size in bits for UART_IS7816_RXT. */ 03771 03772 /*! @brief Read current value of the UART_IS7816_RXT field. */ 03773 #define BR_UART_IS7816_RXT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT))) 03774 03775 /*! @brief Format value for bitfield UART_IS7816_RXT. */ 03776 #define BF_UART_IS7816_RXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_RXT) & BM_UART_IS7816_RXT) 03777 03778 /*! @brief Set the RXT field to a new value. */ 03779 #define BW_UART_IS7816_RXT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_RXT), v)) 03780 /*@}*/ 03781 03782 /*! 03783 * @name Register UART_IS7816, field TXT[1] (W1C) 03784 * 03785 * Indicates that the transmit NACK threshold has been exceeded as indicated by 03786 * ET7816[TXTHRESHOLD]. Regardless of whether this flag is set, the UART 03787 * continues to retransmit indefinitely. This flag asserts only when C7816[TTYPE] = 0. If 03788 * 7816E is cleared/disabled, ANACK is cleared/disabled, C2[TE] is 03789 * cleared/disabled, C7816[TTYPE] = 1, or packet is transferred without receiving a NACK, the 03790 * internal NACK detection counter is cleared and the count restarts from zero on 03791 * the next received NACK. This interrupt is cleared by writing 1. 03792 * 03793 * Values: 03794 * - 0 - The number of retries and corresponding NACKS does not exceed the value 03795 * in ET7816[TXTHRESHOLD]. 03796 * - 1 - The number of retries and corresponding NACKS exceeds the value in 03797 * ET7816[TXTHRESHOLD]. 03798 */ 03799 /*@{*/ 03800 #define BP_UART_IS7816_TXT (1U) /*!< Bit position for UART_IS7816_TXT. */ 03801 #define BM_UART_IS7816_TXT (0x02U) /*!< Bit mask for UART_IS7816_TXT. */ 03802 #define BS_UART_IS7816_TXT (1U) /*!< Bit field size in bits for UART_IS7816_TXT. */ 03803 03804 /*! @brief Read current value of the UART_IS7816_TXT field. */ 03805 #define BR_UART_IS7816_TXT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT))) 03806 03807 /*! @brief Format value for bitfield UART_IS7816_TXT. */ 03808 #define BF_UART_IS7816_TXT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_TXT) & BM_UART_IS7816_TXT) 03809 03810 /*! @brief Set the TXT field to a new value. */ 03811 #define BW_UART_IS7816_TXT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_TXT), v)) 03812 /*@}*/ 03813 03814 /*! 03815 * @name Register UART_IS7816, field GTV[2] (W1C) 03816 * 03817 * Indicates that one or more of the character guard time, block guard time, or 03818 * guard time are violated. This interrupt is cleared by writing 1. 03819 * 03820 * Values: 03821 * - 0 - A guard time (GT, CGT, or BGT) has not been violated. 03822 * - 1 - A guard time (GT, CGT, or BGT) has been violated. 03823 */ 03824 /*@{*/ 03825 #define BP_UART_IS7816_GTV (2U) /*!< Bit position for UART_IS7816_GTV. */ 03826 #define BM_UART_IS7816_GTV (0x04U) /*!< Bit mask for UART_IS7816_GTV. */ 03827 #define BS_UART_IS7816_GTV (1U) /*!< Bit field size in bits for UART_IS7816_GTV. */ 03828 03829 /*! @brief Read current value of the UART_IS7816_GTV field. */ 03830 #define BR_UART_IS7816_GTV(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV))) 03831 03832 /*! @brief Format value for bitfield UART_IS7816_GTV. */ 03833 #define BF_UART_IS7816_GTV(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_GTV) & BM_UART_IS7816_GTV) 03834 03835 /*! @brief Set the GTV field to a new value. */ 03836 #define BW_UART_IS7816_GTV(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_GTV), v)) 03837 /*@}*/ 03838 03839 /*! 03840 * @name Register UART_IS7816, field INITD[4] (W1C) 03841 * 03842 * Indicates that a valid initial character is received. This interrupt is 03843 * cleared by writing 1. 03844 * 03845 * Values: 03846 * - 0 - A valid initial character has not been received. 03847 * - 1 - A valid initial character has been received. 03848 */ 03849 /*@{*/ 03850 #define BP_UART_IS7816_INITD (4U) /*!< Bit position for UART_IS7816_INITD. */ 03851 #define BM_UART_IS7816_INITD (0x10U) /*!< Bit mask for UART_IS7816_INITD. */ 03852 #define BS_UART_IS7816_INITD (1U) /*!< Bit field size in bits for UART_IS7816_INITD. */ 03853 03854 /*! @brief Read current value of the UART_IS7816_INITD field. */ 03855 #define BR_UART_IS7816_INITD(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD))) 03856 03857 /*! @brief Format value for bitfield UART_IS7816_INITD. */ 03858 #define BF_UART_IS7816_INITD(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_INITD) & BM_UART_IS7816_INITD) 03859 03860 /*! @brief Set the INITD field to a new value. */ 03861 #define BW_UART_IS7816_INITD(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_INITD), v)) 03862 /*@}*/ 03863 03864 /*! 03865 * @name Register UART_IS7816, field BWT[5] (W1C) 03866 * 03867 * Indicates that the block wait time, the time between the leading edge of 03868 * first received character of a block and the leading edge of the last character the 03869 * previously transmitted block, has exceeded the programmed value. This flag 03870 * asserts only when C7816[TTYPE] = 1.This interrupt is cleared by writing 1. 03871 * 03872 * Values: 03873 * - 0 - Block wait time (BWT) has not been violated. 03874 * - 1 - Block wait time (BWT) has been violated. 03875 */ 03876 /*@{*/ 03877 #define BP_UART_IS7816_BWT (5U) /*!< Bit position for UART_IS7816_BWT. */ 03878 #define BM_UART_IS7816_BWT (0x20U) /*!< Bit mask for UART_IS7816_BWT. */ 03879 #define BS_UART_IS7816_BWT (1U) /*!< Bit field size in bits for UART_IS7816_BWT. */ 03880 03881 /*! @brief Read current value of the UART_IS7816_BWT field. */ 03882 #define BR_UART_IS7816_BWT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT))) 03883 03884 /*! @brief Format value for bitfield UART_IS7816_BWT. */ 03885 #define BF_UART_IS7816_BWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_BWT) & BM_UART_IS7816_BWT) 03886 03887 /*! @brief Set the BWT field to a new value. */ 03888 #define BW_UART_IS7816_BWT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_BWT), v)) 03889 /*@}*/ 03890 03891 /*! 03892 * @name Register UART_IS7816, field CWT[6] (W1C) 03893 * 03894 * Indicates that the character wait time, the time between the leading edges of 03895 * two consecutive characters in a block, has exceeded the programmed value. 03896 * This flag asserts only when C7816[TTYPE] = 1. This interrupt is cleared by 03897 * writing 1. 03898 * 03899 * Values: 03900 * - 0 - Character wait time (CWT) has not been violated. 03901 * - 1 - Character wait time (CWT) has been violated. 03902 */ 03903 /*@{*/ 03904 #define BP_UART_IS7816_CWT (6U) /*!< Bit position for UART_IS7816_CWT. */ 03905 #define BM_UART_IS7816_CWT (0x40U) /*!< Bit mask for UART_IS7816_CWT. */ 03906 #define BS_UART_IS7816_CWT (1U) /*!< Bit field size in bits for UART_IS7816_CWT. */ 03907 03908 /*! @brief Read current value of the UART_IS7816_CWT field. */ 03909 #define BR_UART_IS7816_CWT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT))) 03910 03911 /*! @brief Format value for bitfield UART_IS7816_CWT. */ 03912 #define BF_UART_IS7816_CWT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_CWT) & BM_UART_IS7816_CWT) 03913 03914 /*! @brief Set the CWT field to a new value. */ 03915 #define BW_UART_IS7816_CWT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_CWT), v)) 03916 /*@}*/ 03917 03918 /*! 03919 * @name Register UART_IS7816, field WT[7] (W1C) 03920 * 03921 * Indicates that the wait time, the time between the leading edge of a 03922 * character being transmitted and the leading edge of the next response character, has 03923 * exceeded the programmed value. This flag asserts only when C7816[TTYPE] = 0. 03924 * This interrupt is cleared by writing 1. 03925 * 03926 * Values: 03927 * - 0 - Wait time (WT) has not been violated. 03928 * - 1 - Wait time (WT) has been violated. 03929 */ 03930 /*@{*/ 03931 #define BP_UART_IS7816_WT (7U) /*!< Bit position for UART_IS7816_WT. */ 03932 #define BM_UART_IS7816_WT (0x80U) /*!< Bit mask for UART_IS7816_WT. */ 03933 #define BS_UART_IS7816_WT (1U) /*!< Bit field size in bits for UART_IS7816_WT. */ 03934 03935 /*! @brief Read current value of the UART_IS7816_WT field. */ 03936 #define BR_UART_IS7816_WT(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT))) 03937 03938 /*! @brief Format value for bitfield UART_IS7816_WT. */ 03939 #define BF_UART_IS7816_WT(v) ((uint8_t)((uint8_t)(v) << BP_UART_IS7816_WT) & BM_UART_IS7816_WT) 03940 03941 /*! @brief Set the WT field to a new value. */ 03942 #define BW_UART_IS7816_WT(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_UART_IS7816_ADDR(x), BP_UART_IS7816_WT), v)) 03943 /*@}*/ 03944 03945 /******************************************************************************* 03946 * HW_UART_WP7816T0 - UART 7816 Wait Parameter Register 03947 ******************************************************************************/ 03948 03949 /*! 03950 * @brief HW_UART_WP7816T0 - UART 7816 Wait Parameter Register (RW) 03951 * 03952 * Reset value: 0x0AU 03953 * 03954 * The WP7816 register contains constants used in the generation of various wait 03955 * timer counters. To save register space, this register is used differently 03956 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any 03957 * time. This register must be written to only when C7816[ISO_7816E] is not set. 03958 */ 03959 typedef union _hw_uart_wp7816t0 03960 { 03961 uint8_t U; 03962 struct _hw_uart_wp7816t0_bitfields 03963 { 03964 uint8_t WI : 8; /*!< [7:0] Wait Time Integer (C7816[TTYPE] = 0) */ 03965 } B; 03966 } hw_uart_wp7816t0_t; 03967 03968 /*! 03969 * @name Constants and macros for entire UART_WP7816T0 register 03970 */ 03971 /*@{*/ 03972 #define HW_UART_WP7816T0_ADDR(x) ((x) + 0x1BU) 03973 03974 #define HW_UART_WP7816T0(x) (*(__IO hw_uart_wp7816t0_t *) HW_UART_WP7816T0_ADDR(x)) 03975 #define HW_UART_WP7816T0_RD(x) (ADDRESS_READ(hw_uart_wp7816t0_t, HW_UART_WP7816T0_ADDR(x))) 03976 #define HW_UART_WP7816T0_WR(x, v) (ADDRESS_WRITE(hw_uart_wp7816t0_t, HW_UART_WP7816T0_ADDR(x), v)) 03977 #define HW_UART_WP7816T0_SET(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) | (v))) 03978 #define HW_UART_WP7816T0_CLR(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) & ~(v))) 03979 #define HW_UART_WP7816T0_TOG(x, v) (HW_UART_WP7816T0_WR(x, HW_UART_WP7816T0_RD(x) ^ (v))) 03980 /*@}*/ 03981 03982 /* 03983 * Constants & macros for individual UART_WP7816T0 bitfields 03984 */ 03985 03986 /*! 03987 * @name Register UART_WP7816T0, field WI[7:0] (RW) 03988 * 03989 * Used to calculate the value used for the WT counter. It represents a value 03990 * between 1 and 255. The value of zero is not valid. This value is used only when 03991 * C7816[TTYPE] = 0. See Wait time and guard time parameters. 03992 */ 03993 /*@{*/ 03994 #define BP_UART_WP7816T0_WI (0U) /*!< Bit position for UART_WP7816T0_WI. */ 03995 #define BM_UART_WP7816T0_WI (0xFFU) /*!< Bit mask for UART_WP7816T0_WI. */ 03996 #define BS_UART_WP7816T0_WI (8U) /*!< Bit field size in bits for UART_WP7816T0_WI. */ 03997 03998 /*! @brief Read current value of the UART_WP7816T0_WI field. */ 03999 #define BR_UART_WP7816T0_WI(x) (HW_UART_WP7816T0(x).U) 04000 04001 /*! @brief Format value for bitfield UART_WP7816T0_WI. */ 04002 #define BF_UART_WP7816T0_WI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T0_WI) & BM_UART_WP7816T0_WI) 04003 04004 /*! @brief Set the WI field to a new value. */ 04005 #define BW_UART_WP7816T0_WI(x, v) (HW_UART_WP7816T0_WR(x, v)) 04006 /*@}*/ 04007 /******************************************************************************* 04008 * HW_UART_WP7816T1 - UART 7816 Wait Parameter Register 04009 ******************************************************************************/ 04010 04011 /*! 04012 * @brief HW_UART_WP7816T1 - UART 7816 Wait Parameter Register (RW) 04013 * 04014 * Reset value: 0x0AU 04015 * 04016 * The WP7816 register contains constants used in the generation of various wait 04017 * timer counters. To save register space, this register is used differently 04018 * when C7816[TTYPE] = 0 and C7816[TTYPE] = 1. This register may be read at any 04019 * time. This register must be written to only when C7816[ISO_7816E] is not set. 04020 */ 04021 typedef union _hw_uart_wp7816t1 04022 { 04023 uint8_t U; 04024 struct _hw_uart_wp7816t1_bitfields 04025 { 04026 uint8_t BWI : 4; /*!< [3:0] Block Wait Time Integer(C7816[TTYPE] = 1) 04027 * */ 04028 uint8_t CWI : 4; /*!< [7:4] Character Wait Time Integer (C7816[TTYPE] 04029 * = 1) */ 04030 } B; 04031 } hw_uart_wp7816t1_t; 04032 04033 /*! 04034 * @name Constants and macros for entire UART_WP7816T1 register 04035 */ 04036 /*@{*/ 04037 #define HW_UART_WP7816T1_ADDR(x) ((x) + 0x1BU) 04038 04039 #define HW_UART_WP7816T1(x) (*(__IO hw_uart_wp7816t1_t *) HW_UART_WP7816T1_ADDR(x)) 04040 #define HW_UART_WP7816T1_RD(x) (ADDRESS_READ(hw_uart_wp7816t1_t, HW_UART_WP7816T1_ADDR(x))) 04041 #define HW_UART_WP7816T1_WR(x, v) (ADDRESS_WRITE(hw_uart_wp7816t1_t, HW_UART_WP7816T1_ADDR(x), v)) 04042 #define HW_UART_WP7816T1_SET(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) | (v))) 04043 #define HW_UART_WP7816T1_CLR(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) & ~(v))) 04044 #define HW_UART_WP7816T1_TOG(x, v) (HW_UART_WP7816T1_WR(x, HW_UART_WP7816T1_RD(x) ^ (v))) 04045 /*@}*/ 04046 04047 /* 04048 * Constants & macros for individual UART_WP7816T1 bitfields 04049 */ 04050 04051 /*! 04052 * @name Register UART_WP7816T1, field BWI[3:0] (RW) 04053 * 04054 * Used to calculate the value used for the BWT counter. It represent a value 04055 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time 04056 * and guard time parameters . 04057 */ 04058 /*@{*/ 04059 #define BP_UART_WP7816T1_BWI (0U) /*!< Bit position for UART_WP7816T1_BWI. */ 04060 #define BM_UART_WP7816T1_BWI (0x0FU) /*!< Bit mask for UART_WP7816T1_BWI. */ 04061 #define BS_UART_WP7816T1_BWI (4U) /*!< Bit field size in bits for UART_WP7816T1_BWI. */ 04062 04063 /*! @brief Read current value of the UART_WP7816T1_BWI field. */ 04064 #define BR_UART_WP7816T1_BWI(x) (UNION_READ(hw_uart_wp7816t1_t, HW_UART_WP7816T1_ADDR(x), U, B.BWI)) 04065 04066 /*! @brief Format value for bitfield UART_WP7816T1_BWI. */ 04067 #define BF_UART_WP7816T1_BWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_BWI) & BM_UART_WP7816T1_BWI) 04068 04069 /*! @brief Set the BWI field to a new value. */ 04070 #define BW_UART_WP7816T1_BWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_BWI) | BF_UART_WP7816T1_BWI(v))) 04071 /*@}*/ 04072 04073 /*! 04074 * @name Register UART_WP7816T1, field CWI[7:4] (RW) 04075 * 04076 * Used to calculate the value used for the CWT counter. It represents a value 04077 * between 0 and 15. This value is used only when C7816[TTYPE] = 1. See Wait time 04078 * and guard time parameters . 04079 */ 04080 /*@{*/ 04081 #define BP_UART_WP7816T1_CWI (4U) /*!< Bit position for UART_WP7816T1_CWI. */ 04082 #define BM_UART_WP7816T1_CWI (0xF0U) /*!< Bit mask for UART_WP7816T1_CWI. */ 04083 #define BS_UART_WP7816T1_CWI (4U) /*!< Bit field size in bits for UART_WP7816T1_CWI. */ 04084 04085 /*! @brief Read current value of the UART_WP7816T1_CWI field. */ 04086 #define BR_UART_WP7816T1_CWI(x) (UNION_READ(hw_uart_wp7816t1_t, HW_UART_WP7816T1_ADDR(x), U, B.CWI)) 04087 04088 /*! @brief Format value for bitfield UART_WP7816T1_CWI. */ 04089 #define BF_UART_WP7816T1_CWI(v) ((uint8_t)((uint8_t)(v) << BP_UART_WP7816T1_CWI) & BM_UART_WP7816T1_CWI) 04090 04091 /*! @brief Set the CWI field to a new value. */ 04092 #define BW_UART_WP7816T1_CWI(x, v) (HW_UART_WP7816T1_WR(x, (HW_UART_WP7816T1_RD(x) & ~BM_UART_WP7816T1_CWI) | BF_UART_WP7816T1_CWI(v))) 04093 /*@}*/ 04094 04095 /******************************************************************************* 04096 * HW_UART_WN7816 - UART 7816 Wait N Register 04097 ******************************************************************************/ 04098 04099 /*! 04100 * @brief HW_UART_WN7816 - UART 7816 Wait N Register (RW) 04101 * 04102 * Reset value: 0x00U 04103 * 04104 * The WN7816 register contains a parameter that is used in the calculation of 04105 * the guard time counter. This register may be read at any time. This register 04106 * must be written to only when C7816[ISO_7816E] is not set. 04107 */ 04108 typedef union _hw_uart_wn7816 04109 { 04110 uint8_t U; 04111 struct _hw_uart_wn7816_bitfields 04112 { 04113 uint8_t GTN : 8; /*!< [7:0] Guard Band N */ 04114 } B; 04115 } hw_uart_wn7816_t; 04116 04117 /*! 04118 * @name Constants and macros for entire UART_WN7816 register 04119 */ 04120 /*@{*/ 04121 #define HW_UART_WN7816_ADDR(x) ((x) + 0x1CU) 04122 04123 #define HW_UART_WN7816(x) (*(__IO hw_uart_wn7816_t *) HW_UART_WN7816_ADDR(x)) 04124 #define HW_UART_WN7816_RD(x) (ADDRESS_READ(hw_uart_wn7816_t, HW_UART_WN7816_ADDR(x))) 04125 #define HW_UART_WN7816_WR(x, v) (ADDRESS_WRITE(hw_uart_wn7816_t, HW_UART_WN7816_ADDR(x), v)) 04126 #define HW_UART_WN7816_SET(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) | (v))) 04127 #define HW_UART_WN7816_CLR(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) & ~(v))) 04128 #define HW_UART_WN7816_TOG(x, v) (HW_UART_WN7816_WR(x, HW_UART_WN7816_RD(x) ^ (v))) 04129 /*@}*/ 04130 04131 /* 04132 * Constants & macros for individual UART_WN7816 bitfields 04133 */ 04134 04135 /*! 04136 * @name Register UART_WN7816, field GTN[7:0] (RW) 04137 * 04138 * Defines a parameter used in the calculation of GT, CGT, and BGT counters. The 04139 * value represents an integer number between 0 and 255. See Wait time and guard 04140 * time parameters . 04141 */ 04142 /*@{*/ 04143 #define BP_UART_WN7816_GTN (0U) /*!< Bit position for UART_WN7816_GTN. */ 04144 #define BM_UART_WN7816_GTN (0xFFU) /*!< Bit mask for UART_WN7816_GTN. */ 04145 #define BS_UART_WN7816_GTN (8U) /*!< Bit field size in bits for UART_WN7816_GTN. */ 04146 04147 /*! @brief Read current value of the UART_WN7816_GTN field. */ 04148 #define BR_UART_WN7816_GTN(x) (HW_UART_WN7816(x).U) 04149 04150 /*! @brief Format value for bitfield UART_WN7816_GTN. */ 04151 #define BF_UART_WN7816_GTN(v) ((uint8_t)((uint8_t)(v) << BP_UART_WN7816_GTN) & BM_UART_WN7816_GTN) 04152 04153 /*! @brief Set the GTN field to a new value. */ 04154 #define BW_UART_WN7816_GTN(x, v) (HW_UART_WN7816_WR(x, v)) 04155 /*@}*/ 04156 04157 /******************************************************************************* 04158 * HW_UART_WF7816 - UART 7816 Wait FD Register 04159 ******************************************************************************/ 04160 04161 /*! 04162 * @brief HW_UART_WF7816 - UART 7816 Wait FD Register (RW) 04163 * 04164 * Reset value: 0x01U 04165 * 04166 * The WF7816 contains parameters that are used in the generation of various 04167 * counters including GT, CGT, BGT, WT, and BWT. This register may be read at any 04168 * time. This register must be written to only when C7816[ISO_7816E] is not set. 04169 */ 04170 typedef union _hw_uart_wf7816 04171 { 04172 uint8_t U; 04173 struct _hw_uart_wf7816_bitfields 04174 { 04175 uint8_t GTFD : 8; /*!< [7:0] FD Multiplier */ 04176 } B; 04177 } hw_uart_wf7816_t; 04178 04179 /*! 04180 * @name Constants and macros for entire UART_WF7816 register 04181 */ 04182 /*@{*/ 04183 #define HW_UART_WF7816_ADDR(x) ((x) + 0x1DU) 04184 04185 #define HW_UART_WF7816(x) (*(__IO hw_uart_wf7816_t *) HW_UART_WF7816_ADDR(x)) 04186 #define HW_UART_WF7816_RD(x) (ADDRESS_READ(hw_uart_wf7816_t, HW_UART_WF7816_ADDR(x))) 04187 #define HW_UART_WF7816_WR(x, v) (ADDRESS_WRITE(hw_uart_wf7816_t, HW_UART_WF7816_ADDR(x), v)) 04188 #define HW_UART_WF7816_SET(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) | (v))) 04189 #define HW_UART_WF7816_CLR(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) & ~(v))) 04190 #define HW_UART_WF7816_TOG(x, v) (HW_UART_WF7816_WR(x, HW_UART_WF7816_RD(x) ^ (v))) 04191 /*@}*/ 04192 04193 /* 04194 * Constants & macros for individual UART_WF7816 bitfields 04195 */ 04196 04197 /*! 04198 * @name Register UART_WF7816, field GTFD[7:0] (RW) 04199 * 04200 * Used as another multiplier in the calculation of WT and BWT. This value 04201 * represents a number between 1 and 255. The value of 0 is invalid. This value is not 04202 * used in baud rate generation. See Wait time and guard time parameters and 04203 * Baud rate generation . 04204 */ 04205 /*@{*/ 04206 #define BP_UART_WF7816_GTFD (0U) /*!< Bit position for UART_WF7816_GTFD. */ 04207 #define BM_UART_WF7816_GTFD (0xFFU) /*!< Bit mask for UART_WF7816_GTFD. */ 04208 #define BS_UART_WF7816_GTFD (8U) /*!< Bit field size in bits for UART_WF7816_GTFD. */ 04209 04210 /*! @brief Read current value of the UART_WF7816_GTFD field. */ 04211 #define BR_UART_WF7816_GTFD(x) (HW_UART_WF7816(x).U) 04212 04213 /*! @brief Format value for bitfield UART_WF7816_GTFD. */ 04214 #define BF_UART_WF7816_GTFD(v) ((uint8_t)((uint8_t)(v) << BP_UART_WF7816_GTFD) & BM_UART_WF7816_GTFD) 04215 04216 /*! @brief Set the GTFD field to a new value. */ 04217 #define BW_UART_WF7816_GTFD(x, v) (HW_UART_WF7816_WR(x, v)) 04218 /*@}*/ 04219 04220 /******************************************************************************* 04221 * HW_UART_ET7816 - UART 7816 Error Threshold Register 04222 ******************************************************************************/ 04223 04224 /*! 04225 * @brief HW_UART_ET7816 - UART 7816 Error Threshold Register (RW) 04226 * 04227 * Reset value: 0x00U 04228 * 04229 * The ET7816 register contains fields that determine the number of NACKs that 04230 * must be received or transmitted before the host processor is notified. This 04231 * register may be read at anytime. This register must be written to only when 04232 * C7816[ISO_7816E] is not set. 04233 */ 04234 typedef union _hw_uart_et7816 04235 { 04236 uint8_t U; 04237 struct _hw_uart_et7816_bitfields 04238 { 04239 uint8_t RXTHRESHOLD : 4; /*!< [3:0] Receive NACK Threshold */ 04240 uint8_t TXTHRESHOLD : 4; /*!< [7:4] Transmit NACK Threshold */ 04241 } B; 04242 } hw_uart_et7816_t; 04243 04244 /*! 04245 * @name Constants and macros for entire UART_ET7816 register 04246 */ 04247 /*@{*/ 04248 #define HW_UART_ET7816_ADDR(x) ((x) + 0x1EU) 04249 04250 #define HW_UART_ET7816(x) (*(__IO hw_uart_et7816_t *) HW_UART_ET7816_ADDR(x)) 04251 #define HW_UART_ET7816_RD(x) (ADDRESS_READ(hw_uart_et7816_t, HW_UART_ET7816_ADDR(x))) 04252 #define HW_UART_ET7816_WR(x, v) (ADDRESS_WRITE(hw_uart_et7816_t, HW_UART_ET7816_ADDR(x), v)) 04253 #define HW_UART_ET7816_SET(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) | (v))) 04254 #define HW_UART_ET7816_CLR(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) & ~(v))) 04255 #define HW_UART_ET7816_TOG(x, v) (HW_UART_ET7816_WR(x, HW_UART_ET7816_RD(x) ^ (v))) 04256 /*@}*/ 04257 04258 /* 04259 * Constants & macros for individual UART_ET7816 bitfields 04260 */ 04261 04262 /*! 04263 * @name Register UART_ET7816, field RXTHRESHOLD[3:0] (RW) 04264 * 04265 * The value written to this field indicates the maximum number of consecutive 04266 * NACKs generated as a result of a parity error or receiver buffer overruns 04267 * before the host processor is notified. After the counter exceeds that value in the 04268 * field, the IS7816[RXT] is asserted. This field is meaningful only when 04269 * C7816[TTYPE] = 0. The value read from this field represents the number of consecutive 04270 * NACKs that have been transmitted since the last successful reception. This 04271 * counter saturates at 4'hF and does not wrap around. Regardless of the number of 04272 * NACKs sent, the UART continues to receive valid packets indefinitely. For 04273 * additional information, see IS7816[RXT] field description. 04274 */ 04275 /*@{*/ 04276 #define BP_UART_ET7816_RXTHRESHOLD (0U) /*!< Bit position for UART_ET7816_RXTHRESHOLD. */ 04277 #define BM_UART_ET7816_RXTHRESHOLD (0x0FU) /*!< Bit mask for UART_ET7816_RXTHRESHOLD. */ 04278 #define BS_UART_ET7816_RXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_RXTHRESHOLD. */ 04279 04280 /*! @brief Read current value of the UART_ET7816_RXTHRESHOLD field. */ 04281 #define BR_UART_ET7816_RXTHRESHOLD(x) (UNION_READ(hw_uart_et7816_t, HW_UART_ET7816_ADDR(x), U, B.RXTHRESHOLD)) 04282 04283 /*! @brief Format value for bitfield UART_ET7816_RXTHRESHOLD. */ 04284 #define BF_UART_ET7816_RXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_RXTHRESHOLD) & BM_UART_ET7816_RXTHRESHOLD) 04285 04286 /*! @brief Set the RXTHRESHOLD field to a new value. */ 04287 #define BW_UART_ET7816_RXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_RXTHRESHOLD) | BF_UART_ET7816_RXTHRESHOLD(v))) 04288 /*@}*/ 04289 04290 /*! 04291 * @name Register UART_ET7816, field TXTHRESHOLD[7:4] (RW) 04292 * 04293 * The value written to this field indicates the maximum number of failed 04294 * attempts (NACKs) a transmitted character can have before the host processor is 04295 * notified. This field is meaningful only when C7816[TTYPE] = 0 and C7816[ANACK] = 1. 04296 * The value read from this field represents the number of consecutive NACKs 04297 * that have been received since the last successful transmission. This counter 04298 * saturates at 4'hF and does not wrap around. Regardless of how many NACKs that are 04299 * received, the UART continues to retransmit indefinitely. This flag only 04300 * asserts when C7816[TTYPE] = 0. For additional information see the IS7816[TXT] field 04301 * description. 04302 * 04303 * Values: 04304 * - 0 - TXT asserts on the first NACK that is received. 04305 * - 1 - TXT asserts on the second NACK that is received. 04306 */ 04307 /*@{*/ 04308 #define BP_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit position for UART_ET7816_TXTHRESHOLD. */ 04309 #define BM_UART_ET7816_TXTHRESHOLD (0xF0U) /*!< Bit mask for UART_ET7816_TXTHRESHOLD. */ 04310 #define BS_UART_ET7816_TXTHRESHOLD (4U) /*!< Bit field size in bits for UART_ET7816_TXTHRESHOLD. */ 04311 04312 /*! @brief Read current value of the UART_ET7816_TXTHRESHOLD field. */ 04313 #define BR_UART_ET7816_TXTHRESHOLD(x) (UNION_READ(hw_uart_et7816_t, HW_UART_ET7816_ADDR(x), U, B.TXTHRESHOLD)) 04314 04315 /*! @brief Format value for bitfield UART_ET7816_TXTHRESHOLD. */ 04316 #define BF_UART_ET7816_TXTHRESHOLD(v) ((uint8_t)((uint8_t)(v) << BP_UART_ET7816_TXTHRESHOLD) & BM_UART_ET7816_TXTHRESHOLD) 04317 04318 /*! @brief Set the TXTHRESHOLD field to a new value. */ 04319 #define BW_UART_ET7816_TXTHRESHOLD(x, v) (HW_UART_ET7816_WR(x, (HW_UART_ET7816_RD(x) & ~BM_UART_ET7816_TXTHRESHOLD) | BF_UART_ET7816_TXTHRESHOLD(v))) 04320 /*@}*/ 04321 04322 /******************************************************************************* 04323 * HW_UART_TL7816 - UART 7816 Transmit Length Register 04324 ******************************************************************************/ 04325 04326 /*! 04327 * @brief HW_UART_TL7816 - UART 7816 Transmit Length Register (RW) 04328 * 04329 * Reset value: 0x00U 04330 * 04331 * The TL7816 register is used to indicate the number of characters contained in 04332 * the block being transmitted. This register is used only when C7816[TTYPE] = 04333 * 1. This register may be read at anytime. This register must be written only 04334 * when C2[TE] is not enabled. 04335 */ 04336 typedef union _hw_uart_tl7816 04337 { 04338 uint8_t U; 04339 struct _hw_uart_tl7816_bitfields 04340 { 04341 uint8_t TLEN : 8; /*!< [7:0] Transmit Length */ 04342 } B; 04343 } hw_uart_tl7816_t; 04344 04345 /*! 04346 * @name Constants and macros for entire UART_TL7816 register 04347 */ 04348 /*@{*/ 04349 #define HW_UART_TL7816_ADDR(x) ((x) + 0x1FU) 04350 04351 #define HW_UART_TL7816(x) (*(__IO hw_uart_tl7816_t *) HW_UART_TL7816_ADDR(x)) 04352 #define HW_UART_TL7816_RD(x) (ADDRESS_READ(hw_uart_tl7816_t, HW_UART_TL7816_ADDR(x))) 04353 #define HW_UART_TL7816_WR(x, v) (ADDRESS_WRITE(hw_uart_tl7816_t, HW_UART_TL7816_ADDR(x), v)) 04354 #define HW_UART_TL7816_SET(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) | (v))) 04355 #define HW_UART_TL7816_CLR(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) & ~(v))) 04356 #define HW_UART_TL7816_TOG(x, v) (HW_UART_TL7816_WR(x, HW_UART_TL7816_RD(x) ^ (v))) 04357 /*@}*/ 04358 04359 /* 04360 * Constants & macros for individual UART_TL7816 bitfields 04361 */ 04362 04363 /*! 04364 * @name Register UART_TL7816, field TLEN[7:0] (RW) 04365 * 04366 * This value plus four indicates the number of characters contained in the 04367 * block being transmitted. This register is automatically decremented by 1 for each 04368 * character in the information field portion of the block. Additionally, this 04369 * register is automatically decremented by 1 for the first character of a CRC in 04370 * the epilogue field. Therefore, this register must be programmed with the number 04371 * of bytes in the data packet if an LRC is being transmitted, and the number of 04372 * bytes + 1 if a CRC is being transmitted. This register is not decremented for 04373 * characters that are assumed to be part of the Prologue field, that is, the 04374 * first three characters transmitted in a block, or the LRC or last CRC character 04375 * in the Epilogue field, that is, the last character transmitted. This field 04376 * must be programed or adjusted only when C2[TE] is cleared. 04377 */ 04378 /*@{*/ 04379 #define BP_UART_TL7816_TLEN (0U) /*!< Bit position for UART_TL7816_TLEN. */ 04380 #define BM_UART_TL7816_TLEN (0xFFU) /*!< Bit mask for UART_TL7816_TLEN. */ 04381 #define BS_UART_TL7816_TLEN (8U) /*!< Bit field size in bits for UART_TL7816_TLEN. */ 04382 04383 /*! @brief Read current value of the UART_TL7816_TLEN field. */ 04384 #define BR_UART_TL7816_TLEN(x) (HW_UART_TL7816(x).U) 04385 04386 /*! @brief Format value for bitfield UART_TL7816_TLEN. */ 04387 #define BF_UART_TL7816_TLEN(v) ((uint8_t)((uint8_t)(v) << BP_UART_TL7816_TLEN) & BM_UART_TL7816_TLEN) 04388 04389 /*! @brief Set the TLEN field to a new value. */ 04390 #define BW_UART_TL7816_TLEN(x, v) (HW_UART_TL7816_WR(x, v)) 04391 /*@}*/ 04392 04393 /* 04394 ** Start of section using anonymous unions 04395 */ 04396 04397 #if defined(__ARMCC_VERSION) 04398 #pragma push 04399 #pragma anon_unions 04400 #elif defined(__CWCC__) 04401 #pragma push 04402 #pragma cpp_extensions on 04403 #elif defined(__GNUC__) 04404 /* anonymous unions are enabled by default */ 04405 #elif defined(__IAR_SYSTEMS_ICC__) 04406 #pragma language=extended 04407 #else 04408 #error Not supported compiler type 04409 #endif 04410 04411 /******************************************************************************* 04412 * hw_uart_t - module struct 04413 ******************************************************************************/ 04414 /*! 04415 * @brief All UART module registers. 04416 */ 04417 #pragma pack(1) 04418 typedef struct _hw_uart 04419 { 04420 __IO hw_uart_bdh_t BDH ; /*!< [0x0] UART Baud Rate Registers: High */ 04421 __IO hw_uart_bdl_t BDL ; /*!< [0x1] UART Baud Rate Registers: Low */ 04422 __IO hw_uart_c1_t C1 ; /*!< [0x2] UART Control Register 1 */ 04423 __IO hw_uart_c2_t C2 ; /*!< [0x3] UART Control Register 2 */ 04424 __I hw_uart_s1_t S1 ; /*!< [0x4] UART Status Register 1 */ 04425 __IO hw_uart_s2_t S2 ; /*!< [0x5] UART Status Register 2 */ 04426 __IO hw_uart_c3_t C3 ; /*!< [0x6] UART Control Register 3 */ 04427 __IO hw_uart_d_t D ; /*!< [0x7] UART Data Register */ 04428 __IO hw_uart_ma1_t MA1 ; /*!< [0x8] UART Match Address Registers 1 */ 04429 __IO hw_uart_ma2_t MA2 ; /*!< [0x9] UART Match Address Registers 2 */ 04430 __IO hw_uart_c4_t C4 ; /*!< [0xA] UART Control Register 4 */ 04431 __IO hw_uart_c5_t C5 ; /*!< [0xB] UART Control Register 5 */ 04432 __I hw_uart_ed_t ED ; /*!< [0xC] UART Extended Data Register */ 04433 __IO hw_uart_modem_t MODEM ; /*!< [0xD] UART Modem Register */ 04434 __IO hw_uart_ir_t IR ; /*!< [0xE] UART Infrared Register */ 04435 uint8_t _reserved0[1]; 04436 __IO hw_uart_pfifo_t PFIFO ; /*!< [0x10] UART FIFO Parameters */ 04437 __IO hw_uart_cfifo_t CFIFO ; /*!< [0x11] UART FIFO Control Register */ 04438 __IO hw_uart_sfifo_t SFIFO ; /*!< [0x12] UART FIFO Status Register */ 04439 __IO hw_uart_twfifo_t TWFIFO ; /*!< [0x13] UART FIFO Transmit Watermark */ 04440 __I hw_uart_tcfifo_t TCFIFO ; /*!< [0x14] UART FIFO Transmit Count */ 04441 __IO hw_uart_rwfifo_t RWFIFO ; /*!< [0x15] UART FIFO Receive Watermark */ 04442 __I hw_uart_rcfifo_t RCFIFO ; /*!< [0x16] UART FIFO Receive Count */ 04443 uint8_t _reserved1[1]; 04444 __IO hw_uart_c7816_t C7816 ; /*!< [0x18] UART 7816 Control Register */ 04445 __IO hw_uart_ie7816_t IE7816 ; /*!< [0x19] UART 7816 Interrupt Enable Register */ 04446 __IO hw_uart_is7816_t IS7816 ; /*!< [0x1A] UART 7816 Interrupt Status Register */ 04447 union { 04448 __IO hw_uart_wp7816t0_t WP7816T0 ; /*!< [0x1B] UART 7816 Wait Parameter Register */ 04449 __IO hw_uart_wp7816t1_t WP7816T1 ; /*!< [0x1B] UART 7816 Wait Parameter Register */ 04450 }; 04451 __IO hw_uart_wn7816_t WN7816 ; /*!< [0x1C] UART 7816 Wait N Register */ 04452 __IO hw_uart_wf7816_t WF7816 ; /*!< [0x1D] UART 7816 Wait FD Register */ 04453 __IO hw_uart_et7816_t ET7816 ; /*!< [0x1E] UART 7816 Error Threshold Register */ 04454 __IO hw_uart_tl7816_t TL7816 ; /*!< [0x1F] UART 7816 Transmit Length Register */ 04455 } hw_uart_t; 04456 #pragma pack() 04457 04458 /*! @brief Macro to access all UART registers. */ 04459 /*! @param x UART module instance base address. */ 04460 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct, 04461 * use the '&' operator, like <code>&HW_UART(UART0_BASE)</code>. */ 04462 #define HW_UART(x) (*(hw_uart_t *)(x)) 04463 04464 /* 04465 ** End of section using anonymous unions 04466 */ 04467 04468 #if defined(__ARMCC_VERSION) 04469 #pragma pop 04470 #elif defined(__CWCC__) 04471 #pragma pop 04472 #elif defined(__GNUC__) 04473 /* leave anonymous unions enabled */ 04474 #elif defined(__IAR_SYSTEMS_ICC__) 04475 #pragma language=default 04476 #else 04477 #error Not supported compiler type 04478 #endif 04479 04480 #endif /* __HW_UART_REGISTERS_H__ */ 04481 /* EOF */
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