MK64F12_smc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_SMC_REGISTERS_H__
00088 #define __HW_SMC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 SMC
00095  *
00096  * System Mode Controller
00097  *
00098  * Registers defined in this header file:
00099  * - HW_SMC_PMPROT - Power Mode Protection register
00100  * - HW_SMC_PMCTRL - Power Mode Control register
00101  * - HW_SMC_VLLSCTRL - VLLS Control register
00102  * - HW_SMC_PMSTAT - Power Mode Status register
00103  *
00104  * - hw_smc_t - Struct containing all module registers.
00105  */
00106 
00107 #define HW_SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
00108 
00109 /*******************************************************************************
00110  * HW_SMC_PMPROT - Power Mode Protection register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
00115  *
00116  * Reset value: 0x00U
00117  *
00118  * This register provides protection for entry into any low-power run or stop
00119  * mode. The enabling of the low-power run or stop mode occurs by configuring the
00120  * Power Mode Control register (PMCTRL). The PMPROT register can be written only
00121  * once after any system reset. If the MCU is configured for a disallowed or
00122  * reserved power mode, the MCU remains in its current power mode. For example, if the
00123  * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
00124  * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
00125  * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
00126  * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
00127  * that do not trigger Chip Reset not VLLS. See the Reset section details for more
00128  * information.
00129  */
00130 typedef union _hw_smc_pmprot
00131 {
00132     uint8_t U;
00133     struct _hw_smc_pmprot_bitfields
00134     {
00135         uint8_t RESERVED0 : 1;         /*!< [0]  */
00136         uint8_t AVLLS : 1;             /*!< [1] Allow Very-Low-Leakage Stop Mode */
00137         uint8_t RESERVED1 : 1;         /*!< [2]  */
00138         uint8_t ALLS : 1;              /*!< [3] Allow Low-Leakage Stop Mode */
00139         uint8_t RESERVED2 : 1;         /*!< [4]  */
00140         uint8_t AVLP : 1;              /*!< [5] Allow Very-Low-Power Modes */
00141         uint8_t RESERVED3 : 2;         /*!< [7:6]  */
00142     } B;
00143 } hw_smc_pmprot_t;
00144 
00145 /*!
00146  * @name Constants and macros for entire SMC_PMPROT register
00147  */
00148 /*@{*/
00149 #define HW_SMC_PMPROT_ADDR(x)    ((x) + 0x0U)
00150 
00151 #define HW_SMC_PMPROT(x)         (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR(x))
00152 #define HW_SMC_PMPROT_RD(x)      (ADDRESS_READ(hw_smc_pmprot_t, HW_SMC_PMPROT_ADDR(x)))
00153 #define HW_SMC_PMPROT_WR(x, v)   (ADDRESS_WRITE(hw_smc_pmprot_t, HW_SMC_PMPROT_ADDR(x), v))
00154 #define HW_SMC_PMPROT_SET(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) |  (v)))
00155 #define HW_SMC_PMPROT_CLR(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) & ~(v)))
00156 #define HW_SMC_PMPROT_TOG(x, v)  (HW_SMC_PMPROT_WR(x, HW_SMC_PMPROT_RD(x) ^  (v)))
00157 /*@}*/
00158 
00159 /*
00160  * Constants & macros for individual SMC_PMPROT bitfields
00161  */
00162 
00163 /*!
00164  * @name Register SMC_PMPROT, field AVLLS[1] (RW)
00165  *
00166  * Provided the appropriate control bits are set up in PMCTRL, this write once
00167  * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
00168  *
00169  * Values:
00170  * - 0 - Any VLLSx mode is not allowed
00171  * - 1 - Any VLLSx mode is allowed
00172  */
00173 /*@{*/
00174 #define BP_SMC_PMPROT_AVLLS  (1U)          /*!< Bit position for SMC_PMPROT_AVLLS. */
00175 #define BM_SMC_PMPROT_AVLLS  (0x02U)       /*!< Bit mask for SMC_PMPROT_AVLLS. */
00176 #define BS_SMC_PMPROT_AVLLS  (1U)          /*!< Bit field size in bits for SMC_PMPROT_AVLLS. */
00177 
00178 /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
00179 #define BR_SMC_PMPROT_AVLLS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS)))
00180 
00181 /*! @brief Format value for bitfield SMC_PMPROT_AVLLS. */
00182 #define BF_SMC_PMPROT_AVLLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLLS) & BM_SMC_PMPROT_AVLLS)
00183 
00184 /*! @brief Set the AVLLS field to a new value. */
00185 #define BW_SMC_PMPROT_AVLLS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLLS), v))
00186 /*@}*/
00187 
00188 /*!
00189  * @name Register SMC_PMPROT, field ALLS[3] (RW)
00190  *
00191  * Provided the appropriate control bits are set up in PMCTRL, this write-once
00192  * field allows the MCU to enter any low-leakage stop mode (LLS).
00193  *
00194  * Values:
00195  * - 0 - LLS is not allowed
00196  * - 1 - LLS is allowed
00197  */
00198 /*@{*/
00199 #define BP_SMC_PMPROT_ALLS   (3U)          /*!< Bit position for SMC_PMPROT_ALLS. */
00200 #define BM_SMC_PMPROT_ALLS   (0x08U)       /*!< Bit mask for SMC_PMPROT_ALLS. */
00201 #define BS_SMC_PMPROT_ALLS   (1U)          /*!< Bit field size in bits for SMC_PMPROT_ALLS. */
00202 
00203 /*! @brief Read current value of the SMC_PMPROT_ALLS field. */
00204 #define BR_SMC_PMPROT_ALLS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS)))
00205 
00206 /*! @brief Format value for bitfield SMC_PMPROT_ALLS. */
00207 #define BF_SMC_PMPROT_ALLS(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_ALLS) & BM_SMC_PMPROT_ALLS)
00208 
00209 /*! @brief Set the ALLS field to a new value. */
00210 #define BW_SMC_PMPROT_ALLS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_ALLS), v))
00211 /*@}*/
00212 
00213 /*!
00214  * @name Register SMC_PMPROT, field AVLP[5] (RW)
00215  *
00216  * Provided the appropriate control bits are set up in PMCTRL, this write-once
00217  * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
00218  *
00219  * Values:
00220  * - 0 - VLPR, VLPW, and VLPS are not allowed.
00221  * - 1 - VLPR, VLPW, and VLPS are allowed.
00222  */
00223 /*@{*/
00224 #define BP_SMC_PMPROT_AVLP   (5U)          /*!< Bit position for SMC_PMPROT_AVLP. */
00225 #define BM_SMC_PMPROT_AVLP   (0x20U)       /*!< Bit mask for SMC_PMPROT_AVLP. */
00226 #define BS_SMC_PMPROT_AVLP   (1U)          /*!< Bit field size in bits for SMC_PMPROT_AVLP. */
00227 
00228 /*! @brief Read current value of the SMC_PMPROT_AVLP field. */
00229 #define BR_SMC_PMPROT_AVLP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP)))
00230 
00231 /*! @brief Format value for bitfield SMC_PMPROT_AVLP. */
00232 #define BF_SMC_PMPROT_AVLP(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMPROT_AVLP) & BM_SMC_PMPROT_AVLP)
00233 
00234 /*! @brief Set the AVLP field to a new value. */
00235 #define BW_SMC_PMPROT_AVLP(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMPROT_ADDR(x), BP_SMC_PMPROT_AVLP), v))
00236 /*@}*/
00237 
00238 /*******************************************************************************
00239  * HW_SMC_PMCTRL - Power Mode Control register
00240  ******************************************************************************/
00241 
00242 /*!
00243  * @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
00244  *
00245  * Reset value: 0x00U
00246  *
00247  * The PMCTRL register controls entry into low-power Run and Stop modes,
00248  * provided that the selected power mode is allowed via an appropriate setting of the
00249  * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
00250  * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
00251  * that do not trigger Chip POR not VLLS. See the Reset section details for more
00252  * information.
00253  */
00254 typedef union _hw_smc_pmctrl
00255 {
00256     uint8_t U;
00257     struct _hw_smc_pmctrl_bitfields
00258     {
00259         uint8_t STOPM : 3;             /*!< [2:0] Stop Mode Control */
00260         uint8_t STOPA : 1;             /*!< [3] Stop Aborted */
00261         uint8_t RESERVED0 : 1;         /*!< [4]  */
00262         uint8_t RUNM : 2;              /*!< [6:5] Run Mode Control */
00263         uint8_t LPWUI : 1;             /*!< [7] Low-Power Wake Up On Interrupt */
00264     } B;
00265 } hw_smc_pmctrl_t;
00266 
00267 /*!
00268  * @name Constants and macros for entire SMC_PMCTRL register
00269  */
00270 /*@{*/
00271 #define HW_SMC_PMCTRL_ADDR(x)    ((x) + 0x1U)
00272 
00273 #define HW_SMC_PMCTRL(x)         (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR(x))
00274 #define HW_SMC_PMCTRL_RD(x)      (ADDRESS_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x)))
00275 #define HW_SMC_PMCTRL_WR(x, v)   (ADDRESS_WRITE(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), v))
00276 #define HW_SMC_PMCTRL_SET(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) |  (v)))
00277 #define HW_SMC_PMCTRL_CLR(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) & ~(v)))
00278 #define HW_SMC_PMCTRL_TOG(x, v)  (HW_SMC_PMCTRL_WR(x, HW_SMC_PMCTRL_RD(x) ^  (v)))
00279 /*@}*/
00280 
00281 /*
00282  * Constants & macros for individual SMC_PMCTRL bitfields
00283  */
00284 
00285 /*!
00286  * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
00287  *
00288  * When written, controls entry into the selected stop mode when Sleep-Now or
00289  * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
00290  * blocked if the protection level has not been enabled using the PMPROT register.
00291  * After any system reset, this field is cleared by hardware on any successful write
00292  * to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
00293  * register is used to further select the particular VLLS submode which will be
00294  * entered.
00295  *
00296  * Values:
00297  * - 000 - Normal Stop (STOP)
00298  * - 001 - Reserved
00299  * - 010 - Very-Low-Power Stop (VLPS)
00300  * - 011 - Low-Leakage Stop (LLS)
00301  * - 100 - Very-Low-Leakage Stop (VLLSx)
00302  * - 101 - Reserved
00303  * - 110 - Reseved
00304  * - 111 - Reserved
00305  */
00306 /*@{*/
00307 #define BP_SMC_PMCTRL_STOPM  (0U)          /*!< Bit position for SMC_PMCTRL_STOPM. */
00308 #define BM_SMC_PMCTRL_STOPM  (0x07U)       /*!< Bit mask for SMC_PMCTRL_STOPM. */
00309 #define BS_SMC_PMCTRL_STOPM  (3U)          /*!< Bit field size in bits for SMC_PMCTRL_STOPM. */
00310 
00311 /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
00312 #define BR_SMC_PMCTRL_STOPM(x) (UNION_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), U, B.STOPM))
00313 
00314 /*! @brief Format value for bitfield SMC_PMCTRL_STOPM. */
00315 #define BF_SMC_PMCTRL_STOPM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_STOPM) & BM_SMC_PMCTRL_STOPM)
00316 
00317 /*! @brief Set the STOPM field to a new value. */
00318 #define BW_SMC_PMCTRL_STOPM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
00319 /*@}*/
00320 
00321 /*!
00322  * @name Register SMC_PMCTRL, field STOPA[3] (RO)
00323  *
00324  * When set, this read-only status bit indicates an interrupt or reset occured
00325  * during the previous stop mode entry sequence, preventing the system from
00326  * entering that mode. This field is cleared by hardware at the beginning of any stop
00327  * mode entry sequence and is set if the sequence was aborted.
00328  *
00329  * Values:
00330  * - 0 - The previous stop mode entry was successsful.
00331  * - 1 - The previous stop mode entry was aborted.
00332  */
00333 /*@{*/
00334 #define BP_SMC_PMCTRL_STOPA  (3U)          /*!< Bit position for SMC_PMCTRL_STOPA. */
00335 #define BM_SMC_PMCTRL_STOPA  (0x08U)       /*!< Bit mask for SMC_PMCTRL_STOPA. */
00336 #define BS_SMC_PMCTRL_STOPA  (1U)          /*!< Bit field size in bits for SMC_PMCTRL_STOPA. */
00337 
00338 /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
00339 #define BR_SMC_PMCTRL_STOPA(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_STOPA)))
00340 /*@}*/
00341 
00342 /*!
00343  * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
00344  *
00345  * When written, causes entry into the selected run mode. Writes to this field
00346  * are blocked if the protection level has not been enabled using the PMPROT
00347  * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
00348  * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
00349  *
00350  * Values:
00351  * - 00 - Normal Run mode (RUN)
00352  * - 01 - Reserved
00353  * - 10 - Very-Low-Power Run mode (VLPR)
00354  * - 11 - Reserved
00355  */
00356 /*@{*/
00357 #define BP_SMC_PMCTRL_RUNM   (5U)          /*!< Bit position for SMC_PMCTRL_RUNM. */
00358 #define BM_SMC_PMCTRL_RUNM   (0x60U)       /*!< Bit mask for SMC_PMCTRL_RUNM. */
00359 #define BS_SMC_PMCTRL_RUNM   (2U)          /*!< Bit field size in bits for SMC_PMCTRL_RUNM. */
00360 
00361 /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
00362 #define BR_SMC_PMCTRL_RUNM(x) (UNION_READ(hw_smc_pmctrl_t, HW_SMC_PMCTRL_ADDR(x), U, B.RUNM))
00363 
00364 /*! @brief Format value for bitfield SMC_PMCTRL_RUNM. */
00365 #define BF_SMC_PMCTRL_RUNM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_RUNM) & BM_SMC_PMCTRL_RUNM)
00366 
00367 /*! @brief Set the RUNM field to a new value. */
00368 #define BW_SMC_PMCTRL_RUNM(x, v) (HW_SMC_PMCTRL_WR(x, (HW_SMC_PMCTRL_RD(x) & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
00369 /*@}*/
00370 
00371 /*!
00372  * @name Register SMC_PMCTRL, field LPWUI[7] (RW)
00373  *
00374  * Causes the SMC to exit to normal RUN mode when any active MCU interrupt
00375  * occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
00376  * from RUN mode, the SMC will always exit back to normal RUN mode regardless of
00377  * the LPWUI setting. LPWUI must be modified only while the system is in RUN
00378  * mode, that is, when PMSTAT=RUN.
00379  *
00380  * Values:
00381  * - 0 - The system remains in a VLP mode on an interrupt
00382  * - 1 - The system exits to Normal RUN mode on an interrupt
00383  */
00384 /*@{*/
00385 #define BP_SMC_PMCTRL_LPWUI  (7U)          /*!< Bit position for SMC_PMCTRL_LPWUI. */
00386 #define BM_SMC_PMCTRL_LPWUI  (0x80U)       /*!< Bit mask for SMC_PMCTRL_LPWUI. */
00387 #define BS_SMC_PMCTRL_LPWUI  (1U)          /*!< Bit field size in bits for SMC_PMCTRL_LPWUI. */
00388 
00389 /*! @brief Read current value of the SMC_PMCTRL_LPWUI field. */
00390 #define BR_SMC_PMCTRL_LPWUI(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI)))
00391 
00392 /*! @brief Format value for bitfield SMC_PMCTRL_LPWUI. */
00393 #define BF_SMC_PMCTRL_LPWUI(v) ((uint8_t)((uint8_t)(v) << BP_SMC_PMCTRL_LPWUI) & BM_SMC_PMCTRL_LPWUI)
00394 
00395 /*! @brief Set the LPWUI field to a new value. */
00396 #define BW_SMC_PMCTRL_LPWUI(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_PMCTRL_ADDR(x), BP_SMC_PMCTRL_LPWUI), v))
00397 /*@}*/
00398 
00399 /*******************************************************************************
00400  * HW_SMC_VLLSCTRL - VLLS Control register
00401  ******************************************************************************/
00402 
00403 /*!
00404  * @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
00405  *
00406  * Reset value: 0x03U
00407  *
00408  * The VLLSCTRL register controls features related to VLLS modes. This register
00409  * is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
00410  * VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
00411  * the Reset section details for more information.
00412  */
00413 typedef union _hw_smc_vllsctrl
00414 {
00415     uint8_t U;
00416     struct _hw_smc_vllsctrl_bitfields
00417     {
00418         uint8_t VLLSM : 3;             /*!< [2:0] VLLS Mode Control */
00419         uint8_t RESERVED0 : 2;         /*!< [4:3]  */
00420         uint8_t PORPO : 1;             /*!< [5] POR Power Option */
00421         uint8_t RESERVED1 : 2;         /*!< [7:6]  */
00422     } B;
00423 } hw_smc_vllsctrl_t;
00424 
00425 /*!
00426  * @name Constants and macros for entire SMC_VLLSCTRL register
00427  */
00428 /*@{*/
00429 #define HW_SMC_VLLSCTRL_ADDR(x)  ((x) + 0x2U)
00430 
00431 #define HW_SMC_VLLSCTRL(x)       (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR(x))
00432 #define HW_SMC_VLLSCTRL_RD(x)    (ADDRESS_READ(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x)))
00433 #define HW_SMC_VLLSCTRL_WR(x, v) (ADDRESS_WRITE(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x), v))
00434 #define HW_SMC_VLLSCTRL_SET(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) |  (v)))
00435 #define HW_SMC_VLLSCTRL_CLR(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) & ~(v)))
00436 #define HW_SMC_VLLSCTRL_TOG(x, v) (HW_SMC_VLLSCTRL_WR(x, HW_SMC_VLLSCTRL_RD(x) ^  (v)))
00437 /*@}*/
00438 
00439 /*
00440  * Constants & macros for individual SMC_VLLSCTRL bitfields
00441  */
00442 
00443 /*!
00444  * @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
00445  *
00446  * Controls which VLLS sub-mode to enter if STOPM=VLLS.
00447  *
00448  * Values:
00449  * - 000 - VLLS0
00450  * - 001 - VLLS1
00451  * - 010 - VLLS2
00452  * - 011 - VLLS3
00453  * - 100 - Reserved
00454  * - 101 - Reserved
00455  * - 110 - Reserved
00456  * - 111 - Reserved
00457  */
00458 /*@{*/
00459 #define BP_SMC_VLLSCTRL_VLLSM (0U)         /*!< Bit position for SMC_VLLSCTRL_VLLSM. */
00460 #define BM_SMC_VLLSCTRL_VLLSM (0x07U)      /*!< Bit mask for SMC_VLLSCTRL_VLLSM. */
00461 #define BS_SMC_VLLSCTRL_VLLSM (3U)         /*!< Bit field size in bits for SMC_VLLSCTRL_VLLSM. */
00462 
00463 /*! @brief Read current value of the SMC_VLLSCTRL_VLLSM field. */
00464 #define BR_SMC_VLLSCTRL_VLLSM(x) (UNION_READ(hw_smc_vllsctrl_t, HW_SMC_VLLSCTRL_ADDR(x), U, B.VLLSM))
00465 
00466 /*! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM. */
00467 #define BF_SMC_VLLSCTRL_VLLSM(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_VLLSM) & BM_SMC_VLLSCTRL_VLLSM)
00468 
00469 /*! @brief Set the VLLSM field to a new value. */
00470 #define BW_SMC_VLLSCTRL_VLLSM(x, v) (HW_SMC_VLLSCTRL_WR(x, (HW_SMC_VLLSCTRL_RD(x) & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
00471 /*@}*/
00472 
00473 /*!
00474  * @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
00475  *
00476  * Controls whether the POR detect circuit (for brown-out detection) is enabled
00477  * in VLLS0 mode.
00478  *
00479  * Values:
00480  * - 0 - POR detect circuit is enabled in VLLS0.
00481  * - 1 - POR detect circuit is disabled in VLLS0.
00482  */
00483 /*@{*/
00484 #define BP_SMC_VLLSCTRL_PORPO (5U)         /*!< Bit position for SMC_VLLSCTRL_PORPO. */
00485 #define BM_SMC_VLLSCTRL_PORPO (0x20U)      /*!< Bit mask for SMC_VLLSCTRL_PORPO. */
00486 #define BS_SMC_VLLSCTRL_PORPO (1U)         /*!< Bit field size in bits for SMC_VLLSCTRL_PORPO. */
00487 
00488 /*! @brief Read current value of the SMC_VLLSCTRL_PORPO field. */
00489 #define BR_SMC_VLLSCTRL_PORPO(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO)))
00490 
00491 /*! @brief Format value for bitfield SMC_VLLSCTRL_PORPO. */
00492 #define BF_SMC_VLLSCTRL_PORPO(v) ((uint8_t)((uint8_t)(v) << BP_SMC_VLLSCTRL_PORPO) & BM_SMC_VLLSCTRL_PORPO)
00493 
00494 /*! @brief Set the PORPO field to a new value. */
00495 #define BW_SMC_VLLSCTRL_PORPO(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_SMC_VLLSCTRL_ADDR(x), BP_SMC_VLLSCTRL_PORPO), v))
00496 /*@}*/
00497 
00498 /*******************************************************************************
00499  * HW_SMC_PMSTAT - Power Mode Status register
00500  ******************************************************************************/
00501 
00502 /*!
00503  * @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
00504  *
00505  * Reset value: 0x01U
00506  *
00507  * PMSTAT is a read-only, one-hot register which indicates the current power
00508  * mode of the system. This register is reset on Chip POR not VLLS and by reset
00509  * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
00510  * trigger Chip POR not VLLS. See the Reset section details for more information.
00511  */
00512 typedef union _hw_smc_pmstat
00513 {
00514     uint8_t U;
00515     struct _hw_smc_pmstat_bitfields
00516     {
00517         uint8_t PMSTAT : 7;            /*!< [6:0]  */
00518         uint8_t RESERVED0 : 1;         /*!< [7]  */
00519     } B;
00520 } hw_smc_pmstat_t;
00521 
00522 /*!
00523  * @name Constants and macros for entire SMC_PMSTAT register
00524  */
00525 /*@{*/
00526 #define HW_SMC_PMSTAT_ADDR(x)    ((x) + 0x3U)
00527 
00528 #define HW_SMC_PMSTAT(x)         (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR(x))
00529 #define HW_SMC_PMSTAT_RD(x)      (ADDRESS_READ(hw_smc_pmstat_t, HW_SMC_PMSTAT_ADDR(x)))
00530 /*@}*/
00531 
00532 /*
00533  * Constants & macros for individual SMC_PMSTAT bitfields
00534  */
00535 
00536 /*!
00537  * @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
00538  *
00539  * When debug is enabled, the PMSTAT will not update to STOP or VLPS
00540  */
00541 /*@{*/
00542 #define BP_SMC_PMSTAT_PMSTAT (0U)          /*!< Bit position for SMC_PMSTAT_PMSTAT. */
00543 #define BM_SMC_PMSTAT_PMSTAT (0x7FU)       /*!< Bit mask for SMC_PMSTAT_PMSTAT. */
00544 #define BS_SMC_PMSTAT_PMSTAT (7U)          /*!< Bit field size in bits for SMC_PMSTAT_PMSTAT. */
00545 
00546 /*! @brief Read current value of the SMC_PMSTAT_PMSTAT field. */
00547 #define BR_SMC_PMSTAT_PMSTAT(x) (UNION_READ(hw_smc_pmstat_t, HW_SMC_PMSTAT_ADDR(x), U, B.PMSTAT))
00548 /*@}*/
00549 
00550 /*******************************************************************************
00551  * hw_smc_t - module struct
00552  ******************************************************************************/
00553 /*!
00554  * @brief All SMC module registers.
00555  */
00556 #pragma pack(1)
00557 typedef struct _hw_smc
00558 {
00559     __IO hw_smc_pmprot_t PMPROT ;           /*!< [0x0] Power Mode Protection register */
00560     __IO hw_smc_pmctrl_t PMCTRL ;           /*!< [0x1] Power Mode Control register */
00561     __IO hw_smc_vllsctrl_t VLLSCTRL ;       /*!< [0x2] VLLS Control register */
00562     __I hw_smc_pmstat_t PMSTAT ;            /*!< [0x3] Power Mode Status register */
00563 } hw_smc_t;
00564 #pragma pack()
00565 
00566 /*! @brief Macro to access all SMC registers. */
00567 /*! @param x SMC module instance base address. */
00568 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00569  *     use the '&' operator, like <code>&HW_SMC(SMC_BASE)</code>. */
00570 #define HW_SMC(x)      (*(hw_smc_t *)(x))
00571 
00572 #endif /* __HW_SMC_REGISTERS_H__ */
00573 /* EOF */