MK64F12_rtc.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_RTC_REGISTERS_H__
00088 #define __HW_RTC_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 RTC
00095  *
00096  * Secure Real Time Clock
00097  *
00098  * Registers defined in this header file:
00099  * - HW_RTC_TSR - RTC Time Seconds Register
00100  * - HW_RTC_TPR - RTC Time Prescaler Register
00101  * - HW_RTC_TAR - RTC Time Alarm Register
00102  * - HW_RTC_TCR - RTC Time Compensation Register
00103  * - HW_RTC_CR - RTC Control Register
00104  * - HW_RTC_SR - RTC Status Register
00105  * - HW_RTC_LR - RTC Lock Register
00106  * - HW_RTC_IER - RTC Interrupt Enable Register
00107  * - HW_RTC_WAR - RTC Write Access Register
00108  * - HW_RTC_RAR - RTC Read Access Register
00109  *
00110  * - hw_rtc_t - Struct containing all module registers.
00111  */
00112 
00113 #define HW_RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
00114 
00115 /*******************************************************************************
00116  * HW_RTC_TSR - RTC Time Seconds Register
00117  ******************************************************************************/
00118 
00119 /*!
00120  * @brief HW_RTC_TSR - RTC Time Seconds Register (RW)
00121  *
00122  * Reset value: 0x00000000U
00123  */
00124 typedef union _hw_rtc_tsr
00125 {
00126     uint32_t U;
00127     struct _hw_rtc_tsr_bitfields
00128     {
00129         uint32_t TSR : 32;             /*!< [31:0] Time Seconds Register */
00130     } B;
00131 } hw_rtc_tsr_t;
00132 
00133 /*!
00134  * @name Constants and macros for entire RTC_TSR register
00135  */
00136 /*@{*/
00137 #define HW_RTC_TSR_ADDR(x)       ((x) + 0x0U)
00138 
00139 #define HW_RTC_TSR(x)            (*(__IO hw_rtc_tsr_t *) HW_RTC_TSR_ADDR(x))
00140 #define HW_RTC_TSR_RD(x)         (ADDRESS_READ(hw_rtc_tsr_t, HW_RTC_TSR_ADDR(x)))
00141 #define HW_RTC_TSR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_tsr_t, HW_RTC_TSR_ADDR(x), v))
00142 #define HW_RTC_TSR_SET(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) |  (v)))
00143 #define HW_RTC_TSR_CLR(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) & ~(v)))
00144 #define HW_RTC_TSR_TOG(x, v)     (HW_RTC_TSR_WR(x, HW_RTC_TSR_RD(x) ^  (v)))
00145 /*@}*/
00146 
00147 /*
00148  * Constants & macros for individual RTC_TSR bitfields
00149  */
00150 
00151 /*!
00152  * @name Register RTC_TSR, field TSR[31:0] (RW)
00153  *
00154  * When the time counter is enabled, the TSR is read only and increments once a
00155  * second provided SR[TOF] or SR[TIF] are not set. The time counter will read as
00156  * zero when SR[TOF] or SR[TIF] are set. When the time counter is disabled, the
00157  * TSR can be read or written. Writing to the TSR when the time counter is
00158  * disabled will clear the SR[TOF] and/or the SR[TIF]. Writing to TSR with zero is
00159  * supported, but not recommended because TSR will read as zero when SR[TIF] or
00160  * SR[TOF] are set (indicating the time is invalid).
00161  */
00162 /*@{*/
00163 #define BP_RTC_TSR_TSR       (0U)          /*!< Bit position for RTC_TSR_TSR. */
00164 #define BM_RTC_TSR_TSR       (0xFFFFFFFFU) /*!< Bit mask for RTC_TSR_TSR. */
00165 #define BS_RTC_TSR_TSR       (32U)         /*!< Bit field size in bits for RTC_TSR_TSR. */
00166 
00167 /*! @brief Read current value of the RTC_TSR_TSR field. */
00168 #define BR_RTC_TSR_TSR(x)    (HW_RTC_TSR(x).U)
00169 
00170 /*! @brief Format value for bitfield RTC_TSR_TSR. */
00171 #define BF_RTC_TSR_TSR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TSR_TSR) & BM_RTC_TSR_TSR)
00172 
00173 /*! @brief Set the TSR field to a new value. */
00174 #define BW_RTC_TSR_TSR(x, v) (HW_RTC_TSR_WR(x, v))
00175 /*@}*/
00176 
00177 /*******************************************************************************
00178  * HW_RTC_TPR - RTC Time Prescaler Register
00179  ******************************************************************************/
00180 
00181 /*!
00182  * @brief HW_RTC_TPR - RTC Time Prescaler Register (RW)
00183  *
00184  * Reset value: 0x00000000U
00185  */
00186 typedef union _hw_rtc_tpr
00187 {
00188     uint32_t U;
00189     struct _hw_rtc_tpr_bitfields
00190     {
00191         uint32_t TPR : 16;             /*!< [15:0] Time Prescaler Register */
00192         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00193     } B;
00194 } hw_rtc_tpr_t;
00195 
00196 /*!
00197  * @name Constants and macros for entire RTC_TPR register
00198  */
00199 /*@{*/
00200 #define HW_RTC_TPR_ADDR(x)       ((x) + 0x4U)
00201 
00202 #define HW_RTC_TPR(x)            (*(__IO hw_rtc_tpr_t *) HW_RTC_TPR_ADDR(x))
00203 #define HW_RTC_TPR_RD(x)         (ADDRESS_READ(hw_rtc_tpr_t, HW_RTC_TPR_ADDR(x)))
00204 #define HW_RTC_TPR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_tpr_t, HW_RTC_TPR_ADDR(x), v))
00205 #define HW_RTC_TPR_SET(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) |  (v)))
00206 #define HW_RTC_TPR_CLR(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) & ~(v)))
00207 #define HW_RTC_TPR_TOG(x, v)     (HW_RTC_TPR_WR(x, HW_RTC_TPR_RD(x) ^  (v)))
00208 /*@}*/
00209 
00210 /*
00211  * Constants & macros for individual RTC_TPR bitfields
00212  */
00213 
00214 /*!
00215  * @name Register RTC_TPR, field TPR[15:0] (RW)
00216  *
00217  * When the time counter is enabled, the TPR is read only and increments every
00218  * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
00219  * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
00220  * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
00221  * to a logic zero.
00222  */
00223 /*@{*/
00224 #define BP_RTC_TPR_TPR       (0U)          /*!< Bit position for RTC_TPR_TPR. */
00225 #define BM_RTC_TPR_TPR       (0x0000FFFFU) /*!< Bit mask for RTC_TPR_TPR. */
00226 #define BS_RTC_TPR_TPR       (16U)         /*!< Bit field size in bits for RTC_TPR_TPR. */
00227 
00228 /*! @brief Read current value of the RTC_TPR_TPR field. */
00229 #define BR_RTC_TPR_TPR(x)    (UNION_READ(hw_rtc_tpr_t, HW_RTC_TPR_ADDR(x), U, B.TPR))
00230 
00231 /*! @brief Format value for bitfield RTC_TPR_TPR. */
00232 #define BF_RTC_TPR_TPR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TPR_TPR) & BM_RTC_TPR_TPR)
00233 
00234 /*! @brief Set the TPR field to a new value. */
00235 #define BW_RTC_TPR_TPR(x, v) (HW_RTC_TPR_WR(x, (HW_RTC_TPR_RD(x) & ~BM_RTC_TPR_TPR) | BF_RTC_TPR_TPR(v)))
00236 /*@}*/
00237 
00238 /*******************************************************************************
00239  * HW_RTC_TAR - RTC Time Alarm Register
00240  ******************************************************************************/
00241 
00242 /*!
00243  * @brief HW_RTC_TAR - RTC Time Alarm Register (RW)
00244  *
00245  * Reset value: 0x00000000U
00246  */
00247 typedef union _hw_rtc_tar
00248 {
00249     uint32_t U;
00250     struct _hw_rtc_tar_bitfields
00251     {
00252         uint32_t TAR : 32;             /*!< [31:0] Time Alarm Register */
00253     } B;
00254 } hw_rtc_tar_t;
00255 
00256 /*!
00257  * @name Constants and macros for entire RTC_TAR register
00258  */
00259 /*@{*/
00260 #define HW_RTC_TAR_ADDR(x)       ((x) + 0x8U)
00261 
00262 #define HW_RTC_TAR(x)            (*(__IO hw_rtc_tar_t *) HW_RTC_TAR_ADDR(x))
00263 #define HW_RTC_TAR_RD(x)         (ADDRESS_READ(hw_rtc_tar_t, HW_RTC_TAR_ADDR(x)))
00264 #define HW_RTC_TAR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_tar_t, HW_RTC_TAR_ADDR(x), v))
00265 #define HW_RTC_TAR_SET(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) |  (v)))
00266 #define HW_RTC_TAR_CLR(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) & ~(v)))
00267 #define HW_RTC_TAR_TOG(x, v)     (HW_RTC_TAR_WR(x, HW_RTC_TAR_RD(x) ^  (v)))
00268 /*@}*/
00269 
00270 /*
00271  * Constants & macros for individual RTC_TAR bitfields
00272  */
00273 
00274 /*!
00275  * @name Register RTC_TAR, field TAR[31:0] (RW)
00276  *
00277  * When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR]
00278  * equals the TSR[TSR] and the TSR[TSR] increments. Writing to the TAR clears the
00279  * SR[TAF].
00280  */
00281 /*@{*/
00282 #define BP_RTC_TAR_TAR       (0U)          /*!< Bit position for RTC_TAR_TAR. */
00283 #define BM_RTC_TAR_TAR       (0xFFFFFFFFU) /*!< Bit mask for RTC_TAR_TAR. */
00284 #define BS_RTC_TAR_TAR       (32U)         /*!< Bit field size in bits for RTC_TAR_TAR. */
00285 
00286 /*! @brief Read current value of the RTC_TAR_TAR field. */
00287 #define BR_RTC_TAR_TAR(x)    (HW_RTC_TAR(x).U)
00288 
00289 /*! @brief Format value for bitfield RTC_TAR_TAR. */
00290 #define BF_RTC_TAR_TAR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TAR_TAR) & BM_RTC_TAR_TAR)
00291 
00292 /*! @brief Set the TAR field to a new value. */
00293 #define BW_RTC_TAR_TAR(x, v) (HW_RTC_TAR_WR(x, v))
00294 /*@}*/
00295 
00296 /*******************************************************************************
00297  * HW_RTC_TCR - RTC Time Compensation Register
00298  ******************************************************************************/
00299 
00300 /*!
00301  * @brief HW_RTC_TCR - RTC Time Compensation Register (RW)
00302  *
00303  * Reset value: 0x00000000U
00304  */
00305 typedef union _hw_rtc_tcr
00306 {
00307     uint32_t U;
00308     struct _hw_rtc_tcr_bitfields
00309     {
00310         uint32_t TCR : 8;              /*!< [7:0] Time Compensation Register */
00311         uint32_t CIR : 8;              /*!< [15:8] Compensation Interval Register */
00312         uint32_t TCV : 8;              /*!< [23:16] Time Compensation Value */
00313         uint32_t CIC : 8;              /*!< [31:24] Compensation Interval Counter */
00314     } B;
00315 } hw_rtc_tcr_t;
00316 
00317 /*!
00318  * @name Constants and macros for entire RTC_TCR register
00319  */
00320 /*@{*/
00321 #define HW_RTC_TCR_ADDR(x)       ((x) + 0xCU)
00322 
00323 #define HW_RTC_TCR(x)            (*(__IO hw_rtc_tcr_t *) HW_RTC_TCR_ADDR(x))
00324 #define HW_RTC_TCR_RD(x)         (ADDRESS_READ(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x)))
00325 #define HW_RTC_TCR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x), v))
00326 #define HW_RTC_TCR_SET(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) |  (v)))
00327 #define HW_RTC_TCR_CLR(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) & ~(v)))
00328 #define HW_RTC_TCR_TOG(x, v)     (HW_RTC_TCR_WR(x, HW_RTC_TCR_RD(x) ^  (v)))
00329 /*@}*/
00330 
00331 /*
00332  * Constants & macros for individual RTC_TCR bitfields
00333  */
00334 
00335 /*!
00336  * @name Register RTC_TCR, field TCR[7:0] (RW)
00337  *
00338  * Configures the number of 32.768 kHz clock cycles in each second. This
00339  * register is double buffered and writes do not take affect until the end of the
00340  * current compensation interval.
00341  *
00342  * Values:
00343  * - 10000000 - Time Prescaler Register overflows every 32896 clock cycles.
00344  * - 11111111 - Time Prescaler Register overflows every 32769 clock cycles.
00345  * - 0 - Time Prescaler Register overflows every 32768 clock cycles.
00346  * - 1 - Time Prescaler Register overflows every 32767 clock cycles.
00347  * - 1111111 - Time Prescaler Register overflows every 32641 clock cycles.
00348  */
00349 /*@{*/
00350 #define BP_RTC_TCR_TCR       (0U)          /*!< Bit position for RTC_TCR_TCR. */
00351 #define BM_RTC_TCR_TCR       (0x000000FFU) /*!< Bit mask for RTC_TCR_TCR. */
00352 #define BS_RTC_TCR_TCR       (8U)          /*!< Bit field size in bits for RTC_TCR_TCR. */
00353 
00354 /*! @brief Read current value of the RTC_TCR_TCR field. */
00355 #define BR_RTC_TCR_TCR(x)    (UNION_READ(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x), U, B.TCR))
00356 
00357 /*! @brief Format value for bitfield RTC_TCR_TCR. */
00358 #define BF_RTC_TCR_TCR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_TCR) & BM_RTC_TCR_TCR)
00359 
00360 /*! @brief Set the TCR field to a new value. */
00361 #define BW_RTC_TCR_TCR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_TCR) | BF_RTC_TCR_TCR(v)))
00362 /*@}*/
00363 
00364 /*!
00365  * @name Register RTC_TCR, field CIR[15:8] (RW)
00366  *
00367  * Configures the compensation interval in seconds from 1 to 256 to control how
00368  * frequently the TCR should adjust the number of 32.768 kHz cycles in each
00369  * second. The value written should be one less than the number of seconds. For
00370  * example, write zero to configure for a compensation interval of one second. This
00371  * register is double buffered and writes do not take affect until the end of the
00372  * current compensation interval.
00373  */
00374 /*@{*/
00375 #define BP_RTC_TCR_CIR       (8U)          /*!< Bit position for RTC_TCR_CIR. */
00376 #define BM_RTC_TCR_CIR       (0x0000FF00U) /*!< Bit mask for RTC_TCR_CIR. */
00377 #define BS_RTC_TCR_CIR       (8U)          /*!< Bit field size in bits for RTC_TCR_CIR. */
00378 
00379 /*! @brief Read current value of the RTC_TCR_CIR field. */
00380 #define BR_RTC_TCR_CIR(x)    (UNION_READ(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x), U, B.CIR))
00381 
00382 /*! @brief Format value for bitfield RTC_TCR_CIR. */
00383 #define BF_RTC_TCR_CIR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_TCR_CIR) & BM_RTC_TCR_CIR)
00384 
00385 /*! @brief Set the CIR field to a new value. */
00386 #define BW_RTC_TCR_CIR(x, v) (HW_RTC_TCR_WR(x, (HW_RTC_TCR_RD(x) & ~BM_RTC_TCR_CIR) | BF_RTC_TCR_CIR(v)))
00387 /*@}*/
00388 
00389 /*!
00390  * @name Register RTC_TCR, field TCV[23:16] (RO)
00391  *
00392  * Current value used by the compensation logic for the present second interval.
00393  * Updated once a second if the CIC equals 0 with the contents of the TCR field.
00394  * If the CIC does not equal zero then it is loaded with zero (compensation is
00395  * not enabled for that second increment).
00396  */
00397 /*@{*/
00398 #define BP_RTC_TCR_TCV       (16U)         /*!< Bit position for RTC_TCR_TCV. */
00399 #define BM_RTC_TCR_TCV       (0x00FF0000U) /*!< Bit mask for RTC_TCR_TCV. */
00400 #define BS_RTC_TCR_TCV       (8U)          /*!< Bit field size in bits for RTC_TCR_TCV. */
00401 
00402 /*! @brief Read current value of the RTC_TCR_TCV field. */
00403 #define BR_RTC_TCR_TCV(x)    (UNION_READ(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x), U, B.TCV))
00404 /*@}*/
00405 
00406 /*!
00407  * @name Register RTC_TCR, field CIC[31:24] (RO)
00408  *
00409  * Current value of the compensation interval counter. If the compensation
00410  * interval counter equals zero then it is loaded with the contents of the CIR. If the
00411  * CIC does not equal zero then it is decremented once a second.
00412  */
00413 /*@{*/
00414 #define BP_RTC_TCR_CIC       (24U)         /*!< Bit position for RTC_TCR_CIC. */
00415 #define BM_RTC_TCR_CIC       (0xFF000000U) /*!< Bit mask for RTC_TCR_CIC. */
00416 #define BS_RTC_TCR_CIC       (8U)          /*!< Bit field size in bits for RTC_TCR_CIC. */
00417 
00418 /*! @brief Read current value of the RTC_TCR_CIC field. */
00419 #define BR_RTC_TCR_CIC(x)    (UNION_READ(hw_rtc_tcr_t, HW_RTC_TCR_ADDR(x), U, B.CIC))
00420 /*@}*/
00421 
00422 /*******************************************************************************
00423  * HW_RTC_CR - RTC Control Register
00424  ******************************************************************************/
00425 
00426 /*!
00427  * @brief HW_RTC_CR - RTC Control Register (RW)
00428  *
00429  * Reset value: 0x00000000U
00430  */
00431 typedef union _hw_rtc_cr
00432 {
00433     uint32_t U;
00434     struct _hw_rtc_cr_bitfields
00435     {
00436         uint32_t SWR : 1;              /*!< [0] Software Reset */
00437         uint32_t WPE : 1;              /*!< [1] Wakeup Pin Enable */
00438         uint32_t SUP : 1;              /*!< [2] Supervisor Access */
00439         uint32_t UM : 1;               /*!< [3] Update Mode */
00440         uint32_t WPS : 1;              /*!< [4] Wakeup Pin Select */
00441         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
00442         uint32_t OSCE : 1;             /*!< [8] Oscillator Enable */
00443         uint32_t CLKO : 1;             /*!< [9] Clock Output */
00444         uint32_t SC16P : 1;            /*!< [10] Oscillator 16pF Load Configure */
00445         uint32_t SC8P : 1;             /*!< [11] Oscillator 8pF Load Configure */
00446         uint32_t SC4P : 1;             /*!< [12] Oscillator 4pF Load Configure */
00447         uint32_t SC2P : 1;             /*!< [13] Oscillator 2pF Load Configure */
00448         uint32_t RESERVED1 : 18;       /*!< [31:14]  */
00449     } B;
00450 } hw_rtc_cr_t;
00451 
00452 /*!
00453  * @name Constants and macros for entire RTC_CR register
00454  */
00455 /*@{*/
00456 #define HW_RTC_CR_ADDR(x)        ((x) + 0x10U)
00457 
00458 #define HW_RTC_CR(x)             (*(__IO hw_rtc_cr_t *) HW_RTC_CR_ADDR(x))
00459 #define HW_RTC_CR_RD(x)          (ADDRESS_READ(hw_rtc_cr_t, HW_RTC_CR_ADDR(x)))
00460 #define HW_RTC_CR_WR(x, v)       (ADDRESS_WRITE(hw_rtc_cr_t, HW_RTC_CR_ADDR(x), v))
00461 #define HW_RTC_CR_SET(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) |  (v)))
00462 #define HW_RTC_CR_CLR(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) & ~(v)))
00463 #define HW_RTC_CR_TOG(x, v)      (HW_RTC_CR_WR(x, HW_RTC_CR_RD(x) ^  (v)))
00464 /*@}*/
00465 
00466 /*
00467  * Constants & macros for individual RTC_CR bitfields
00468  */
00469 
00470 /*!
00471  * @name Register RTC_CR, field SWR[0] (RW)
00472  *
00473  * Values:
00474  * - 0 - No effect.
00475  * - 1 - Resets all RTC registers except for the SWR bit and the RTC_WAR and
00476  *     RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software
00477  *     explicitly clearing it.
00478  */
00479 /*@{*/
00480 #define BP_RTC_CR_SWR        (0U)          /*!< Bit position for RTC_CR_SWR. */
00481 #define BM_RTC_CR_SWR        (0x00000001U) /*!< Bit mask for RTC_CR_SWR. */
00482 #define BS_RTC_CR_SWR        (1U)          /*!< Bit field size in bits for RTC_CR_SWR. */
00483 
00484 /*! @brief Read current value of the RTC_CR_SWR field. */
00485 #define BR_RTC_CR_SWR(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR)))
00486 
00487 /*! @brief Format value for bitfield RTC_CR_SWR. */
00488 #define BF_RTC_CR_SWR(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SWR) & BM_RTC_CR_SWR)
00489 
00490 /*! @brief Set the SWR field to a new value. */
00491 #define BW_RTC_CR_SWR(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SWR), v))
00492 /*@}*/
00493 
00494 /*!
00495  * @name Register RTC_CR, field WPE[1] (RW)
00496  *
00497  * The wakeup pin is optional and not available on all devices.
00498  *
00499  * Values:
00500  * - 0 - Wakeup pin is disabled.
00501  * - 1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
00502  *     asserts or the wakeup pin is turned on.
00503  */
00504 /*@{*/
00505 #define BP_RTC_CR_WPE        (1U)          /*!< Bit position for RTC_CR_WPE. */
00506 #define BM_RTC_CR_WPE        (0x00000002U) /*!< Bit mask for RTC_CR_WPE. */
00507 #define BS_RTC_CR_WPE        (1U)          /*!< Bit field size in bits for RTC_CR_WPE. */
00508 
00509 /*! @brief Read current value of the RTC_CR_WPE field. */
00510 #define BR_RTC_CR_WPE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE)))
00511 
00512 /*! @brief Format value for bitfield RTC_CR_WPE. */
00513 #define BF_RTC_CR_WPE(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPE) & BM_RTC_CR_WPE)
00514 
00515 /*! @brief Set the WPE field to a new value. */
00516 #define BW_RTC_CR_WPE(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPE), v))
00517 /*@}*/
00518 
00519 /*!
00520  * @name Register RTC_CR, field SUP[2] (RW)
00521  *
00522  * Values:
00523  * - 0 - Non-supervisor mode write accesses are not supported and generate a bus
00524  *     error.
00525  * - 1 - Non-supervisor mode write accesses are supported.
00526  */
00527 /*@{*/
00528 #define BP_RTC_CR_SUP        (2U)          /*!< Bit position for RTC_CR_SUP. */
00529 #define BM_RTC_CR_SUP        (0x00000004U) /*!< Bit mask for RTC_CR_SUP. */
00530 #define BS_RTC_CR_SUP        (1U)          /*!< Bit field size in bits for RTC_CR_SUP. */
00531 
00532 /*! @brief Read current value of the RTC_CR_SUP field. */
00533 #define BR_RTC_CR_SUP(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP)))
00534 
00535 /*! @brief Format value for bitfield RTC_CR_SUP. */
00536 #define BF_RTC_CR_SUP(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SUP) & BM_RTC_CR_SUP)
00537 
00538 /*! @brief Set the SUP field to a new value. */
00539 #define BW_RTC_CR_SUP(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SUP), v))
00540 /*@}*/
00541 
00542 /*!
00543  * @name Register RTC_CR, field UM[3] (RW)
00544  *
00545  * Allows SR[TCE] to be written even when the Status Register is locked. When
00546  * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
00547  * the SR[TCE] is clear.
00548  *
00549  * Values:
00550  * - 0 - Registers cannot be written when locked.
00551  * - 1 - Registers can be written when locked under limited conditions.
00552  */
00553 /*@{*/
00554 #define BP_RTC_CR_UM         (3U)          /*!< Bit position for RTC_CR_UM. */
00555 #define BM_RTC_CR_UM         (0x00000008U) /*!< Bit mask for RTC_CR_UM. */
00556 #define BS_RTC_CR_UM         (1U)          /*!< Bit field size in bits for RTC_CR_UM. */
00557 
00558 /*! @brief Read current value of the RTC_CR_UM field. */
00559 #define BR_RTC_CR_UM(x)      (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM)))
00560 
00561 /*! @brief Format value for bitfield RTC_CR_UM. */
00562 #define BF_RTC_CR_UM(v)      ((uint32_t)((uint32_t)(v) << BP_RTC_CR_UM) & BM_RTC_CR_UM)
00563 
00564 /*! @brief Set the UM field to a new value. */
00565 #define BW_RTC_CR_UM(x, v)   (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_UM), v))
00566 /*@}*/
00567 
00568 /*!
00569  * @name Register RTC_CR, field WPS[4] (RW)
00570  *
00571  * The wakeup pin is optional and not available on all devices.
00572  *
00573  * Values:
00574  * - 0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
00575  *     asserts or the wakeup pin is turned on.
00576  * - 1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin
00577  *     is turned on and the 32kHz clock is output to other peripherals.
00578  */
00579 /*@{*/
00580 #define BP_RTC_CR_WPS        (4U)          /*!< Bit position for RTC_CR_WPS. */
00581 #define BM_RTC_CR_WPS        (0x00000010U) /*!< Bit mask for RTC_CR_WPS. */
00582 #define BS_RTC_CR_WPS        (1U)          /*!< Bit field size in bits for RTC_CR_WPS. */
00583 
00584 /*! @brief Read current value of the RTC_CR_WPS field. */
00585 #define BR_RTC_CR_WPS(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS)))
00586 
00587 /*! @brief Format value for bitfield RTC_CR_WPS. */
00588 #define BF_RTC_CR_WPS(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_CR_WPS) & BM_RTC_CR_WPS)
00589 
00590 /*! @brief Set the WPS field to a new value. */
00591 #define BW_RTC_CR_WPS(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_WPS), v))
00592 /*@}*/
00593 
00594 /*!
00595  * @name Register RTC_CR, field OSCE[8] (RW)
00596  *
00597  * Values:
00598  * - 0 - 32.768 kHz oscillator is disabled.
00599  * - 1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
00600  *     oscillator startup time before enabling the time counter to allow the 32.768
00601  *     kHz clock time to stabilize.
00602  */
00603 /*@{*/
00604 #define BP_RTC_CR_OSCE       (8U)          /*!< Bit position for RTC_CR_OSCE. */
00605 #define BM_RTC_CR_OSCE       (0x00000100U) /*!< Bit mask for RTC_CR_OSCE. */
00606 #define BS_RTC_CR_OSCE       (1U)          /*!< Bit field size in bits for RTC_CR_OSCE. */
00607 
00608 /*! @brief Read current value of the RTC_CR_OSCE field. */
00609 #define BR_RTC_CR_OSCE(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE)))
00610 
00611 /*! @brief Format value for bitfield RTC_CR_OSCE. */
00612 #define BF_RTC_CR_OSCE(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_OSCE) & BM_RTC_CR_OSCE)
00613 
00614 /*! @brief Set the OSCE field to a new value. */
00615 #define BW_RTC_CR_OSCE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_OSCE), v))
00616 /*@}*/
00617 
00618 /*!
00619  * @name Register RTC_CR, field CLKO[9] (RW)
00620  *
00621  * Values:
00622  * - 0 - The 32 kHz clock is output to other peripherals.
00623  * - 1 - The 32 kHz clock is not output to other peripherals.
00624  */
00625 /*@{*/
00626 #define BP_RTC_CR_CLKO       (9U)          /*!< Bit position for RTC_CR_CLKO. */
00627 #define BM_RTC_CR_CLKO       (0x00000200U) /*!< Bit mask for RTC_CR_CLKO. */
00628 #define BS_RTC_CR_CLKO       (1U)          /*!< Bit field size in bits for RTC_CR_CLKO. */
00629 
00630 /*! @brief Read current value of the RTC_CR_CLKO field. */
00631 #define BR_RTC_CR_CLKO(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO)))
00632 
00633 /*! @brief Format value for bitfield RTC_CR_CLKO. */
00634 #define BF_RTC_CR_CLKO(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_CLKO) & BM_RTC_CR_CLKO)
00635 
00636 /*! @brief Set the CLKO field to a new value. */
00637 #define BW_RTC_CR_CLKO(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_CLKO), v))
00638 /*@}*/
00639 
00640 /*!
00641  * @name Register RTC_CR, field SC16P[10] (RW)
00642  *
00643  * Values:
00644  * - 0 - Disable the load.
00645  * - 1 - Enable the additional load.
00646  */
00647 /*@{*/
00648 #define BP_RTC_CR_SC16P      (10U)         /*!< Bit position for RTC_CR_SC16P. */
00649 #define BM_RTC_CR_SC16P      (0x00000400U) /*!< Bit mask for RTC_CR_SC16P. */
00650 #define BS_RTC_CR_SC16P      (1U)          /*!< Bit field size in bits for RTC_CR_SC16P. */
00651 
00652 /*! @brief Read current value of the RTC_CR_SC16P field. */
00653 #define BR_RTC_CR_SC16P(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P)))
00654 
00655 /*! @brief Format value for bitfield RTC_CR_SC16P. */
00656 #define BF_RTC_CR_SC16P(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC16P) & BM_RTC_CR_SC16P)
00657 
00658 /*! @brief Set the SC16P field to a new value. */
00659 #define BW_RTC_CR_SC16P(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC16P), v))
00660 /*@}*/
00661 
00662 /*!
00663  * @name Register RTC_CR, field SC8P[11] (RW)
00664  *
00665  * Values:
00666  * - 0 - Disable the load.
00667  * - 1 - Enable the additional load.
00668  */
00669 /*@{*/
00670 #define BP_RTC_CR_SC8P       (11U)         /*!< Bit position for RTC_CR_SC8P. */
00671 #define BM_RTC_CR_SC8P       (0x00000800U) /*!< Bit mask for RTC_CR_SC8P. */
00672 #define BS_RTC_CR_SC8P       (1U)          /*!< Bit field size in bits for RTC_CR_SC8P. */
00673 
00674 /*! @brief Read current value of the RTC_CR_SC8P field. */
00675 #define BR_RTC_CR_SC8P(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P)))
00676 
00677 /*! @brief Format value for bitfield RTC_CR_SC8P. */
00678 #define BF_RTC_CR_SC8P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC8P) & BM_RTC_CR_SC8P)
00679 
00680 /*! @brief Set the SC8P field to a new value. */
00681 #define BW_RTC_CR_SC8P(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC8P), v))
00682 /*@}*/
00683 
00684 /*!
00685  * @name Register RTC_CR, field SC4P[12] (RW)
00686  *
00687  * Values:
00688  * - 0 - Disable the load.
00689  * - 1 - Enable the additional load.
00690  */
00691 /*@{*/
00692 #define BP_RTC_CR_SC4P       (12U)         /*!< Bit position for RTC_CR_SC4P. */
00693 #define BM_RTC_CR_SC4P       (0x00001000U) /*!< Bit mask for RTC_CR_SC4P. */
00694 #define BS_RTC_CR_SC4P       (1U)          /*!< Bit field size in bits for RTC_CR_SC4P. */
00695 
00696 /*! @brief Read current value of the RTC_CR_SC4P field. */
00697 #define BR_RTC_CR_SC4P(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P)))
00698 
00699 /*! @brief Format value for bitfield RTC_CR_SC4P. */
00700 #define BF_RTC_CR_SC4P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC4P) & BM_RTC_CR_SC4P)
00701 
00702 /*! @brief Set the SC4P field to a new value. */
00703 #define BW_RTC_CR_SC4P(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC4P), v))
00704 /*@}*/
00705 
00706 /*!
00707  * @name Register RTC_CR, field SC2P[13] (RW)
00708  *
00709  * Values:
00710  * - 0 - Disable the load.
00711  * - 1 - Enable the additional load.
00712  */
00713 /*@{*/
00714 #define BP_RTC_CR_SC2P       (13U)         /*!< Bit position for RTC_CR_SC2P. */
00715 #define BM_RTC_CR_SC2P       (0x00002000U) /*!< Bit mask for RTC_CR_SC2P. */
00716 #define BS_RTC_CR_SC2P       (1U)          /*!< Bit field size in bits for RTC_CR_SC2P. */
00717 
00718 /*! @brief Read current value of the RTC_CR_SC2P field. */
00719 #define BR_RTC_CR_SC2P(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P)))
00720 
00721 /*! @brief Format value for bitfield RTC_CR_SC2P. */
00722 #define BF_RTC_CR_SC2P(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_CR_SC2P) & BM_RTC_CR_SC2P)
00723 
00724 /*! @brief Set the SC2P field to a new value. */
00725 #define BW_RTC_CR_SC2P(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_CR_ADDR(x), BP_RTC_CR_SC2P), v))
00726 /*@}*/
00727 
00728 /*******************************************************************************
00729  * HW_RTC_SR - RTC Status Register
00730  ******************************************************************************/
00731 
00732 /*!
00733  * @brief HW_RTC_SR - RTC Status Register (RW)
00734  *
00735  * Reset value: 0x00000001U
00736  */
00737 typedef union _hw_rtc_sr
00738 {
00739     uint32_t U;
00740     struct _hw_rtc_sr_bitfields
00741     {
00742         uint32_t TIF : 1;              /*!< [0] Time Invalid Flag */
00743         uint32_t TOF : 1;              /*!< [1] Time Overflow Flag */
00744         uint32_t TAF : 1;              /*!< [2] Time Alarm Flag */
00745         uint32_t RESERVED0 : 1;        /*!< [3]  */
00746         uint32_t TCE : 1;              /*!< [4] Time Counter Enable */
00747         uint32_t RESERVED1 : 27;       /*!< [31:5]  */
00748     } B;
00749 } hw_rtc_sr_t;
00750 
00751 /*!
00752  * @name Constants and macros for entire RTC_SR register
00753  */
00754 /*@{*/
00755 #define HW_RTC_SR_ADDR(x)        ((x) + 0x14U)
00756 
00757 #define HW_RTC_SR(x)             (*(__IO hw_rtc_sr_t *) HW_RTC_SR_ADDR(x))
00758 #define HW_RTC_SR_RD(x)          (ADDRESS_READ(hw_rtc_sr_t, HW_RTC_SR_ADDR(x)))
00759 #define HW_RTC_SR_WR(x, v)       (ADDRESS_WRITE(hw_rtc_sr_t, HW_RTC_SR_ADDR(x), v))
00760 #define HW_RTC_SR_SET(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) |  (v)))
00761 #define HW_RTC_SR_CLR(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) & ~(v)))
00762 #define HW_RTC_SR_TOG(x, v)      (HW_RTC_SR_WR(x, HW_RTC_SR_RD(x) ^  (v)))
00763 /*@}*/
00764 
00765 /*
00766  * Constants & macros for individual RTC_SR bitfields
00767  */
00768 
00769 /*!
00770  * @name Register RTC_SR, field TIF[0] (RO)
00771  *
00772  * The time invalid flag is set on VBAT POR or software reset. The TSR and TPR
00773  * do not increment and read as zero when this bit is set. This bit is cleared by
00774  * writing the TSR register when the time counter is disabled.
00775  *
00776  * Values:
00777  * - 0 - Time is valid.
00778  * - 1 - Time is invalid and time counter is read as zero.
00779  */
00780 /*@{*/
00781 #define BP_RTC_SR_TIF        (0U)          /*!< Bit position for RTC_SR_TIF. */
00782 #define BM_RTC_SR_TIF        (0x00000001U) /*!< Bit mask for RTC_SR_TIF. */
00783 #define BS_RTC_SR_TIF        (1U)          /*!< Bit field size in bits for RTC_SR_TIF. */
00784 
00785 /*! @brief Read current value of the RTC_SR_TIF field. */
00786 #define BR_RTC_SR_TIF(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TIF)))
00787 /*@}*/
00788 
00789 /*!
00790  * @name Register RTC_SR, field TOF[1] (RO)
00791  *
00792  * Time overflow flag is set when the time counter is enabled and overflows. The
00793  * TSR and TPR do not increment and read as zero when this bit is set. This bit
00794  * is cleared by writing the TSR register when the time counter is disabled.
00795  *
00796  * Values:
00797  * - 0 - Time overflow has not occurred.
00798  * - 1 - Time overflow has occurred and time counter is read as zero.
00799  */
00800 /*@{*/
00801 #define BP_RTC_SR_TOF        (1U)          /*!< Bit position for RTC_SR_TOF. */
00802 #define BM_RTC_SR_TOF        (0x00000002U) /*!< Bit mask for RTC_SR_TOF. */
00803 #define BS_RTC_SR_TOF        (1U)          /*!< Bit field size in bits for RTC_SR_TOF. */
00804 
00805 /*! @brief Read current value of the RTC_SR_TOF field. */
00806 #define BR_RTC_SR_TOF(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TOF)))
00807 /*@}*/
00808 
00809 /*!
00810  * @name Register RTC_SR, field TAF[2] (RO)
00811  *
00812  * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
00813  * increments. This bit is cleared by writing the TAR register.
00814  *
00815  * Values:
00816  * - 0 - Time alarm has not occurred.
00817  * - 1 - Time alarm has occurred.
00818  */
00819 /*@{*/
00820 #define BP_RTC_SR_TAF        (2U)          /*!< Bit position for RTC_SR_TAF. */
00821 #define BM_RTC_SR_TAF        (0x00000004U) /*!< Bit mask for RTC_SR_TAF. */
00822 #define BS_RTC_SR_TAF        (1U)          /*!< Bit field size in bits for RTC_SR_TAF. */
00823 
00824 /*! @brief Read current value of the RTC_SR_TAF field. */
00825 #define BR_RTC_SR_TAF(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TAF)))
00826 /*@}*/
00827 
00828 /*!
00829  * @name Register RTC_SR, field TCE[4] (RW)
00830  *
00831  * When time counter is disabled the TSR register and TPR register are
00832  * writeable, but do not increment. When time counter is enabled the TSR register and TPR
00833  * register are not writeable, but increment.
00834  *
00835  * Values:
00836  * - 0 - Time counter is disabled.
00837  * - 1 - Time counter is enabled.
00838  */
00839 /*@{*/
00840 #define BP_RTC_SR_TCE        (4U)          /*!< Bit position for RTC_SR_TCE. */
00841 #define BM_RTC_SR_TCE        (0x00000010U) /*!< Bit mask for RTC_SR_TCE. */
00842 #define BS_RTC_SR_TCE        (1U)          /*!< Bit field size in bits for RTC_SR_TCE. */
00843 
00844 /*! @brief Read current value of the RTC_SR_TCE field. */
00845 #define BR_RTC_SR_TCE(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE)))
00846 
00847 /*! @brief Format value for bitfield RTC_SR_TCE. */
00848 #define BF_RTC_SR_TCE(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_SR_TCE) & BM_RTC_SR_TCE)
00849 
00850 /*! @brief Set the TCE field to a new value. */
00851 #define BW_RTC_SR_TCE(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_SR_ADDR(x), BP_RTC_SR_TCE), v))
00852 /*@}*/
00853 
00854 /*******************************************************************************
00855  * HW_RTC_LR - RTC Lock Register
00856  ******************************************************************************/
00857 
00858 /*!
00859  * @brief HW_RTC_LR - RTC Lock Register (RW)
00860  *
00861  * Reset value: 0x000000FFU
00862  */
00863 typedef union _hw_rtc_lr
00864 {
00865     uint32_t U;
00866     struct _hw_rtc_lr_bitfields
00867     {
00868         uint32_t RESERVED0 : 3;        /*!< [2:0]  */
00869         uint32_t TCL : 1;              /*!< [3] Time Compensation Lock */
00870         uint32_t CRL : 1;              /*!< [4] Control Register Lock */
00871         uint32_t SRL : 1;              /*!< [5] Status Register Lock */
00872         uint32_t LRL : 1;              /*!< [6] Lock Register Lock */
00873         uint32_t RESERVED1 : 25;       /*!< [31:7]  */
00874     } B;
00875 } hw_rtc_lr_t;
00876 
00877 /*!
00878  * @name Constants and macros for entire RTC_LR register
00879  */
00880 /*@{*/
00881 #define HW_RTC_LR_ADDR(x)        ((x) + 0x18U)
00882 
00883 #define HW_RTC_LR(x)             (*(__IO hw_rtc_lr_t *) HW_RTC_LR_ADDR(x))
00884 #define HW_RTC_LR_RD(x)          (ADDRESS_READ(hw_rtc_lr_t, HW_RTC_LR_ADDR(x)))
00885 #define HW_RTC_LR_WR(x, v)       (ADDRESS_WRITE(hw_rtc_lr_t, HW_RTC_LR_ADDR(x), v))
00886 #define HW_RTC_LR_SET(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) |  (v)))
00887 #define HW_RTC_LR_CLR(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) & ~(v)))
00888 #define HW_RTC_LR_TOG(x, v)      (HW_RTC_LR_WR(x, HW_RTC_LR_RD(x) ^  (v)))
00889 /*@}*/
00890 
00891 /*
00892  * Constants & macros for individual RTC_LR bitfields
00893  */
00894 
00895 /*!
00896  * @name Register RTC_LR, field TCL[3] (RW)
00897  *
00898  * After being cleared, this bit can be set only by VBAT POR or software reset.
00899  *
00900  * Values:
00901  * - 0 - Time Compensation Register is locked and writes are ignored.
00902  * - 1 - Time Compensation Register is not locked and writes complete as normal.
00903  */
00904 /*@{*/
00905 #define BP_RTC_LR_TCL        (3U)          /*!< Bit position for RTC_LR_TCL. */
00906 #define BM_RTC_LR_TCL        (0x00000008U) /*!< Bit mask for RTC_LR_TCL. */
00907 #define BS_RTC_LR_TCL        (1U)          /*!< Bit field size in bits for RTC_LR_TCL. */
00908 
00909 /*! @brief Read current value of the RTC_LR_TCL field. */
00910 #define BR_RTC_LR_TCL(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL)))
00911 
00912 /*! @brief Format value for bitfield RTC_LR_TCL. */
00913 #define BF_RTC_LR_TCL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_TCL) & BM_RTC_LR_TCL)
00914 
00915 /*! @brief Set the TCL field to a new value. */
00916 #define BW_RTC_LR_TCL(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_TCL), v))
00917 /*@}*/
00918 
00919 /*!
00920  * @name Register RTC_LR, field CRL[4] (RW)
00921  *
00922  * After being cleared, this bit can only be set by VBAT POR.
00923  *
00924  * Values:
00925  * - 0 - Control Register is locked and writes are ignored.
00926  * - 1 - Control Register is not locked and writes complete as normal.
00927  */
00928 /*@{*/
00929 #define BP_RTC_LR_CRL        (4U)          /*!< Bit position for RTC_LR_CRL. */
00930 #define BM_RTC_LR_CRL        (0x00000010U) /*!< Bit mask for RTC_LR_CRL. */
00931 #define BS_RTC_LR_CRL        (1U)          /*!< Bit field size in bits for RTC_LR_CRL. */
00932 
00933 /*! @brief Read current value of the RTC_LR_CRL field. */
00934 #define BR_RTC_LR_CRL(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL)))
00935 
00936 /*! @brief Format value for bitfield RTC_LR_CRL. */
00937 #define BF_RTC_LR_CRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_CRL) & BM_RTC_LR_CRL)
00938 
00939 /*! @brief Set the CRL field to a new value. */
00940 #define BW_RTC_LR_CRL(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_CRL), v))
00941 /*@}*/
00942 
00943 /*!
00944  * @name Register RTC_LR, field SRL[5] (RW)
00945  *
00946  * After being cleared, this bit can be set only by VBAT POR or software reset.
00947  *
00948  * Values:
00949  * - 0 - Status Register is locked and writes are ignored.
00950  * - 1 - Status Register is not locked and writes complete as normal.
00951  */
00952 /*@{*/
00953 #define BP_RTC_LR_SRL        (5U)          /*!< Bit position for RTC_LR_SRL. */
00954 #define BM_RTC_LR_SRL        (0x00000020U) /*!< Bit mask for RTC_LR_SRL. */
00955 #define BS_RTC_LR_SRL        (1U)          /*!< Bit field size in bits for RTC_LR_SRL. */
00956 
00957 /*! @brief Read current value of the RTC_LR_SRL field. */
00958 #define BR_RTC_LR_SRL(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL)))
00959 
00960 /*! @brief Format value for bitfield RTC_LR_SRL. */
00961 #define BF_RTC_LR_SRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_SRL) & BM_RTC_LR_SRL)
00962 
00963 /*! @brief Set the SRL field to a new value. */
00964 #define BW_RTC_LR_SRL(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_SRL), v))
00965 /*@}*/
00966 
00967 /*!
00968  * @name Register RTC_LR, field LRL[6] (RW)
00969  *
00970  * After being cleared, this bit can be set only by VBAT POR or software reset.
00971  *
00972  * Values:
00973  * - 0 - Lock Register is locked and writes are ignored.
00974  * - 1 - Lock Register is not locked and writes complete as normal.
00975  */
00976 /*@{*/
00977 #define BP_RTC_LR_LRL        (6U)          /*!< Bit position for RTC_LR_LRL. */
00978 #define BM_RTC_LR_LRL        (0x00000040U) /*!< Bit mask for RTC_LR_LRL. */
00979 #define BS_RTC_LR_LRL        (1U)          /*!< Bit field size in bits for RTC_LR_LRL. */
00980 
00981 /*! @brief Read current value of the RTC_LR_LRL field. */
00982 #define BR_RTC_LR_LRL(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL)))
00983 
00984 /*! @brief Format value for bitfield RTC_LR_LRL. */
00985 #define BF_RTC_LR_LRL(v)     ((uint32_t)((uint32_t)(v) << BP_RTC_LR_LRL) & BM_RTC_LR_LRL)
00986 
00987 /*! @brief Set the LRL field to a new value. */
00988 #define BW_RTC_LR_LRL(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_LR_ADDR(x), BP_RTC_LR_LRL), v))
00989 /*@}*/
00990 
00991 /*******************************************************************************
00992  * HW_RTC_IER - RTC Interrupt Enable Register
00993  ******************************************************************************/
00994 
00995 /*!
00996  * @brief HW_RTC_IER - RTC Interrupt Enable Register (RW)
00997  *
00998  * Reset value: 0x00000007U
00999  */
01000 typedef union _hw_rtc_ier
01001 {
01002     uint32_t U;
01003     struct _hw_rtc_ier_bitfields
01004     {
01005         uint32_t TIIE : 1;             /*!< [0] Time Invalid Interrupt Enable */
01006         uint32_t TOIE : 1;             /*!< [1] Time Overflow Interrupt Enable */
01007         uint32_t TAIE : 1;             /*!< [2] Time Alarm Interrupt Enable */
01008         uint32_t RESERVED0 : 1;        /*!< [3]  */
01009         uint32_t TSIE : 1;             /*!< [4] Time Seconds Interrupt Enable */
01010         uint32_t RESERVED1 : 2;        /*!< [6:5]  */
01011         uint32_t WPON : 1;             /*!< [7] Wakeup Pin On */
01012         uint32_t RESERVED2 : 24;       /*!< [31:8]  */
01013     } B;
01014 } hw_rtc_ier_t;
01015 
01016 /*!
01017  * @name Constants and macros for entire RTC_IER register
01018  */
01019 /*@{*/
01020 #define HW_RTC_IER_ADDR(x)       ((x) + 0x1CU)
01021 
01022 #define HW_RTC_IER(x)            (*(__IO hw_rtc_ier_t *) HW_RTC_IER_ADDR(x))
01023 #define HW_RTC_IER_RD(x)         (ADDRESS_READ(hw_rtc_ier_t, HW_RTC_IER_ADDR(x)))
01024 #define HW_RTC_IER_WR(x, v)      (ADDRESS_WRITE(hw_rtc_ier_t, HW_RTC_IER_ADDR(x), v))
01025 #define HW_RTC_IER_SET(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) |  (v)))
01026 #define HW_RTC_IER_CLR(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) & ~(v)))
01027 #define HW_RTC_IER_TOG(x, v)     (HW_RTC_IER_WR(x, HW_RTC_IER_RD(x) ^  (v)))
01028 /*@}*/
01029 
01030 /*
01031  * Constants & macros for individual RTC_IER bitfields
01032  */
01033 
01034 /*!
01035  * @name Register RTC_IER, field TIIE[0] (RW)
01036  *
01037  * Values:
01038  * - 0 - Time invalid flag does not generate an interrupt.
01039  * - 1 - Time invalid flag does generate an interrupt.
01040  */
01041 /*@{*/
01042 #define BP_RTC_IER_TIIE      (0U)          /*!< Bit position for RTC_IER_TIIE. */
01043 #define BM_RTC_IER_TIIE      (0x00000001U) /*!< Bit mask for RTC_IER_TIIE. */
01044 #define BS_RTC_IER_TIIE      (1U)          /*!< Bit field size in bits for RTC_IER_TIIE. */
01045 
01046 /*! @brief Read current value of the RTC_IER_TIIE field. */
01047 #define BR_RTC_IER_TIIE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE)))
01048 
01049 /*! @brief Format value for bitfield RTC_IER_TIIE. */
01050 #define BF_RTC_IER_TIIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TIIE) & BM_RTC_IER_TIIE)
01051 
01052 /*! @brief Set the TIIE field to a new value. */
01053 #define BW_RTC_IER_TIIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TIIE), v))
01054 /*@}*/
01055 
01056 /*!
01057  * @name Register RTC_IER, field TOIE[1] (RW)
01058  *
01059  * Values:
01060  * - 0 - Time overflow flag does not generate an interrupt.
01061  * - 1 - Time overflow flag does generate an interrupt.
01062  */
01063 /*@{*/
01064 #define BP_RTC_IER_TOIE      (1U)          /*!< Bit position for RTC_IER_TOIE. */
01065 #define BM_RTC_IER_TOIE      (0x00000002U) /*!< Bit mask for RTC_IER_TOIE. */
01066 #define BS_RTC_IER_TOIE      (1U)          /*!< Bit field size in bits for RTC_IER_TOIE. */
01067 
01068 /*! @brief Read current value of the RTC_IER_TOIE field. */
01069 #define BR_RTC_IER_TOIE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE)))
01070 
01071 /*! @brief Format value for bitfield RTC_IER_TOIE. */
01072 #define BF_RTC_IER_TOIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TOIE) & BM_RTC_IER_TOIE)
01073 
01074 /*! @brief Set the TOIE field to a new value. */
01075 #define BW_RTC_IER_TOIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TOIE), v))
01076 /*@}*/
01077 
01078 /*!
01079  * @name Register RTC_IER, field TAIE[2] (RW)
01080  *
01081  * Values:
01082  * - 0 - Time alarm flag does not generate an interrupt.
01083  * - 1 - Time alarm flag does generate an interrupt.
01084  */
01085 /*@{*/
01086 #define BP_RTC_IER_TAIE      (2U)          /*!< Bit position for RTC_IER_TAIE. */
01087 #define BM_RTC_IER_TAIE      (0x00000004U) /*!< Bit mask for RTC_IER_TAIE. */
01088 #define BS_RTC_IER_TAIE      (1U)          /*!< Bit field size in bits for RTC_IER_TAIE. */
01089 
01090 /*! @brief Read current value of the RTC_IER_TAIE field. */
01091 #define BR_RTC_IER_TAIE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE)))
01092 
01093 /*! @brief Format value for bitfield RTC_IER_TAIE. */
01094 #define BF_RTC_IER_TAIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TAIE) & BM_RTC_IER_TAIE)
01095 
01096 /*! @brief Set the TAIE field to a new value. */
01097 #define BW_RTC_IER_TAIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TAIE), v))
01098 /*@}*/
01099 
01100 /*!
01101  * @name Register RTC_IER, field TSIE[4] (RW)
01102  *
01103  * The seconds interrupt is an edge-sensitive interrupt with a dedicated
01104  * interrupt vector. It is generated once a second and requires no software overhead
01105  * (there is no corresponding status flag to clear).
01106  *
01107  * Values:
01108  * - 0 - Seconds interrupt is disabled.
01109  * - 1 - Seconds interrupt is enabled.
01110  */
01111 /*@{*/
01112 #define BP_RTC_IER_TSIE      (4U)          /*!< Bit position for RTC_IER_TSIE. */
01113 #define BM_RTC_IER_TSIE      (0x00000010U) /*!< Bit mask for RTC_IER_TSIE. */
01114 #define BS_RTC_IER_TSIE      (1U)          /*!< Bit field size in bits for RTC_IER_TSIE. */
01115 
01116 /*! @brief Read current value of the RTC_IER_TSIE field. */
01117 #define BR_RTC_IER_TSIE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE)))
01118 
01119 /*! @brief Format value for bitfield RTC_IER_TSIE. */
01120 #define BF_RTC_IER_TSIE(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_TSIE) & BM_RTC_IER_TSIE)
01121 
01122 /*! @brief Set the TSIE field to a new value. */
01123 #define BW_RTC_IER_TSIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_TSIE), v))
01124 /*@}*/
01125 
01126 /*!
01127  * @name Register RTC_IER, field WPON[7] (RW)
01128  *
01129  * The wakeup pin is optional and not available on all devices. Whenever the
01130  * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
01131  *
01132  * Values:
01133  * - 0 - No effect.
01134  * - 1 - If the wakeup pin is enabled, then the wakeup pin will assert.
01135  */
01136 /*@{*/
01137 #define BP_RTC_IER_WPON      (7U)          /*!< Bit position for RTC_IER_WPON. */
01138 #define BM_RTC_IER_WPON      (0x00000080U) /*!< Bit mask for RTC_IER_WPON. */
01139 #define BS_RTC_IER_WPON      (1U)          /*!< Bit field size in bits for RTC_IER_WPON. */
01140 
01141 /*! @brief Read current value of the RTC_IER_WPON field. */
01142 #define BR_RTC_IER_WPON(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON)))
01143 
01144 /*! @brief Format value for bitfield RTC_IER_WPON. */
01145 #define BF_RTC_IER_WPON(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_IER_WPON) & BM_RTC_IER_WPON)
01146 
01147 /*! @brief Set the WPON field to a new value. */
01148 #define BW_RTC_IER_WPON(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_IER_ADDR(x), BP_RTC_IER_WPON), v))
01149 /*@}*/
01150 
01151 /*******************************************************************************
01152  * HW_RTC_WAR - RTC Write Access Register
01153  ******************************************************************************/
01154 
01155 /*!
01156  * @brief HW_RTC_WAR - RTC Write Access Register (RW)
01157  *
01158  * Reset value: 0x000000FFU
01159  */
01160 typedef union _hw_rtc_war
01161 {
01162     uint32_t U;
01163     struct _hw_rtc_war_bitfields
01164     {
01165         uint32_t TSRW : 1;             /*!< [0] Time Seconds Register Write */
01166         uint32_t TPRW : 1;             /*!< [1] Time Prescaler Register Write */
01167         uint32_t TARW : 1;             /*!< [2] Time Alarm Register Write */
01168         uint32_t TCRW : 1;             /*!< [3] Time Compensation Register Write */
01169         uint32_t CRW : 1;              /*!< [4] Control Register Write */
01170         uint32_t SRW : 1;              /*!< [5] Status Register Write */
01171         uint32_t LRW : 1;              /*!< [6] Lock Register Write */
01172         uint32_t IERW : 1;             /*!< [7] Interrupt Enable Register Write */
01173         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01174     } B;
01175 } hw_rtc_war_t;
01176 
01177 /*!
01178  * @name Constants and macros for entire RTC_WAR register
01179  */
01180 /*@{*/
01181 #define HW_RTC_WAR_ADDR(x)       ((x) + 0x800U)
01182 
01183 #define HW_RTC_WAR(x)            (*(__IO hw_rtc_war_t *) HW_RTC_WAR_ADDR(x))
01184 #define HW_RTC_WAR_RD(x)         (ADDRESS_READ(hw_rtc_war_t, HW_RTC_WAR_ADDR(x)))
01185 #define HW_RTC_WAR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_war_t, HW_RTC_WAR_ADDR(x), v))
01186 #define HW_RTC_WAR_SET(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) |  (v)))
01187 #define HW_RTC_WAR_CLR(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) & ~(v)))
01188 #define HW_RTC_WAR_TOG(x, v)     (HW_RTC_WAR_WR(x, HW_RTC_WAR_RD(x) ^  (v)))
01189 /*@}*/
01190 
01191 /*
01192  * Constants & macros for individual RTC_WAR bitfields
01193  */
01194 
01195 /*!
01196  * @name Register RTC_WAR, field TSRW[0] (RW)
01197  *
01198  * After being cleared, this bit is set only by system reset. It is not affected
01199  * by VBAT POR or software reset.
01200  *
01201  * Values:
01202  * - 0 - Writes to the Time Seconds Register are ignored.
01203  * - 1 - Writes to the Time Seconds Register complete as normal.
01204  */
01205 /*@{*/
01206 #define BP_RTC_WAR_TSRW      (0U)          /*!< Bit position for RTC_WAR_TSRW. */
01207 #define BM_RTC_WAR_TSRW      (0x00000001U) /*!< Bit mask for RTC_WAR_TSRW. */
01208 #define BS_RTC_WAR_TSRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TSRW. */
01209 
01210 /*! @brief Read current value of the RTC_WAR_TSRW field. */
01211 #define BR_RTC_WAR_TSRW(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW)))
01212 
01213 /*! @brief Format value for bitfield RTC_WAR_TSRW. */
01214 #define BF_RTC_WAR_TSRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TSRW) & BM_RTC_WAR_TSRW)
01215 
01216 /*! @brief Set the TSRW field to a new value. */
01217 #define BW_RTC_WAR_TSRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TSRW), v))
01218 /*@}*/
01219 
01220 /*!
01221  * @name Register RTC_WAR, field TPRW[1] (RW)
01222  *
01223  * After being cleared, this bit is set only by system reset. It is not affected
01224  * by VBAT POR or software reset.
01225  *
01226  * Values:
01227  * - 0 - Writes to the Time Prescaler Register are ignored.
01228  * - 1 - Writes to the Time Prescaler Register complete as normal.
01229  */
01230 /*@{*/
01231 #define BP_RTC_WAR_TPRW      (1U)          /*!< Bit position for RTC_WAR_TPRW. */
01232 #define BM_RTC_WAR_TPRW      (0x00000002U) /*!< Bit mask for RTC_WAR_TPRW. */
01233 #define BS_RTC_WAR_TPRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TPRW. */
01234 
01235 /*! @brief Read current value of the RTC_WAR_TPRW field. */
01236 #define BR_RTC_WAR_TPRW(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW)))
01237 
01238 /*! @brief Format value for bitfield RTC_WAR_TPRW. */
01239 #define BF_RTC_WAR_TPRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TPRW) & BM_RTC_WAR_TPRW)
01240 
01241 /*! @brief Set the TPRW field to a new value. */
01242 #define BW_RTC_WAR_TPRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TPRW), v))
01243 /*@}*/
01244 
01245 /*!
01246  * @name Register RTC_WAR, field TARW[2] (RW)
01247  *
01248  * After being cleared, this bit is set only by system reset. It is not affected
01249  * by VBAT POR or software reset.
01250  *
01251  * Values:
01252  * - 0 - Writes to the Time Alarm Register are ignored.
01253  * - 1 - Writes to the Time Alarm Register complete as normal.
01254  */
01255 /*@{*/
01256 #define BP_RTC_WAR_TARW      (2U)          /*!< Bit position for RTC_WAR_TARW. */
01257 #define BM_RTC_WAR_TARW      (0x00000004U) /*!< Bit mask for RTC_WAR_TARW. */
01258 #define BS_RTC_WAR_TARW      (1U)          /*!< Bit field size in bits for RTC_WAR_TARW. */
01259 
01260 /*! @brief Read current value of the RTC_WAR_TARW field. */
01261 #define BR_RTC_WAR_TARW(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW)))
01262 
01263 /*! @brief Format value for bitfield RTC_WAR_TARW. */
01264 #define BF_RTC_WAR_TARW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TARW) & BM_RTC_WAR_TARW)
01265 
01266 /*! @brief Set the TARW field to a new value. */
01267 #define BW_RTC_WAR_TARW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TARW), v))
01268 /*@}*/
01269 
01270 /*!
01271  * @name Register RTC_WAR, field TCRW[3] (RW)
01272  *
01273  * After being cleared, this bit is set only by system reset. It is not affected
01274  * by VBAT POR or software reset.
01275  *
01276  * Values:
01277  * - 0 - Writes to the Time Compensation Register are ignored.
01278  * - 1 - Writes to the Time Compensation Register complete as normal.
01279  */
01280 /*@{*/
01281 #define BP_RTC_WAR_TCRW      (3U)          /*!< Bit position for RTC_WAR_TCRW. */
01282 #define BM_RTC_WAR_TCRW      (0x00000008U) /*!< Bit mask for RTC_WAR_TCRW. */
01283 #define BS_RTC_WAR_TCRW      (1U)          /*!< Bit field size in bits for RTC_WAR_TCRW. */
01284 
01285 /*! @brief Read current value of the RTC_WAR_TCRW field. */
01286 #define BR_RTC_WAR_TCRW(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW)))
01287 
01288 /*! @brief Format value for bitfield RTC_WAR_TCRW. */
01289 #define BF_RTC_WAR_TCRW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_TCRW) & BM_RTC_WAR_TCRW)
01290 
01291 /*! @brief Set the TCRW field to a new value. */
01292 #define BW_RTC_WAR_TCRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_TCRW), v))
01293 /*@}*/
01294 
01295 /*!
01296  * @name Register RTC_WAR, field CRW[4] (RW)
01297  *
01298  * After being cleared, this bit is set only by system reset. It is not affected
01299  * by VBAT POR or software reset.
01300  *
01301  * Values:
01302  * - 0 - Writes to the Control Register are ignored.
01303  * - 1 - Writes to the Control Register complete as normal.
01304  */
01305 /*@{*/
01306 #define BP_RTC_WAR_CRW       (4U)          /*!< Bit position for RTC_WAR_CRW. */
01307 #define BM_RTC_WAR_CRW       (0x00000010U) /*!< Bit mask for RTC_WAR_CRW. */
01308 #define BS_RTC_WAR_CRW       (1U)          /*!< Bit field size in bits for RTC_WAR_CRW. */
01309 
01310 /*! @brief Read current value of the RTC_WAR_CRW field. */
01311 #define BR_RTC_WAR_CRW(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW)))
01312 
01313 /*! @brief Format value for bitfield RTC_WAR_CRW. */
01314 #define BF_RTC_WAR_CRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_CRW) & BM_RTC_WAR_CRW)
01315 
01316 /*! @brief Set the CRW field to a new value. */
01317 #define BW_RTC_WAR_CRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_CRW), v))
01318 /*@}*/
01319 
01320 /*!
01321  * @name Register RTC_WAR, field SRW[5] (RW)
01322  *
01323  * After being cleared, this bit is set only by system reset. It is not affected
01324  * by VBAT POR or software reset.
01325  *
01326  * Values:
01327  * - 0 - Writes to the Status Register are ignored.
01328  * - 1 - Writes to the Status Register complete as normal.
01329  */
01330 /*@{*/
01331 #define BP_RTC_WAR_SRW       (5U)          /*!< Bit position for RTC_WAR_SRW. */
01332 #define BM_RTC_WAR_SRW       (0x00000020U) /*!< Bit mask for RTC_WAR_SRW. */
01333 #define BS_RTC_WAR_SRW       (1U)          /*!< Bit field size in bits for RTC_WAR_SRW. */
01334 
01335 /*! @brief Read current value of the RTC_WAR_SRW field. */
01336 #define BR_RTC_WAR_SRW(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW)))
01337 
01338 /*! @brief Format value for bitfield RTC_WAR_SRW. */
01339 #define BF_RTC_WAR_SRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_SRW) & BM_RTC_WAR_SRW)
01340 
01341 /*! @brief Set the SRW field to a new value. */
01342 #define BW_RTC_WAR_SRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_SRW), v))
01343 /*@}*/
01344 
01345 /*!
01346  * @name Register RTC_WAR, field LRW[6] (RW)
01347  *
01348  * After being cleared, this bit is set only by system reset. It is not affected
01349  * by VBAT POR or software reset.
01350  *
01351  * Values:
01352  * - 0 - Writes to the Lock Register are ignored.
01353  * - 1 - Writes to the Lock Register complete as normal.
01354  */
01355 /*@{*/
01356 #define BP_RTC_WAR_LRW       (6U)          /*!< Bit position for RTC_WAR_LRW. */
01357 #define BM_RTC_WAR_LRW       (0x00000040U) /*!< Bit mask for RTC_WAR_LRW. */
01358 #define BS_RTC_WAR_LRW       (1U)          /*!< Bit field size in bits for RTC_WAR_LRW. */
01359 
01360 /*! @brief Read current value of the RTC_WAR_LRW field. */
01361 #define BR_RTC_WAR_LRW(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW)))
01362 
01363 /*! @brief Format value for bitfield RTC_WAR_LRW. */
01364 #define BF_RTC_WAR_LRW(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_LRW) & BM_RTC_WAR_LRW)
01365 
01366 /*! @brief Set the LRW field to a new value. */
01367 #define BW_RTC_WAR_LRW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_LRW), v))
01368 /*@}*/
01369 
01370 /*!
01371  * @name Register RTC_WAR, field IERW[7] (RW)
01372  *
01373  * After being cleared, this bit is set only by system reset. It is not affected
01374  * by VBAT POR or software reset.
01375  *
01376  * Values:
01377  * - 0 - Writes to the Interupt Enable Register are ignored.
01378  * - 1 - Writes to the Interrupt Enable Register complete as normal.
01379  */
01380 /*@{*/
01381 #define BP_RTC_WAR_IERW      (7U)          /*!< Bit position for RTC_WAR_IERW. */
01382 #define BM_RTC_WAR_IERW      (0x00000080U) /*!< Bit mask for RTC_WAR_IERW. */
01383 #define BS_RTC_WAR_IERW      (1U)          /*!< Bit field size in bits for RTC_WAR_IERW. */
01384 
01385 /*! @brief Read current value of the RTC_WAR_IERW field. */
01386 #define BR_RTC_WAR_IERW(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW)))
01387 
01388 /*! @brief Format value for bitfield RTC_WAR_IERW. */
01389 #define BF_RTC_WAR_IERW(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_WAR_IERW) & BM_RTC_WAR_IERW)
01390 
01391 /*! @brief Set the IERW field to a new value. */
01392 #define BW_RTC_WAR_IERW(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_WAR_ADDR(x), BP_RTC_WAR_IERW), v))
01393 /*@}*/
01394 
01395 /*******************************************************************************
01396  * HW_RTC_RAR - RTC Read Access Register
01397  ******************************************************************************/
01398 
01399 /*!
01400  * @brief HW_RTC_RAR - RTC Read Access Register (RW)
01401  *
01402  * Reset value: 0x000000FFU
01403  */
01404 typedef union _hw_rtc_rar
01405 {
01406     uint32_t U;
01407     struct _hw_rtc_rar_bitfields
01408     {
01409         uint32_t TSRR : 1;             /*!< [0] Time Seconds Register Read */
01410         uint32_t TPRR : 1;             /*!< [1] Time Prescaler Register Read */
01411         uint32_t TARR : 1;             /*!< [2] Time Alarm Register Read */
01412         uint32_t TCRR : 1;             /*!< [3] Time Compensation Register Read */
01413         uint32_t CRR : 1;              /*!< [4] Control Register Read */
01414         uint32_t SRR : 1;              /*!< [5] Status Register Read */
01415         uint32_t LRR : 1;              /*!< [6] Lock Register Read */
01416         uint32_t IERR : 1;             /*!< [7] Interrupt Enable Register Read */
01417         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01418     } B;
01419 } hw_rtc_rar_t;
01420 
01421 /*!
01422  * @name Constants and macros for entire RTC_RAR register
01423  */
01424 /*@{*/
01425 #define HW_RTC_RAR_ADDR(x)       ((x) + 0x804U)
01426 
01427 #define HW_RTC_RAR(x)            (*(__IO hw_rtc_rar_t *) HW_RTC_RAR_ADDR(x))
01428 #define HW_RTC_RAR_RD(x)         (ADDRESS_READ(hw_rtc_rar_t, HW_RTC_RAR_ADDR(x)))
01429 #define HW_RTC_RAR_WR(x, v)      (ADDRESS_WRITE(hw_rtc_rar_t, HW_RTC_RAR_ADDR(x), v))
01430 #define HW_RTC_RAR_SET(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) |  (v)))
01431 #define HW_RTC_RAR_CLR(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) & ~(v)))
01432 #define HW_RTC_RAR_TOG(x, v)     (HW_RTC_RAR_WR(x, HW_RTC_RAR_RD(x) ^  (v)))
01433 /*@}*/
01434 
01435 /*
01436  * Constants & macros for individual RTC_RAR bitfields
01437  */
01438 
01439 /*!
01440  * @name Register RTC_RAR, field TSRR[0] (RW)
01441  *
01442  * After being cleared, this bit is set only by system reset. It is not affected
01443  * by VBAT POR or software reset.
01444  *
01445  * Values:
01446  * - 0 - Reads to the Time Seconds Register are ignored.
01447  * - 1 - Reads to the Time Seconds Register complete as normal.
01448  */
01449 /*@{*/
01450 #define BP_RTC_RAR_TSRR      (0U)          /*!< Bit position for RTC_RAR_TSRR. */
01451 #define BM_RTC_RAR_TSRR      (0x00000001U) /*!< Bit mask for RTC_RAR_TSRR. */
01452 #define BS_RTC_RAR_TSRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TSRR. */
01453 
01454 /*! @brief Read current value of the RTC_RAR_TSRR field. */
01455 #define BR_RTC_RAR_TSRR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR)))
01456 
01457 /*! @brief Format value for bitfield RTC_RAR_TSRR. */
01458 #define BF_RTC_RAR_TSRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TSRR) & BM_RTC_RAR_TSRR)
01459 
01460 /*! @brief Set the TSRR field to a new value. */
01461 #define BW_RTC_RAR_TSRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TSRR), v))
01462 /*@}*/
01463 
01464 /*!
01465  * @name Register RTC_RAR, field TPRR[1] (RW)
01466  *
01467  * After being cleared, this bit is set only by system reset. It is not affected
01468  * by VBAT POR or software reset.
01469  *
01470  * Values:
01471  * - 0 - Reads to the Time Pprescaler Register are ignored.
01472  * - 1 - Reads to the Time Prescaler Register complete as normal.
01473  */
01474 /*@{*/
01475 #define BP_RTC_RAR_TPRR      (1U)          /*!< Bit position for RTC_RAR_TPRR. */
01476 #define BM_RTC_RAR_TPRR      (0x00000002U) /*!< Bit mask for RTC_RAR_TPRR. */
01477 #define BS_RTC_RAR_TPRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TPRR. */
01478 
01479 /*! @brief Read current value of the RTC_RAR_TPRR field. */
01480 #define BR_RTC_RAR_TPRR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR)))
01481 
01482 /*! @brief Format value for bitfield RTC_RAR_TPRR. */
01483 #define BF_RTC_RAR_TPRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TPRR) & BM_RTC_RAR_TPRR)
01484 
01485 /*! @brief Set the TPRR field to a new value. */
01486 #define BW_RTC_RAR_TPRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TPRR), v))
01487 /*@}*/
01488 
01489 /*!
01490  * @name Register RTC_RAR, field TARR[2] (RW)
01491  *
01492  * After being cleared, this bit is set only by system reset. It is not affected
01493  * by VBAT POR or software reset.
01494  *
01495  * Values:
01496  * - 0 - Reads to the Time Alarm Register are ignored.
01497  * - 1 - Reads to the Time Alarm Register complete as normal.
01498  */
01499 /*@{*/
01500 #define BP_RTC_RAR_TARR      (2U)          /*!< Bit position for RTC_RAR_TARR. */
01501 #define BM_RTC_RAR_TARR      (0x00000004U) /*!< Bit mask for RTC_RAR_TARR. */
01502 #define BS_RTC_RAR_TARR      (1U)          /*!< Bit field size in bits for RTC_RAR_TARR. */
01503 
01504 /*! @brief Read current value of the RTC_RAR_TARR field. */
01505 #define BR_RTC_RAR_TARR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR)))
01506 
01507 /*! @brief Format value for bitfield RTC_RAR_TARR. */
01508 #define BF_RTC_RAR_TARR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TARR) & BM_RTC_RAR_TARR)
01509 
01510 /*! @brief Set the TARR field to a new value. */
01511 #define BW_RTC_RAR_TARR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TARR), v))
01512 /*@}*/
01513 
01514 /*!
01515  * @name Register RTC_RAR, field TCRR[3] (RW)
01516  *
01517  * After being cleared, this bit is set only by system reset. It is not affected
01518  * by VBAT POR or software reset.
01519  *
01520  * Values:
01521  * - 0 - Reads to the Time Compensation Register are ignored.
01522  * - 1 - Reads to the Time Compensation Register complete as normal.
01523  */
01524 /*@{*/
01525 #define BP_RTC_RAR_TCRR      (3U)          /*!< Bit position for RTC_RAR_TCRR. */
01526 #define BM_RTC_RAR_TCRR      (0x00000008U) /*!< Bit mask for RTC_RAR_TCRR. */
01527 #define BS_RTC_RAR_TCRR      (1U)          /*!< Bit field size in bits for RTC_RAR_TCRR. */
01528 
01529 /*! @brief Read current value of the RTC_RAR_TCRR field. */
01530 #define BR_RTC_RAR_TCRR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR)))
01531 
01532 /*! @brief Format value for bitfield RTC_RAR_TCRR. */
01533 #define BF_RTC_RAR_TCRR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_TCRR) & BM_RTC_RAR_TCRR)
01534 
01535 /*! @brief Set the TCRR field to a new value. */
01536 #define BW_RTC_RAR_TCRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_TCRR), v))
01537 /*@}*/
01538 
01539 /*!
01540  * @name Register RTC_RAR, field CRR[4] (RW)
01541  *
01542  * After being cleared, this bit is set only by system reset. It is not affected
01543  * by VBAT POR or software reset.
01544  *
01545  * Values:
01546  * - 0 - Reads to the Control Register are ignored.
01547  * - 1 - Reads to the Control Register complete as normal.
01548  */
01549 /*@{*/
01550 #define BP_RTC_RAR_CRR       (4U)          /*!< Bit position for RTC_RAR_CRR. */
01551 #define BM_RTC_RAR_CRR       (0x00000010U) /*!< Bit mask for RTC_RAR_CRR. */
01552 #define BS_RTC_RAR_CRR       (1U)          /*!< Bit field size in bits for RTC_RAR_CRR. */
01553 
01554 /*! @brief Read current value of the RTC_RAR_CRR field. */
01555 #define BR_RTC_RAR_CRR(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR)))
01556 
01557 /*! @brief Format value for bitfield RTC_RAR_CRR. */
01558 #define BF_RTC_RAR_CRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_CRR) & BM_RTC_RAR_CRR)
01559 
01560 /*! @brief Set the CRR field to a new value. */
01561 #define BW_RTC_RAR_CRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_CRR), v))
01562 /*@}*/
01563 
01564 /*!
01565  * @name Register RTC_RAR, field SRR[5] (RW)
01566  *
01567  * After being cleared, this bit is set only by system reset. It is not affected
01568  * by VBAT POR or software reset.
01569  *
01570  * Values:
01571  * - 0 - Reads to the Status Register are ignored.
01572  * - 1 - Reads to the Status Register complete as normal.
01573  */
01574 /*@{*/
01575 #define BP_RTC_RAR_SRR       (5U)          /*!< Bit position for RTC_RAR_SRR. */
01576 #define BM_RTC_RAR_SRR       (0x00000020U) /*!< Bit mask for RTC_RAR_SRR. */
01577 #define BS_RTC_RAR_SRR       (1U)          /*!< Bit field size in bits for RTC_RAR_SRR. */
01578 
01579 /*! @brief Read current value of the RTC_RAR_SRR field. */
01580 #define BR_RTC_RAR_SRR(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR)))
01581 
01582 /*! @brief Format value for bitfield RTC_RAR_SRR. */
01583 #define BF_RTC_RAR_SRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_SRR) & BM_RTC_RAR_SRR)
01584 
01585 /*! @brief Set the SRR field to a new value. */
01586 #define BW_RTC_RAR_SRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_SRR), v))
01587 /*@}*/
01588 
01589 /*!
01590  * @name Register RTC_RAR, field LRR[6] (RW)
01591  *
01592  * After being cleared, this bit is set only by system reset. It is not affected
01593  * by VBAT POR or software reset.
01594  *
01595  * Values:
01596  * - 0 - Reads to the Lock Register are ignored.
01597  * - 1 - Reads to the Lock Register complete as normal.
01598  */
01599 /*@{*/
01600 #define BP_RTC_RAR_LRR       (6U)          /*!< Bit position for RTC_RAR_LRR. */
01601 #define BM_RTC_RAR_LRR       (0x00000040U) /*!< Bit mask for RTC_RAR_LRR. */
01602 #define BS_RTC_RAR_LRR       (1U)          /*!< Bit field size in bits for RTC_RAR_LRR. */
01603 
01604 /*! @brief Read current value of the RTC_RAR_LRR field. */
01605 #define BR_RTC_RAR_LRR(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR)))
01606 
01607 /*! @brief Format value for bitfield RTC_RAR_LRR. */
01608 #define BF_RTC_RAR_LRR(v)    ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_LRR) & BM_RTC_RAR_LRR)
01609 
01610 /*! @brief Set the LRR field to a new value. */
01611 #define BW_RTC_RAR_LRR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_LRR), v))
01612 /*@}*/
01613 
01614 /*!
01615  * @name Register RTC_RAR, field IERR[7] (RW)
01616  *
01617  * After being cleared, this bit is set only by system reset. It is not affected
01618  * by VBAT POR or software reset.
01619  *
01620  * Values:
01621  * - 0 - Reads to the Interrupt Enable Register are ignored.
01622  * - 1 - Reads to the Interrupt Enable Register complete as normal.
01623  */
01624 /*@{*/
01625 #define BP_RTC_RAR_IERR      (7U)          /*!< Bit position for RTC_RAR_IERR. */
01626 #define BM_RTC_RAR_IERR      (0x00000080U) /*!< Bit mask for RTC_RAR_IERR. */
01627 #define BS_RTC_RAR_IERR      (1U)          /*!< Bit field size in bits for RTC_RAR_IERR. */
01628 
01629 /*! @brief Read current value of the RTC_RAR_IERR field. */
01630 #define BR_RTC_RAR_IERR(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR)))
01631 
01632 /*! @brief Format value for bitfield RTC_RAR_IERR. */
01633 #define BF_RTC_RAR_IERR(v)   ((uint32_t)((uint32_t)(v) << BP_RTC_RAR_IERR) & BM_RTC_RAR_IERR)
01634 
01635 /*! @brief Set the IERR field to a new value. */
01636 #define BW_RTC_RAR_IERR(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RTC_RAR_ADDR(x), BP_RTC_RAR_IERR), v))
01637 /*@}*/
01638 
01639 /*******************************************************************************
01640  * hw_rtc_t - module struct
01641  ******************************************************************************/
01642 /*!
01643  * @brief All RTC module registers.
01644  */
01645 #pragma pack(1)
01646 typedef struct _hw_rtc
01647 {
01648     __IO hw_rtc_tsr_t TSR ;                 /*!< [0x0] RTC Time Seconds Register */
01649     __IO hw_rtc_tpr_t TPR ;                 /*!< [0x4] RTC Time Prescaler Register */
01650     __IO hw_rtc_tar_t TAR ;                 /*!< [0x8] RTC Time Alarm Register */
01651     __IO hw_rtc_tcr_t TCR ;                 /*!< [0xC] RTC Time Compensation Register */
01652     __IO hw_rtc_cr_t CR ;                   /*!< [0x10] RTC Control Register */
01653     __IO hw_rtc_sr_t SR ;                   /*!< [0x14] RTC Status Register */
01654     __IO hw_rtc_lr_t LR ;                   /*!< [0x18] RTC Lock Register */
01655     __IO hw_rtc_ier_t IER ;                 /*!< [0x1C] RTC Interrupt Enable Register */
01656     uint8_t _reserved0[2016];
01657     __IO hw_rtc_war_t WAR ;                 /*!< [0x800] RTC Write Access Register */
01658     __IO hw_rtc_rar_t RAR ;                 /*!< [0x804] RTC Read Access Register */
01659 } hw_rtc_t;
01660 #pragma pack()
01661 
01662 /*! @brief Macro to access all RTC registers. */
01663 /*! @param x RTC module instance base address. */
01664 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01665  *     use the '&' operator, like <code>&HW_RTC(RTC_BASE)</code>. */
01666 #define HW_RTC(x)      (*(hw_rtc_t *)(x))
01667 
01668 #endif /* __HW_RTC_REGISTERS_H__ */
01669 /* EOF */