MK64F12_rng.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_RNG_REGISTERS_H__
00088 #define __HW_RNG_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 RNG
00095  *
00096  * Random Number Generator Accelerator
00097  *
00098  * Registers defined in this header file:
00099  * - HW_RNG_CR - RNGA Control Register
00100  * - HW_RNG_SR - RNGA Status Register
00101  * - HW_RNG_ER - RNGA Entropy Register
00102  * - HW_RNG_OR - RNGA Output Register
00103  *
00104  * - hw_rng_t - Struct containing all module registers.
00105  */
00106 
00107 #define HW_RNG_INSTANCE_COUNT (1U) /*!< Number of instances of the RNG module. */
00108 
00109 /*******************************************************************************
00110  * HW_RNG_CR - RNGA Control Register
00111  ******************************************************************************/
00112 
00113 /*!
00114  * @brief HW_RNG_CR - RNGA Control Register (RW)
00115  *
00116  * Reset value: 0x00000000U
00117  *
00118  * Controls the operation of RNGA.
00119  */
00120 typedef union _hw_rng_cr
00121 {
00122     uint32_t U;
00123     struct _hw_rng_cr_bitfields
00124     {
00125         uint32_t GO : 1;               /*!< [0] Go */
00126         uint32_t HA : 1;               /*!< [1] High Assurance */
00127         uint32_t INTM : 1;             /*!< [2] Interrupt Mask */
00128         uint32_t CLRI : 1;             /*!< [3] Clear Interrupt */
00129         uint32_t SLP : 1;              /*!< [4] Sleep */
00130         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
00131     } B;
00132 } hw_rng_cr_t;
00133 
00134 /*!
00135  * @name Constants and macros for entire RNG_CR register
00136  */
00137 /*@{*/
00138 #define HW_RNG_CR_ADDR(x)        ((x) + 0x0U)
00139 
00140 #define HW_RNG_CR(x)             (*(__IO hw_rng_cr_t *) HW_RNG_CR_ADDR(x))
00141 #define HW_RNG_CR_RD(x)          (ADDRESS_READ(hw_rng_cr_t, HW_RNG_CR_ADDR(x)))
00142 #define HW_RNG_CR_WR(x, v)       (ADDRESS_WRITE(hw_rng_cr_t, HW_RNG_CR_ADDR(x), v))
00143 #define HW_RNG_CR_SET(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) |  (v)))
00144 #define HW_RNG_CR_CLR(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) & ~(v)))
00145 #define HW_RNG_CR_TOG(x, v)      (HW_RNG_CR_WR(x, HW_RNG_CR_RD(x) ^  (v)))
00146 /*@}*/
00147 
00148 /*
00149  * Constants & macros for individual RNG_CR bitfields
00150  */
00151 
00152 /*!
00153  * @name Register RNG_CR, field GO[0] (RW)
00154  *
00155  * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
00156  * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
00157  * OR[RANDOUT] with data.
00158  *
00159  * Values:
00160  * - 0 - Disabled
00161  * - 1 - Enabled
00162  */
00163 /*@{*/
00164 #define BP_RNG_CR_GO         (0U)          /*!< Bit position for RNG_CR_GO. */
00165 #define BM_RNG_CR_GO         (0x00000001U) /*!< Bit mask for RNG_CR_GO. */
00166 #define BS_RNG_CR_GO         (1U)          /*!< Bit field size in bits for RNG_CR_GO. */
00167 
00168 /*! @brief Read current value of the RNG_CR_GO field. */
00169 #define BR_RNG_CR_GO(x)      (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO)))
00170 
00171 /*! @brief Format value for bitfield RNG_CR_GO. */
00172 #define BF_RNG_CR_GO(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_GO) & BM_RNG_CR_GO)
00173 
00174 /*! @brief Set the GO field to a new value. */
00175 #define BW_RNG_CR_GO(x, v)   (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_GO), v))
00176 /*@}*/
00177 
00178 /*!
00179  * @name Register RNG_CR, field HA[1] (RW)
00180  *
00181  * Enables notification of security violations (via SR[SECV]). A security
00182  * violation occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0. This field is sticky.
00183  * After enabling notification of security violations, you must reset RNGA to
00184  * disable them again.
00185  *
00186  * Values:
00187  * - 0 - Disabled
00188  * - 1 - Enabled
00189  */
00190 /*@{*/
00191 #define BP_RNG_CR_HA         (1U)          /*!< Bit position for RNG_CR_HA. */
00192 #define BM_RNG_CR_HA         (0x00000002U) /*!< Bit mask for RNG_CR_HA. */
00193 #define BS_RNG_CR_HA         (1U)          /*!< Bit field size in bits for RNG_CR_HA. */
00194 
00195 /*! @brief Read current value of the RNG_CR_HA field. */
00196 #define BR_RNG_CR_HA(x)      (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA)))
00197 
00198 /*! @brief Format value for bitfield RNG_CR_HA. */
00199 #define BF_RNG_CR_HA(v)      ((uint32_t)((uint32_t)(v) << BP_RNG_CR_HA) & BM_RNG_CR_HA)
00200 
00201 /*! @brief Set the HA field to a new value. */
00202 #define BW_RNG_CR_HA(x, v)   (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_HA), v))
00203 /*@}*/
00204 
00205 /*!
00206  * @name Register RNG_CR, field INTM[2] (RW)
00207  *
00208  * Masks the triggering of an error interrupt to the interrupt controller when
00209  * an OR underflow condition occurs. An OR underflow condition occurs when you
00210  * read OR[RANDOUT] and SR[OREG_LVL]=0. See the Output Register (OR) description.
00211  *
00212  * Values:
00213  * - 0 - Not masked
00214  * - 1 - Masked
00215  */
00216 /*@{*/
00217 #define BP_RNG_CR_INTM       (2U)          /*!< Bit position for RNG_CR_INTM. */
00218 #define BM_RNG_CR_INTM       (0x00000004U) /*!< Bit mask for RNG_CR_INTM. */
00219 #define BS_RNG_CR_INTM       (1U)          /*!< Bit field size in bits for RNG_CR_INTM. */
00220 
00221 /*! @brief Read current value of the RNG_CR_INTM field. */
00222 #define BR_RNG_CR_INTM(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM)))
00223 
00224 /*! @brief Format value for bitfield RNG_CR_INTM. */
00225 #define BF_RNG_CR_INTM(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_INTM) & BM_RNG_CR_INTM)
00226 
00227 /*! @brief Set the INTM field to a new value. */
00228 #define BW_RNG_CR_INTM(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_INTM), v))
00229 /*@}*/
00230 
00231 /*!
00232  * @name Register RNG_CR, field CLRI[3] (WORZ)
00233  *
00234  * Clears the interrupt by resetting the error-interrupt indicator (SR[ERRI]).
00235  *
00236  * Values:
00237  * - 0 - Do not clear the interrupt.
00238  * - 1 - Clear the interrupt. When you write 1 to this field, RNGA then resets
00239  *     the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
00240  */
00241 /*@{*/
00242 #define BP_RNG_CR_CLRI       (3U)          /*!< Bit position for RNG_CR_CLRI. */
00243 #define BM_RNG_CR_CLRI       (0x00000008U) /*!< Bit mask for RNG_CR_CLRI. */
00244 #define BS_RNG_CR_CLRI       (1U)          /*!< Bit field size in bits for RNG_CR_CLRI. */
00245 
00246 /*! @brief Format value for bitfield RNG_CR_CLRI. */
00247 #define BF_RNG_CR_CLRI(v)    ((uint32_t)((uint32_t)(v) << BP_RNG_CR_CLRI) & BM_RNG_CR_CLRI)
00248 
00249 /*! @brief Set the CLRI field to a new value. */
00250 #define BW_RNG_CR_CLRI(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_CLRI), v))
00251 /*@}*/
00252 
00253 /*!
00254  * @name Register RNG_CR, field SLP[4] (RW)
00255  *
00256  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
00257  * mode by asserting the DOZE signal.
00258  *
00259  * Values:
00260  * - 0 - Normal mode
00261  * - 1 - Sleep (low-power) mode
00262  */
00263 /*@{*/
00264 #define BP_RNG_CR_SLP        (4U)          /*!< Bit position for RNG_CR_SLP. */
00265 #define BM_RNG_CR_SLP        (0x00000010U) /*!< Bit mask for RNG_CR_SLP. */
00266 #define BS_RNG_CR_SLP        (1U)          /*!< Bit field size in bits for RNG_CR_SLP. */
00267 
00268 /*! @brief Read current value of the RNG_CR_SLP field. */
00269 #define BR_RNG_CR_SLP(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP)))
00270 
00271 /*! @brief Format value for bitfield RNG_CR_SLP. */
00272 #define BF_RNG_CR_SLP(v)     ((uint32_t)((uint32_t)(v) << BP_RNG_CR_SLP) & BM_RNG_CR_SLP)
00273 
00274 /*! @brief Set the SLP field to a new value. */
00275 #define BW_RNG_CR_SLP(x, v)  (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_RNG_CR_ADDR(x), BP_RNG_CR_SLP), v))
00276 /*@}*/
00277 
00278 /*******************************************************************************
00279  * HW_RNG_SR - RNGA Status Register
00280  ******************************************************************************/
00281 
00282 /*!
00283  * @brief HW_RNG_SR - RNGA Status Register (RO)
00284  *
00285  * Reset value: 0x00010000U
00286  *
00287  * Indicates the status of RNGA. This register is read-only.
00288  */
00289 typedef union _hw_rng_sr
00290 {
00291     uint32_t U;
00292     struct _hw_rng_sr_bitfields
00293     {
00294         uint32_t SECV : 1;             /*!< [0] Security Violation */
00295         uint32_t LRS : 1;              /*!< [1] Last Read Status */
00296         uint32_t ORU : 1;              /*!< [2] Output Register Underflow */
00297         uint32_t ERRI : 1;             /*!< [3] Error Interrupt */
00298         uint32_t SLP : 1;              /*!< [4] Sleep */
00299         uint32_t RESERVED0 : 3;        /*!< [7:5]  */
00300         uint32_t OREG_LVL : 8;         /*!< [15:8] Output Register Level */
00301         uint32_t OREG_SIZE : 8;        /*!< [23:16] Output Register Size */
00302         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
00303     } B;
00304 } hw_rng_sr_t;
00305 
00306 /*!
00307  * @name Constants and macros for entire RNG_SR register
00308  */
00309 /*@{*/
00310 #define HW_RNG_SR_ADDR(x)        ((x) + 0x4U)
00311 
00312 #define HW_RNG_SR(x)             (*(__I hw_rng_sr_t *) HW_RNG_SR_ADDR(x))
00313 #define HW_RNG_SR_RD(x)          (ADDRESS_READ(hw_rng_sr_t, HW_RNG_SR_ADDR(x)))
00314 /*@}*/
00315 
00316 /*
00317  * Constants & macros for individual RNG_SR bitfields
00318  */
00319 
00320 /*!
00321  * @name Register RNG_SR, field SECV[0] (RO)
00322  *
00323  * Used only when high assurance is enabled (CR[HA]). Indicates that a security
00324  * violation has occurred.This field is sticky. To clear SR[SECV], you must reset
00325  * RNGA.
00326  *
00327  * Values:
00328  * - 0 - No security violation
00329  * - 1 - Security violation
00330  */
00331 /*@{*/
00332 #define BP_RNG_SR_SECV       (0U)          /*!< Bit position for RNG_SR_SECV. */
00333 #define BM_RNG_SR_SECV       (0x00000001U) /*!< Bit mask for RNG_SR_SECV. */
00334 #define BS_RNG_SR_SECV       (1U)          /*!< Bit field size in bits for RNG_SR_SECV. */
00335 
00336 /*! @brief Read current value of the RNG_SR_SECV field. */
00337 #define BR_RNG_SR_SECV(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SECV)))
00338 /*@}*/
00339 
00340 /*!
00341  * @name Register RNG_SR, field LRS[1] (RO)
00342  *
00343  * Indicates whether the most recent read of OR[RANDOUT] caused an OR underflow
00344  * condition, regardless of whether the error interrupt is masked (CR[INTM]). An
00345  * OR underflow condition occurs when you read OR[RANDOUT] and SR[OREG_LVL]=0.
00346  * After you read this register, RNGA writes 0 to this field.
00347  *
00348  * Values:
00349  * - 0 - No underflow
00350  * - 1 - Underflow
00351  */
00352 /*@{*/
00353 #define BP_RNG_SR_LRS        (1U)          /*!< Bit position for RNG_SR_LRS. */
00354 #define BM_RNG_SR_LRS        (0x00000002U) /*!< Bit mask for RNG_SR_LRS. */
00355 #define BS_RNG_SR_LRS        (1U)          /*!< Bit field size in bits for RNG_SR_LRS. */
00356 
00357 /*! @brief Read current value of the RNG_SR_LRS field. */
00358 #define BR_RNG_SR_LRS(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_LRS)))
00359 /*@}*/
00360 
00361 /*!
00362  * @name Register RNG_SR, field ORU[2] (RO)
00363  *
00364  * Indicates whether an OR underflow condition has occurred since you last read
00365  * this register (SR) or RNGA was reset, regardless of whether the error
00366  * interrupt is masked (CR[INTM]). An OR underflow condition occurs when you read
00367  * OR[RANDOUT] and SR[OREG_LVL]=0. After you read this register, RNGA writes 0 to this
00368  * field.
00369  *
00370  * Values:
00371  * - 0 - No underflow
00372  * - 1 - Underflow
00373  */
00374 /*@{*/
00375 #define BP_RNG_SR_ORU        (2U)          /*!< Bit position for RNG_SR_ORU. */
00376 #define BM_RNG_SR_ORU        (0x00000004U) /*!< Bit mask for RNG_SR_ORU. */
00377 #define BS_RNG_SR_ORU        (1U)          /*!< Bit field size in bits for RNG_SR_ORU. */
00378 
00379 /*! @brief Read current value of the RNG_SR_ORU field. */
00380 #define BR_RNG_SR_ORU(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ORU)))
00381 /*@}*/
00382 
00383 /*!
00384  * @name Register RNG_SR, field ERRI[3] (RO)
00385  *
00386  * Indicates whether an OR underflow condition has occurred since you last
00387  * cleared the error interrupt (CR[CLRI]) or RNGA was reset, regardless of whether the
00388  * error interrupt is masked (CR[INTM]). An OR underflow condition occurs when
00389  * you read OR[RANDOUT] and SR[OREG_LVL]=0. After you reset the error-interrupt
00390  * indicator (via CR[CLRI]), RNGA writes 0 to this field.
00391  *
00392  * Values:
00393  * - 0 - No underflow
00394  * - 1 - Underflow
00395  */
00396 /*@{*/
00397 #define BP_RNG_SR_ERRI       (3U)          /*!< Bit position for RNG_SR_ERRI. */
00398 #define BM_RNG_SR_ERRI       (0x00000008U) /*!< Bit mask for RNG_SR_ERRI. */
00399 #define BS_RNG_SR_ERRI       (1U)          /*!< Bit field size in bits for RNG_SR_ERRI. */
00400 
00401 /*! @brief Read current value of the RNG_SR_ERRI field. */
00402 #define BR_RNG_SR_ERRI(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_ERRI)))
00403 /*@}*/
00404 
00405 /*!
00406  * @name Register RNG_SR, field SLP[4] (RO)
00407  *
00408  * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
00409  * mode by asserting the DOZE signal.
00410  *
00411  * Values:
00412  * - 0 - Normal mode
00413  * - 1 - Sleep (low-power) mode
00414  */
00415 /*@{*/
00416 #define BP_RNG_SR_SLP        (4U)          /*!< Bit position for RNG_SR_SLP. */
00417 #define BM_RNG_SR_SLP        (0x00000010U) /*!< Bit mask for RNG_SR_SLP. */
00418 #define BS_RNG_SR_SLP        (1U)          /*!< Bit field size in bits for RNG_SR_SLP. */
00419 
00420 /*! @brief Read current value of the RNG_SR_SLP field. */
00421 #define BR_RNG_SR_SLP(x)     (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_RNG_SR_ADDR(x), BP_RNG_SR_SLP)))
00422 /*@}*/
00423 
00424 /*!
00425  * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
00426  *
00427  * Indicates the number of random-data words that are in OR[RANDOUT], which
00428  * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
00429  * is not 0, then the contents of a random number contained in OR[RANDOUT] are
00430  * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
00431  *
00432  * Values:
00433  * - 0 - No words (empty)
00434  * - 1 - One word (valid)
00435  */
00436 /*@{*/
00437 #define BP_RNG_SR_OREG_LVL   (8U)          /*!< Bit position for RNG_SR_OREG_LVL. */
00438 #define BM_RNG_SR_OREG_LVL   (0x0000FF00U) /*!< Bit mask for RNG_SR_OREG_LVL. */
00439 #define BS_RNG_SR_OREG_LVL   (8U)          /*!< Bit field size in bits for RNG_SR_OREG_LVL. */
00440 
00441 /*! @brief Read current value of the RNG_SR_OREG_LVL field. */
00442 #define BR_RNG_SR_OREG_LVL(x) (UNION_READ(hw_rng_sr_t, HW_RNG_SR_ADDR(x), U, B.OREG_LVL))
00443 /*@}*/
00444 
00445 /*!
00446  * @name Register RNG_SR, field OREG_SIZE[23:16] (RO)
00447  *
00448  * Indicates the size of the Output (OR) register in terms of the number of
00449  * 32-bit random-data words it can hold.
00450  *
00451  * Values:
00452  * - 1 - One word (this value is fixed)
00453  */
00454 /*@{*/
00455 #define BP_RNG_SR_OREG_SIZE  (16U)         /*!< Bit position for RNG_SR_OREG_SIZE. */
00456 #define BM_RNG_SR_OREG_SIZE  (0x00FF0000U) /*!< Bit mask for RNG_SR_OREG_SIZE. */
00457 #define BS_RNG_SR_OREG_SIZE  (8U)          /*!< Bit field size in bits for RNG_SR_OREG_SIZE. */
00458 
00459 /*! @brief Read current value of the RNG_SR_OREG_SIZE field. */
00460 #define BR_RNG_SR_OREG_SIZE(x) (UNION_READ(hw_rng_sr_t, HW_RNG_SR_ADDR(x), U, B.OREG_SIZE))
00461 /*@}*/
00462 
00463 /*******************************************************************************
00464  * HW_RNG_ER - RNGA Entropy Register
00465  ******************************************************************************/
00466 
00467 /*!
00468  * @brief HW_RNG_ER - RNGA Entropy Register (WORZ)
00469  *
00470  * Reset value: 0x00000000U
00471  *
00472  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
00473  * to seed its pseudorandom algorithm. This is a write-only register; reads
00474  * return all zeros.
00475  */
00476 typedef union _hw_rng_er
00477 {
00478     uint32_t U;
00479     struct _hw_rng_er_bitfields
00480     {
00481         uint32_t EXT_ENT : 32;         /*!< [31:0] External Entropy */
00482     } B;
00483 } hw_rng_er_t;
00484 
00485 /*!
00486  * @name Constants and macros for entire RNG_ER register
00487  */
00488 /*@{*/
00489 #define HW_RNG_ER_ADDR(x)        ((x) + 0x8U)
00490 
00491 #define HW_RNG_ER(x)             (*(__O hw_rng_er_t *) HW_RNG_ER_ADDR(x))
00492 #define HW_RNG_ER_RD(x)          (ADDRESS_READ(hw_rng_er_t, HW_RNG_ER_ADDR(x)))
00493 #define HW_RNG_ER_WR(x, v)       (ADDRESS_WRITE(hw_rng_er_t, HW_RNG_ER_ADDR(x), v))
00494 /*@}*/
00495 
00496 /*
00497  * Constants & macros for individual RNG_ER bitfields
00498  */
00499 
00500 /*!
00501  * @name Register RNG_ER, field EXT_ENT[31:0] (WORZ)
00502  *
00503  * Specifies an entropy value that RNGA uses in addition to its ring oscillators
00504  * to seed its pseudorandom algorithm.Specifying a value for this field is
00505  * optional but recommended. You can write to this field at any time during operation.
00506  */
00507 /*@{*/
00508 #define BP_RNG_ER_EXT_ENT    (0U)          /*!< Bit position for RNG_ER_EXT_ENT. */
00509 #define BM_RNG_ER_EXT_ENT    (0xFFFFFFFFU) /*!< Bit mask for RNG_ER_EXT_ENT. */
00510 #define BS_RNG_ER_EXT_ENT    (32U)         /*!< Bit field size in bits for RNG_ER_EXT_ENT. */
00511 
00512 /*! @brief Format value for bitfield RNG_ER_EXT_ENT. */
00513 #define BF_RNG_ER_EXT_ENT(v) ((uint32_t)((uint32_t)(v) << BP_RNG_ER_EXT_ENT) & BM_RNG_ER_EXT_ENT)
00514 
00515 /*! @brief Set the EXT_ENT field to a new value. */
00516 #define BW_RNG_ER_EXT_ENT(x, v) (HW_RNG_ER_WR(x, v))
00517 /*@}*/
00518 
00519 /*******************************************************************************
00520  * HW_RNG_OR - RNGA Output Register
00521  ******************************************************************************/
00522 
00523 /*!
00524  * @brief HW_RNG_OR - RNGA Output Register (RO)
00525  *
00526  * Reset value: 0x00000000U
00527  *
00528  * Stores a random-data word generated by RNGA.
00529  */
00530 typedef union _hw_rng_or
00531 {
00532     uint32_t U;
00533     struct _hw_rng_or_bitfields
00534     {
00535         uint32_t RANDOUT : 32;         /*!< [31:0] Random Output */
00536     } B;
00537 } hw_rng_or_t;
00538 
00539 /*!
00540  * @name Constants and macros for entire RNG_OR register
00541  */
00542 /*@{*/
00543 #define HW_RNG_OR_ADDR(x)        ((x) + 0xCU)
00544 
00545 #define HW_RNG_OR(x)             (*(__I hw_rng_or_t *) HW_RNG_OR_ADDR(x))
00546 #define HW_RNG_OR_RD(x)          (ADDRESS_READ(hw_rng_or_t, HW_RNG_OR_ADDR(x)))
00547 /*@}*/
00548 
00549 /*
00550  * Constants & macros for individual RNG_OR bitfields
00551  */
00552 
00553 /*!
00554  * @name Register RNG_OR, field RANDOUT[31:0] (RO)
00555  *
00556  * Stores a random-data word generated by RNGA. This is a read-only field.Before
00557  * reading RANDOUT, be sure it is valid (SR[OREG_LVL]=1).
00558  *
00559  * Values:
00560  * - 0 - Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is
00561  *     0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error
00562  *     interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt
00563  *     request to the interrupt controller).
00564  */
00565 /*@{*/
00566 #define BP_RNG_OR_RANDOUT    (0U)          /*!< Bit position for RNG_OR_RANDOUT. */
00567 #define BM_RNG_OR_RANDOUT    (0xFFFFFFFFU) /*!< Bit mask for RNG_OR_RANDOUT. */
00568 #define BS_RNG_OR_RANDOUT    (32U)         /*!< Bit field size in bits for RNG_OR_RANDOUT. */
00569 
00570 /*! @brief Read current value of the RNG_OR_RANDOUT field. */
00571 #define BR_RNG_OR_RANDOUT(x) (HW_RNG_OR(x).U)
00572 /*@}*/
00573 
00574 /*******************************************************************************
00575  * hw_rng_t - module struct
00576  ******************************************************************************/
00577 /*!
00578  * @brief All RNG module registers.
00579  */
00580 #pragma pack(1)
00581 typedef struct _hw_rng
00582 {
00583     __IO hw_rng_cr_t CR ;                   /*!< [0x0] RNGA Control Register */
00584     __I hw_rng_sr_t SR ;                    /*!< [0x4] RNGA Status Register */
00585     __O hw_rng_er_t ER ;                    /*!< [0x8] RNGA Entropy Register */
00586     __I hw_rng_or_t OR ;                    /*!< [0xC] RNGA Output Register */
00587 } hw_rng_t;
00588 #pragma pack()
00589 
00590 /*! @brief Macro to access all RNG registers. */
00591 /*! @param x RNG module instance base address. */
00592 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00593  *     use the '&' operator, like <code>&HW_RNG(RNG_BASE)</code>. */
00594 #define HW_RNG(x)      (*(hw_rng_t *)(x))
00595 
00596 #endif /* __HW_RNG_REGISTERS_H__ */
00597 /* EOF */