MK64F12_rfvbat.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_RFVBAT_REGISTERS_H__
00088 #define __HW_RFVBAT_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 RFVBAT
00095  *
00096  * VBAT register file
00097  *
00098  * Registers defined in this header file:
00099  * - HW_RFVBAT_REGn - VBAT register file register
00100  *
00101  * - hw_rfvbat_t - Struct containing all module registers.
00102  */
00103 
00104 #define HW_RFVBAT_INSTANCE_COUNT (1U) /*!< Number of instances of the RFVBAT module. */
00105 
00106 /*******************************************************************************
00107  * HW_RFVBAT_REGn - VBAT register file register
00108  ******************************************************************************/
00109 
00110 /*!
00111  * @brief HW_RFVBAT_REGn - VBAT register file register (RW)
00112  *
00113  * Reset value: 0x00000000U
00114  *
00115  * Each register can be accessed as 8-, 16-, or 32-bits.
00116  */
00117 typedef union _hw_rfvbat_regn
00118 {
00119     uint32_t U;
00120     struct _hw_rfvbat_regn_bitfields
00121     {
00122         uint32_t LL : 8;               /*!< [7:0]  */
00123         uint32_t LH : 8;               /*!< [15:8]  */
00124         uint32_t HL : 8;               /*!< [23:16]  */
00125         uint32_t HH : 8;               /*!< [31:24]  */
00126     } B;
00127 } hw_rfvbat_regn_t;
00128 
00129 /*!
00130  * @name Constants and macros for entire RFVBAT_REGn register
00131  */
00132 /*@{*/
00133 #define HW_RFVBAT_REGn_COUNT (8U)
00134 
00135 #define HW_RFVBAT_REGn_ADDR(x, n) ((x) + 0x0U + (0x4U * (n)))
00136 
00137 #define HW_RFVBAT_REGn(x, n)     (*(__IO hw_rfvbat_regn_t *) HW_RFVBAT_REGn_ADDR(x, n))
00138 #define HW_RFVBAT_REGn_RD(x, n)  (ADDRESS_READ(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n)))
00139 #define HW_RFVBAT_REGn_WR(x, n, v) (ADDRESS_WRITE(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n), v))
00140 #define HW_RFVBAT_REGn_SET(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) |  (v)))
00141 #define HW_RFVBAT_REGn_CLR(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) & ~(v)))
00142 #define HW_RFVBAT_REGn_TOG(x, n, v) (HW_RFVBAT_REGn_WR(x, n, HW_RFVBAT_REGn_RD(x, n) ^  (v)))
00143 /*@}*/
00144 
00145 /*
00146  * Constants & macros for individual RFVBAT_REGn bitfields
00147  */
00148 
00149 /*!
00150  * @name Register RFVBAT_REGn, field LL[7:0] (RW)
00151  *
00152  * Low lower byte
00153  */
00154 /*@{*/
00155 #define BP_RFVBAT_REGn_LL    (0U)          /*!< Bit position for RFVBAT_REGn_LL. */
00156 #define BM_RFVBAT_REGn_LL    (0x000000FFU) /*!< Bit mask for RFVBAT_REGn_LL. */
00157 #define BS_RFVBAT_REGn_LL    (8U)          /*!< Bit field size in bits for RFVBAT_REGn_LL. */
00158 
00159 /*! @brief Read current value of the RFVBAT_REGn_LL field. */
00160 #define BR_RFVBAT_REGn_LL(x, n) (UNION_READ(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n), U, B.LL))
00161 
00162 /*! @brief Format value for bitfield RFVBAT_REGn_LL. */
00163 #define BF_RFVBAT_REGn_LL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LL) & BM_RFVBAT_REGn_LL)
00164 
00165 /*! @brief Set the LL field to a new value. */
00166 #define BW_RFVBAT_REGn_LL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LL) | BF_RFVBAT_REGn_LL(v)))
00167 /*@}*/
00168 
00169 /*!
00170  * @name Register RFVBAT_REGn, field LH[15:8] (RW)
00171  *
00172  * Low higher byte
00173  */
00174 /*@{*/
00175 #define BP_RFVBAT_REGn_LH    (8U)          /*!< Bit position for RFVBAT_REGn_LH. */
00176 #define BM_RFVBAT_REGn_LH    (0x0000FF00U) /*!< Bit mask for RFVBAT_REGn_LH. */
00177 #define BS_RFVBAT_REGn_LH    (8U)          /*!< Bit field size in bits for RFVBAT_REGn_LH. */
00178 
00179 /*! @brief Read current value of the RFVBAT_REGn_LH field. */
00180 #define BR_RFVBAT_REGn_LH(x, n) (UNION_READ(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n), U, B.LH))
00181 
00182 /*! @brief Format value for bitfield RFVBAT_REGn_LH. */
00183 #define BF_RFVBAT_REGn_LH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_LH) & BM_RFVBAT_REGn_LH)
00184 
00185 /*! @brief Set the LH field to a new value. */
00186 #define BW_RFVBAT_REGn_LH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_LH) | BF_RFVBAT_REGn_LH(v)))
00187 /*@}*/
00188 
00189 /*!
00190  * @name Register RFVBAT_REGn, field HL[23:16] (RW)
00191  *
00192  * High lower byte
00193  */
00194 /*@{*/
00195 #define BP_RFVBAT_REGn_HL    (16U)         /*!< Bit position for RFVBAT_REGn_HL. */
00196 #define BM_RFVBAT_REGn_HL    (0x00FF0000U) /*!< Bit mask for RFVBAT_REGn_HL. */
00197 #define BS_RFVBAT_REGn_HL    (8U)          /*!< Bit field size in bits for RFVBAT_REGn_HL. */
00198 
00199 /*! @brief Read current value of the RFVBAT_REGn_HL field. */
00200 #define BR_RFVBAT_REGn_HL(x, n) (UNION_READ(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n), U, B.HL))
00201 
00202 /*! @brief Format value for bitfield RFVBAT_REGn_HL. */
00203 #define BF_RFVBAT_REGn_HL(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HL) & BM_RFVBAT_REGn_HL)
00204 
00205 /*! @brief Set the HL field to a new value. */
00206 #define BW_RFVBAT_REGn_HL(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HL) | BF_RFVBAT_REGn_HL(v)))
00207 /*@}*/
00208 
00209 /*!
00210  * @name Register RFVBAT_REGn, field HH[31:24] (RW)
00211  *
00212  * High higher byte
00213  */
00214 /*@{*/
00215 #define BP_RFVBAT_REGn_HH    (24U)         /*!< Bit position for RFVBAT_REGn_HH. */
00216 #define BM_RFVBAT_REGn_HH    (0xFF000000U) /*!< Bit mask for RFVBAT_REGn_HH. */
00217 #define BS_RFVBAT_REGn_HH    (8U)          /*!< Bit field size in bits for RFVBAT_REGn_HH. */
00218 
00219 /*! @brief Read current value of the RFVBAT_REGn_HH field. */
00220 #define BR_RFVBAT_REGn_HH(x, n) (UNION_READ(hw_rfvbat_regn_t, HW_RFVBAT_REGn_ADDR(x, n), U, B.HH))
00221 
00222 /*! @brief Format value for bitfield RFVBAT_REGn_HH. */
00223 #define BF_RFVBAT_REGn_HH(v) ((uint32_t)((uint32_t)(v) << BP_RFVBAT_REGn_HH) & BM_RFVBAT_REGn_HH)
00224 
00225 /*! @brief Set the HH field to a new value. */
00226 #define BW_RFVBAT_REGn_HH(x, n, v) (HW_RFVBAT_REGn_WR(x, n, (HW_RFVBAT_REGn_RD(x, n) & ~BM_RFVBAT_REGn_HH) | BF_RFVBAT_REGn_HH(v)))
00227 /*@}*/
00228 
00229 /*******************************************************************************
00230  * hw_rfvbat_t - module struct
00231  ******************************************************************************/
00232 /*!
00233  * @brief All RFVBAT module registers.
00234  */
00235 #pragma pack(1)
00236 typedef struct _hw_rfvbat
00237 {
00238     __IO hw_rfvbat_regn_t REGn [8];         /*!< [0x0] VBAT register file register */
00239 } hw_rfvbat_t;
00240 #pragma pack()
00241 
00242 /*! @brief Macro to access all RFVBAT registers. */
00243 /*! @param x RFVBAT module instance base address. */
00244 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00245  *     use the '&' operator, like <code>&HW_RFVBAT(RFVBAT_BASE)</code>. */
00246 #define HW_RFVBAT(x)   (*(hw_rfvbat_t *)(x))
00247 
00248 #endif /* __HW_RFVBAT_REGISTERS_H__ */
00249 /* EOF */