MK64F12_rcm.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_RCM_REGISTERS_H__
00088 #define __HW_RCM_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 RCM
00095  *
00096  * Reset Control Module
00097  *
00098  * Registers defined in this header file:
00099  * - HW_RCM_SRS0 - System Reset Status Register 0
00100  * - HW_RCM_SRS1 - System Reset Status Register 1
00101  * - HW_RCM_RPFC - Reset Pin Filter Control register
00102  * - HW_RCM_RPFW - Reset Pin Filter Width register
00103  * - HW_RCM_MR - Mode Register
00104  *
00105  * - hw_rcm_t - Struct containing all module registers.
00106  */
00107 
00108 #define HW_RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
00109 
00110 /*******************************************************************************
00111  * HW_RCM_SRS0 - System Reset Status Register 0
00112  ******************************************************************************/
00113 
00114 /*!
00115  * @brief HW_RCM_SRS0 - System Reset Status Register 0 (RO)
00116  *
00117  * Reset value: 0x82U
00118  *
00119  * This register includes read-only status flags to indicate the source of the
00120  * most recent reset. The reset state of these bits depends on what caused the MCU
00121  * to reset. The reset value of this register depends on the reset source: POR
00122  * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
00123  * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
00124  * reset - a bit is set if its corresponding reset source caused the reset
00125  */
00126 typedef union _hw_rcm_srs0
00127 {
00128     uint8_t U;
00129     struct _hw_rcm_srs0_bitfields
00130     {
00131         uint8_t WAKEUP : 1;            /*!< [0] Low Leakage Wakeup Reset */
00132         uint8_t LVD : 1;               /*!< [1] Low-Voltage Detect Reset */
00133         uint8_t LOC : 1;               /*!< [2] Loss-of-Clock Reset */
00134         uint8_t LOL : 1;               /*!< [3] Loss-of-Lock Reset */
00135         uint8_t RESERVED0 : 1;         /*!< [4]  */
00136         uint8_t WDOGb : 1;             /*!< [5] Watchdog */
00137         uint8_t PIN : 1;               /*!< [6] External Reset Pin */
00138         uint8_t POR : 1;               /*!< [7] Power-On Reset */
00139     } B;
00140 } hw_rcm_srs0_t;
00141 
00142 /*!
00143  * @name Constants and macros for entire RCM_SRS0 register
00144  */
00145 /*@{*/
00146 #define HW_RCM_SRS0_ADDR(x)      ((x) + 0x0U)
00147 
00148 #define HW_RCM_SRS0(x)           (*(__I hw_rcm_srs0_t *) HW_RCM_SRS0_ADDR(x))
00149 #define HW_RCM_SRS0_RD(x)        (ADDRESS_READ(hw_rcm_srs0_t, HW_RCM_SRS0_ADDR(x)))
00150 /*@}*/
00151 
00152 /*
00153  * Constants & macros for individual RCM_SRS0 bitfields
00154  */
00155 
00156 /*!
00157  * @name Register RCM_SRS0, field WAKEUP[0] (RO)
00158  *
00159  * Indicates a reset has been caused by an enabled LLWU module wakeup source
00160  * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
00161  * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
00162  * mode causes a reset. This bit is cleared by any reset except WAKEUP.
00163  *
00164  * Values:
00165  * - 0 - Reset not caused by LLWU module wakeup source
00166  * - 1 - Reset caused by LLWU module wakeup source
00167  */
00168 /*@{*/
00169 #define BP_RCM_SRS0_WAKEUP   (0U)          /*!< Bit position for RCM_SRS0_WAKEUP. */
00170 #define BM_RCM_SRS0_WAKEUP   (0x01U)       /*!< Bit mask for RCM_SRS0_WAKEUP. */
00171 #define BS_RCM_SRS0_WAKEUP   (1U)          /*!< Bit field size in bits for RCM_SRS0_WAKEUP. */
00172 
00173 /*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
00174 #define BR_RCM_SRS0_WAKEUP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WAKEUP)))
00175 /*@}*/
00176 
00177 /*!
00178  * @name Register RCM_SRS0, field LVD[1] (RO)
00179  *
00180  * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
00181  * an LVD reset occurs. This field is also set by POR.
00182  *
00183  * Values:
00184  * - 0 - Reset not caused by LVD trip or POR
00185  * - 1 - Reset caused by LVD trip or POR
00186  */
00187 /*@{*/
00188 #define BP_RCM_SRS0_LVD      (1U)          /*!< Bit position for RCM_SRS0_LVD. */
00189 #define BM_RCM_SRS0_LVD      (0x02U)       /*!< Bit mask for RCM_SRS0_LVD. */
00190 #define BS_RCM_SRS0_LVD      (1U)          /*!< Bit field size in bits for RCM_SRS0_LVD. */
00191 
00192 /*! @brief Read current value of the RCM_SRS0_LVD field. */
00193 #define BR_RCM_SRS0_LVD(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LVD)))
00194 /*@}*/
00195 
00196 /*!
00197  * @name Register RCM_SRS0, field LOC[2] (RO)
00198  *
00199  * Indicates a reset has been caused by a loss of external clock. The MCG clock
00200  * monitor must be enabled for a loss of clock to be detected. Refer to the
00201  * detailed MCG description for information on enabling the clock monitor.
00202  *
00203  * Values:
00204  * - 0 - Reset not caused by a loss of external clock.
00205  * - 1 - Reset caused by a loss of external clock.
00206  */
00207 /*@{*/
00208 #define BP_RCM_SRS0_LOC      (2U)          /*!< Bit position for RCM_SRS0_LOC. */
00209 #define BM_RCM_SRS0_LOC      (0x04U)       /*!< Bit mask for RCM_SRS0_LOC. */
00210 #define BS_RCM_SRS0_LOC      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOC. */
00211 
00212 /*! @brief Read current value of the RCM_SRS0_LOC field. */
00213 #define BR_RCM_SRS0_LOC(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOC)))
00214 /*@}*/
00215 
00216 /*!
00217  * @name Register RCM_SRS0, field LOL[3] (RO)
00218  *
00219  * Indicates a reset has been caused by a loss of lock in the MCG PLL. See the
00220  * MCG description for information on the loss-of-clock event.
00221  *
00222  * Values:
00223  * - 0 - Reset not caused by a loss of lock in the PLL
00224  * - 1 - Reset caused by a loss of lock in the PLL
00225  */
00226 /*@{*/
00227 #define BP_RCM_SRS0_LOL      (3U)          /*!< Bit position for RCM_SRS0_LOL. */
00228 #define BM_RCM_SRS0_LOL      (0x08U)       /*!< Bit mask for RCM_SRS0_LOL. */
00229 #define BS_RCM_SRS0_LOL      (1U)          /*!< Bit field size in bits for RCM_SRS0_LOL. */
00230 
00231 /*! @brief Read current value of the RCM_SRS0_LOL field. */
00232 #define BR_RCM_SRS0_LOL(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_LOL)))
00233 /*@}*/
00234 
00235 /*!
00236  * @name Register RCM_SRS0, field WDOG[5] (RO)
00237  *
00238  * Indicates a reset has been caused by the watchdog timer Computer Operating
00239  * Properly (COP) timing out. This reset source can be blocked by disabling the COP
00240  * watchdog: write 00 to SIM_COPCTRL[COPT].
00241  *
00242  * Values:
00243  * - 0 - Reset not caused by watchdog timeout
00244  * - 1 - Reset caused by watchdog timeout
00245  */
00246 /*@{*/
00247 #define BP_RCM_SRS0_WDOG     (5U)          /*!< Bit position for RCM_SRS0_WDOG. */
00248 #define BM_RCM_SRS0_WDOG     (0x20U)       /*!< Bit mask for RCM_SRS0_WDOG. */
00249 #define BS_RCM_SRS0_WDOG     (1U)          /*!< Bit field size in bits for RCM_SRS0_WDOG. */
00250 
00251 /*! @brief Read current value of the RCM_SRS0_WDOG field. */
00252 #define BR_RCM_SRS0_WDOG(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_WDOG)))
00253 /*@}*/
00254 
00255 /*!
00256  * @name Register RCM_SRS0, field PIN[6] (RO)
00257  *
00258  * Indicates a reset has been caused by an active-low level on the external
00259  * RESET pin.
00260  *
00261  * Values:
00262  * - 0 - Reset not caused by external reset pin
00263  * - 1 - Reset caused by external reset pin
00264  */
00265 /*@{*/
00266 #define BP_RCM_SRS0_PIN      (6U)          /*!< Bit position for RCM_SRS0_PIN. */
00267 #define BM_RCM_SRS0_PIN      (0x40U)       /*!< Bit mask for RCM_SRS0_PIN. */
00268 #define BS_RCM_SRS0_PIN      (1U)          /*!< Bit field size in bits for RCM_SRS0_PIN. */
00269 
00270 /*! @brief Read current value of the RCM_SRS0_PIN field. */
00271 #define BR_RCM_SRS0_PIN(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_PIN)))
00272 /*@}*/
00273 
00274 /*!
00275  * @name Register RCM_SRS0, field POR[7] (RO)
00276  *
00277  * Indicates a reset has been caused by the power-on detection logic. Because
00278  * the internal supply voltage was ramping up at the time, the low-voltage reset
00279  * (LVD) status bit is also set to indicate that the reset occurred while the
00280  * internal supply was below the LVD threshold.
00281  *
00282  * Values:
00283  * - 0 - Reset not caused by POR
00284  * - 1 - Reset caused by POR
00285  */
00286 /*@{*/
00287 #define BP_RCM_SRS0_POR      (7U)          /*!< Bit position for RCM_SRS0_POR. */
00288 #define BM_RCM_SRS0_POR      (0x80U)       /*!< Bit mask for RCM_SRS0_POR. */
00289 #define BS_RCM_SRS0_POR      (1U)          /*!< Bit field size in bits for RCM_SRS0_POR. */
00290 
00291 /*! @brief Read current value of the RCM_SRS0_POR field. */
00292 #define BR_RCM_SRS0_POR(x)   (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS0_ADDR(x), BP_RCM_SRS0_POR)))
00293 /*@}*/
00294 
00295 /*******************************************************************************
00296  * HW_RCM_SRS1 - System Reset Status Register 1
00297  ******************************************************************************/
00298 
00299 /*!
00300  * @brief HW_RCM_SRS1 - System Reset Status Register 1 (RO)
00301  *
00302  * Reset value: 0x00U
00303  *
00304  * This register includes read-only status flags to indicate the source of the
00305  * most recent reset. The reset state of these bits depends on what caused the MCU
00306  * to reset. The reset value of this register depends on the reset source: POR
00307  * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
00308  * reset - a bit is set if its corresponding reset source caused the reset
00309  */
00310 typedef union _hw_rcm_srs1
00311 {
00312     uint8_t U;
00313     struct _hw_rcm_srs1_bitfields
00314     {
00315         uint8_t JTAG : 1;              /*!< [0] JTAG Generated Reset */
00316         uint8_t LOCKUP : 1;            /*!< [1] Core Lockup */
00317         uint8_t SW : 1;                /*!< [2] Software */
00318         uint8_t MDM_AP : 1;            /*!< [3] MDM-AP System Reset Request */
00319         uint8_t EZPT : 1;              /*!< [4] EzPort Reset */
00320         uint8_t SACKERR : 1;           /*!< [5] Stop Mode Acknowledge Error Reset */
00321         uint8_t RESERVED0 : 2;         /*!< [7:6]  */
00322     } B;
00323 } hw_rcm_srs1_t;
00324 
00325 /*!
00326  * @name Constants and macros for entire RCM_SRS1 register
00327  */
00328 /*@{*/
00329 #define HW_RCM_SRS1_ADDR(x)      ((x) + 0x1U)
00330 
00331 #define HW_RCM_SRS1(x)           (*(__I hw_rcm_srs1_t *) HW_RCM_SRS1_ADDR(x))
00332 #define HW_RCM_SRS1_RD(x)        (ADDRESS_READ(hw_rcm_srs1_t, HW_RCM_SRS1_ADDR(x)))
00333 /*@}*/
00334 
00335 /*
00336  * Constants & macros for individual RCM_SRS1 bitfields
00337  */
00338 
00339 /*!
00340  * @name Register RCM_SRS1, field JTAG[0] (RO)
00341  *
00342  * Indicates a reset has been caused by JTAG selection of certain IR codes:
00343  * EZPORT, EXTEST, HIGHZ, and CLAMP.
00344  *
00345  * Values:
00346  * - 0 - Reset not caused by JTAG
00347  * - 1 - Reset caused by JTAG
00348  */
00349 /*@{*/
00350 #define BP_RCM_SRS1_JTAG     (0U)          /*!< Bit position for RCM_SRS1_JTAG. */
00351 #define BM_RCM_SRS1_JTAG     (0x01U)       /*!< Bit mask for RCM_SRS1_JTAG. */
00352 #define BS_RCM_SRS1_JTAG     (1U)          /*!< Bit field size in bits for RCM_SRS1_JTAG. */
00353 
00354 /*! @brief Read current value of the RCM_SRS1_JTAG field. */
00355 #define BR_RCM_SRS1_JTAG(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_JTAG)))
00356 /*@}*/
00357 
00358 /*!
00359  * @name Register RCM_SRS1, field LOCKUP[1] (RO)
00360  *
00361  * Indicates a reset has been caused by the ARM core indication of a LOCKUP
00362  * event.
00363  *
00364  * Values:
00365  * - 0 - Reset not caused by core LOCKUP event
00366  * - 1 - Reset caused by core LOCKUP event
00367  */
00368 /*@{*/
00369 #define BP_RCM_SRS1_LOCKUP   (1U)          /*!< Bit position for RCM_SRS1_LOCKUP. */
00370 #define BM_RCM_SRS1_LOCKUP   (0x02U)       /*!< Bit mask for RCM_SRS1_LOCKUP. */
00371 #define BS_RCM_SRS1_LOCKUP   (1U)          /*!< Bit field size in bits for RCM_SRS1_LOCKUP. */
00372 
00373 /*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
00374 #define BR_RCM_SRS1_LOCKUP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_LOCKUP)))
00375 /*@}*/
00376 
00377 /*!
00378  * @name Register RCM_SRS1, field SW[2] (RO)
00379  *
00380  * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
00381  * Application Interrupt and Reset Control Register in the ARM core.
00382  *
00383  * Values:
00384  * - 0 - Reset not caused by software setting of SYSRESETREQ bit
00385  * - 1 - Reset caused by software setting of SYSRESETREQ bit
00386  */
00387 /*@{*/
00388 #define BP_RCM_SRS1_SW       (2U)          /*!< Bit position for RCM_SRS1_SW. */
00389 #define BM_RCM_SRS1_SW       (0x04U)       /*!< Bit mask for RCM_SRS1_SW. */
00390 #define BS_RCM_SRS1_SW       (1U)          /*!< Bit field size in bits for RCM_SRS1_SW. */
00391 
00392 /*! @brief Read current value of the RCM_SRS1_SW field. */
00393 #define BR_RCM_SRS1_SW(x)    (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SW)))
00394 /*@}*/
00395 
00396 /*!
00397  * @name Register RCM_SRS1, field MDM_AP[3] (RO)
00398  *
00399  * Indicates a reset has been caused by the host debugger system setting of the
00400  * System Reset Request bit in the MDM-AP Control Register.
00401  *
00402  * Values:
00403  * - 0 - Reset not caused by host debugger system setting of the System Reset
00404  *     Request bit
00405  * - 1 - Reset caused by host debugger system setting of the System Reset
00406  *     Request bit
00407  */
00408 /*@{*/
00409 #define BP_RCM_SRS1_MDM_AP   (3U)          /*!< Bit position for RCM_SRS1_MDM_AP. */
00410 #define BM_RCM_SRS1_MDM_AP   (0x08U)       /*!< Bit mask for RCM_SRS1_MDM_AP. */
00411 #define BS_RCM_SRS1_MDM_AP   (1U)          /*!< Bit field size in bits for RCM_SRS1_MDM_AP. */
00412 
00413 /*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
00414 #define BR_RCM_SRS1_MDM_AP(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_MDM_AP)))
00415 /*@}*/
00416 
00417 /*!
00418  * @name Register RCM_SRS1, field EZPT[4] (RO)
00419  *
00420  * Indicates a reset has been caused by EzPort receiving the RESET command while
00421  * the device is in EzPort mode.
00422  *
00423  * Values:
00424  * - 0 - Reset not caused by EzPort receiving the RESET command while the device
00425  *     is in EzPort mode
00426  * - 1 - Reset caused by EzPort receiving the RESET command while the device is
00427  *     in EzPort mode
00428  */
00429 /*@{*/
00430 #define BP_RCM_SRS1_EZPT     (4U)          /*!< Bit position for RCM_SRS1_EZPT. */
00431 #define BM_RCM_SRS1_EZPT     (0x10U)       /*!< Bit mask for RCM_SRS1_EZPT. */
00432 #define BS_RCM_SRS1_EZPT     (1U)          /*!< Bit field size in bits for RCM_SRS1_EZPT. */
00433 
00434 /*! @brief Read current value of the RCM_SRS1_EZPT field. */
00435 #define BR_RCM_SRS1_EZPT(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_EZPT)))
00436 /*@}*/
00437 
00438 /*!
00439  * @name Register RCM_SRS1, field SACKERR[5] (RO)
00440  *
00441  * Indicates that after an attempt to enter Stop mode, a reset has been caused
00442  * by a failure of one or more peripherals to acknowledge within approximately one
00443  * second to enter stop mode.
00444  *
00445  * Values:
00446  * - 0 - Reset not caused by peripheral failure to acknowledge attempt to enter
00447  *     stop mode
00448  * - 1 - Reset caused by peripheral failure to acknowledge attempt to enter stop
00449  *     mode
00450  */
00451 /*@{*/
00452 #define BP_RCM_SRS1_SACKERR  (5U)          /*!< Bit position for RCM_SRS1_SACKERR. */
00453 #define BM_RCM_SRS1_SACKERR  (0x20U)       /*!< Bit mask for RCM_SRS1_SACKERR. */
00454 #define BS_RCM_SRS1_SACKERR  (1U)          /*!< Bit field size in bits for RCM_SRS1_SACKERR. */
00455 
00456 /*! @brief Read current value of the RCM_SRS1_SACKERR field. */
00457 #define BR_RCM_SRS1_SACKERR(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_SRS1_ADDR(x), BP_RCM_SRS1_SACKERR)))
00458 /*@}*/
00459 
00460 /*******************************************************************************
00461  * HW_RCM_RPFC - Reset Pin Filter Control register
00462  ******************************************************************************/
00463 
00464 /*!
00465  * @brief HW_RCM_RPFC - Reset Pin Filter Control register (RW)
00466  *
00467  * Reset value: 0x00U
00468  *
00469  * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
00470  * other reset types. The bus clock filter is reset when disabled or when entering
00471  * stop mode. The LPO filter is reset when disabled or when entering any low
00472  * leakage stop mode .
00473  */
00474 typedef union _hw_rcm_rpfc
00475 {
00476     uint8_t U;
00477     struct _hw_rcm_rpfc_bitfields
00478     {
00479         uint8_t RSTFLTSRW : 2;         /*!< [1:0] Reset Pin Filter Select in Run and
00480                                         * Wait Modes */
00481         uint8_t RSTFLTSS : 1;          /*!< [2] Reset Pin Filter Select in Stop Mode */
00482         uint8_t RESERVED0 : 5;         /*!< [7:3]  */
00483     } B;
00484 } hw_rcm_rpfc_t;
00485 
00486 /*!
00487  * @name Constants and macros for entire RCM_RPFC register
00488  */
00489 /*@{*/
00490 #define HW_RCM_RPFC_ADDR(x)      ((x) + 0x4U)
00491 
00492 #define HW_RCM_RPFC(x)           (*(__IO hw_rcm_rpfc_t *) HW_RCM_RPFC_ADDR(x))
00493 #define HW_RCM_RPFC_RD(x)        (ADDRESS_READ(hw_rcm_rpfc_t, HW_RCM_RPFC_ADDR(x)))
00494 #define HW_RCM_RPFC_WR(x, v)     (ADDRESS_WRITE(hw_rcm_rpfc_t, HW_RCM_RPFC_ADDR(x), v))
00495 #define HW_RCM_RPFC_SET(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) |  (v)))
00496 #define HW_RCM_RPFC_CLR(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) & ~(v)))
00497 #define HW_RCM_RPFC_TOG(x, v)    (HW_RCM_RPFC_WR(x, HW_RCM_RPFC_RD(x) ^  (v)))
00498 /*@}*/
00499 
00500 /*
00501  * Constants & macros for individual RCM_RPFC bitfields
00502  */
00503 
00504 /*!
00505  * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
00506  *
00507  * Selects how the reset pin filter is enabled in run and wait modes.
00508  *
00509  * Values:
00510  * - 00 - All filtering disabled
00511  * - 01 - Bus clock filter enabled for normal operation
00512  * - 10 - LPO clock filter enabled for normal operation
00513  * - 11 - Reserved
00514  */
00515 /*@{*/
00516 #define BP_RCM_RPFC_RSTFLTSRW (0U)         /*!< Bit position for RCM_RPFC_RSTFLTSRW. */
00517 #define BM_RCM_RPFC_RSTFLTSRW (0x03U)      /*!< Bit mask for RCM_RPFC_RSTFLTSRW. */
00518 #define BS_RCM_RPFC_RSTFLTSRW (2U)         /*!< Bit field size in bits for RCM_RPFC_RSTFLTSRW. */
00519 
00520 /*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
00521 #define BR_RCM_RPFC_RSTFLTSRW(x) (UNION_READ(hw_rcm_rpfc_t, HW_RCM_RPFC_ADDR(x), U, B.RSTFLTSRW))
00522 
00523 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSRW. */
00524 #define BF_RCM_RPFC_RSTFLTSRW(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSRW) & BM_RCM_RPFC_RSTFLTSRW)
00525 
00526 /*! @brief Set the RSTFLTSRW field to a new value. */
00527 #define BW_RCM_RPFC_RSTFLTSRW(x, v) (HW_RCM_RPFC_WR(x, (HW_RCM_RPFC_RD(x) & ~BM_RCM_RPFC_RSTFLTSRW) | BF_RCM_RPFC_RSTFLTSRW(v)))
00528 /*@}*/
00529 
00530 /*!
00531  * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
00532  *
00533  * Selects how the reset pin filter is enabled in Stop and VLPS modes
00534  *
00535  * Values:
00536  * - 0 - All filtering disabled
00537  * - 1 - LPO clock filter enabled
00538  */
00539 /*@{*/
00540 #define BP_RCM_RPFC_RSTFLTSS (2U)          /*!< Bit position for RCM_RPFC_RSTFLTSS. */
00541 #define BM_RCM_RPFC_RSTFLTSS (0x04U)       /*!< Bit mask for RCM_RPFC_RSTFLTSS. */
00542 #define BS_RCM_RPFC_RSTFLTSS (1U)          /*!< Bit field size in bits for RCM_RPFC_RSTFLTSS. */
00543 
00544 /*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
00545 #define BR_RCM_RPFC_RSTFLTSS(x) (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS)))
00546 
00547 /*! @brief Format value for bitfield RCM_RPFC_RSTFLTSS. */
00548 #define BF_RCM_RPFC_RSTFLTSS(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFC_RSTFLTSS) & BM_RCM_RPFC_RSTFLTSS)
00549 
00550 /*! @brief Set the RSTFLTSS field to a new value. */
00551 #define BW_RCM_RPFC_RSTFLTSS(x, v) (ADDRESS_WRITE(uint8_t, BITBAND_ADDRESS8(HW_RCM_RPFC_ADDR(x), BP_RCM_RPFC_RSTFLTSS), v))
00552 /*@}*/
00553 
00554 /*******************************************************************************
00555  * HW_RCM_RPFW - Reset Pin Filter Width register
00556  ******************************************************************************/
00557 
00558 /*!
00559  * @brief HW_RCM_RPFW - Reset Pin Filter Width register (RW)
00560  *
00561  * Reset value: 0x00U
00562  *
00563  * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
00564  * They are unaffected by other reset types.
00565  */
00566 typedef union _hw_rcm_rpfw
00567 {
00568     uint8_t U;
00569     struct _hw_rcm_rpfw_bitfields
00570     {
00571         uint8_t RSTFLTSEL : 5;         /*!< [4:0] Reset Pin Filter Bus Clock Select */
00572         uint8_t RESERVED0 : 3;         /*!< [7:5]  */
00573     } B;
00574 } hw_rcm_rpfw_t;
00575 
00576 /*!
00577  * @name Constants and macros for entire RCM_RPFW register
00578  */
00579 /*@{*/
00580 #define HW_RCM_RPFW_ADDR(x)      ((x) + 0x5U)
00581 
00582 #define HW_RCM_RPFW(x)           (*(__IO hw_rcm_rpfw_t *) HW_RCM_RPFW_ADDR(x))
00583 #define HW_RCM_RPFW_RD(x)        (ADDRESS_READ(hw_rcm_rpfw_t, HW_RCM_RPFW_ADDR(x)))
00584 #define HW_RCM_RPFW_WR(x, v)     (ADDRESS_WRITE(hw_rcm_rpfw_t, HW_RCM_RPFW_ADDR(x), v))
00585 #define HW_RCM_RPFW_SET(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) |  (v)))
00586 #define HW_RCM_RPFW_CLR(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) & ~(v)))
00587 #define HW_RCM_RPFW_TOG(x, v)    (HW_RCM_RPFW_WR(x, HW_RCM_RPFW_RD(x) ^  (v)))
00588 /*@}*/
00589 
00590 /*
00591  * Constants & macros for individual RCM_RPFW bitfields
00592  */
00593 
00594 /*!
00595  * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
00596  *
00597  * Selects the reset pin bus clock filter width.
00598  *
00599  * Values:
00600  * - 00000 - Bus clock filter count is 1
00601  * - 00001 - Bus clock filter count is 2
00602  * - 00010 - Bus clock filter count is 3
00603  * - 00011 - Bus clock filter count is 4
00604  * - 00100 - Bus clock filter count is 5
00605  * - 00101 - Bus clock filter count is 6
00606  * - 00110 - Bus clock filter count is 7
00607  * - 00111 - Bus clock filter count is 8
00608  * - 01000 - Bus clock filter count is 9
00609  * - 01001 - Bus clock filter count is 10
00610  * - 01010 - Bus clock filter count is 11
00611  * - 01011 - Bus clock filter count is 12
00612  * - 01100 - Bus clock filter count is 13
00613  * - 01101 - Bus clock filter count is 14
00614  * - 01110 - Bus clock filter count is 15
00615  * - 01111 - Bus clock filter count is 16
00616  * - 10000 - Bus clock filter count is 17
00617  * - 10001 - Bus clock filter count is 18
00618  * - 10010 - Bus clock filter count is 19
00619  * - 10011 - Bus clock filter count is 20
00620  * - 10100 - Bus clock filter count is 21
00621  * - 10101 - Bus clock filter count is 22
00622  * - 10110 - Bus clock filter count is 23
00623  * - 10111 - Bus clock filter count is 24
00624  * - 11000 - Bus clock filter count is 25
00625  * - 11001 - Bus clock filter count is 26
00626  * - 11010 - Bus clock filter count is 27
00627  * - 11011 - Bus clock filter count is 28
00628  * - 11100 - Bus clock filter count is 29
00629  * - 11101 - Bus clock filter count is 30
00630  * - 11110 - Bus clock filter count is 31
00631  * - 11111 - Bus clock filter count is 32
00632  */
00633 /*@{*/
00634 #define BP_RCM_RPFW_RSTFLTSEL (0U)         /*!< Bit position for RCM_RPFW_RSTFLTSEL. */
00635 #define BM_RCM_RPFW_RSTFLTSEL (0x1FU)      /*!< Bit mask for RCM_RPFW_RSTFLTSEL. */
00636 #define BS_RCM_RPFW_RSTFLTSEL (5U)         /*!< Bit field size in bits for RCM_RPFW_RSTFLTSEL. */
00637 
00638 /*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
00639 #define BR_RCM_RPFW_RSTFLTSEL(x) (UNION_READ(hw_rcm_rpfw_t, HW_RCM_RPFW_ADDR(x), U, B.RSTFLTSEL))
00640 
00641 /*! @brief Format value for bitfield RCM_RPFW_RSTFLTSEL. */
00642 #define BF_RCM_RPFW_RSTFLTSEL(v) ((uint8_t)((uint8_t)(v) << BP_RCM_RPFW_RSTFLTSEL) & BM_RCM_RPFW_RSTFLTSEL)
00643 
00644 /*! @brief Set the RSTFLTSEL field to a new value. */
00645 #define BW_RCM_RPFW_RSTFLTSEL(x, v) (HW_RCM_RPFW_WR(x, (HW_RCM_RPFW_RD(x) & ~BM_RCM_RPFW_RSTFLTSEL) | BF_RCM_RPFW_RSTFLTSEL(v)))
00646 /*@}*/
00647 
00648 /*******************************************************************************
00649  * HW_RCM_MR - Mode Register
00650  ******************************************************************************/
00651 
00652 /*!
00653  * @brief HW_RCM_MR - Mode Register (RO)
00654  *
00655  * Reset value: 0x00U
00656  *
00657  * This register includes read-only status flags to indicate the state of the
00658  * mode pins during the last Chip Reset.
00659  */
00660 typedef union _hw_rcm_mr
00661 {
00662     uint8_t U;
00663     struct _hw_rcm_mr_bitfields
00664     {
00665         uint8_t RESERVED0 : 1;         /*!< [0]  */
00666         uint8_t EZP_MS : 1;            /*!< [1] EZP_MS_B pin state */
00667         uint8_t RESERVED1 : 6;         /*!< [7:2]  */
00668     } B;
00669 } hw_rcm_mr_t;
00670 
00671 /*!
00672  * @name Constants and macros for entire RCM_MR register
00673  */
00674 /*@{*/
00675 #define HW_RCM_MR_ADDR(x)        ((x) + 0x7U)
00676 
00677 #define HW_RCM_MR(x)             (*(__I hw_rcm_mr_t *) HW_RCM_MR_ADDR(x))
00678 #define HW_RCM_MR_RD(x)          (ADDRESS_READ(hw_rcm_mr_t, HW_RCM_MR_ADDR(x)))
00679 /*@}*/
00680 
00681 /*
00682  * Constants & macros for individual RCM_MR bitfields
00683  */
00684 
00685 /*!
00686  * @name Register RCM_MR, field EZP_MS[1] (RO)
00687  *
00688  * Reflects the state of the EZP_MS pin during the last Chip Reset
00689  *
00690  * Values:
00691  * - 0 - Pin deasserted (logic 1)
00692  * - 1 - Pin asserted (logic 0)
00693  */
00694 /*@{*/
00695 #define BP_RCM_MR_EZP_MS     (1U)          /*!< Bit position for RCM_MR_EZP_MS. */
00696 #define BM_RCM_MR_EZP_MS     (0x02U)       /*!< Bit mask for RCM_MR_EZP_MS. */
00697 #define BS_RCM_MR_EZP_MS     (1U)          /*!< Bit field size in bits for RCM_MR_EZP_MS. */
00698 
00699 /*! @brief Read current value of the RCM_MR_EZP_MS field. */
00700 #define BR_RCM_MR_EZP_MS(x)  (ADDRESS_READ(uint8_t, BITBAND_ADDRESS8(HW_RCM_MR_ADDR(x), BP_RCM_MR_EZP_MS)))
00701 /*@}*/
00702 
00703 /*******************************************************************************
00704  * hw_rcm_t - module struct
00705  ******************************************************************************/
00706 /*!
00707  * @brief All RCM module registers.
00708  */
00709 #pragma pack(1)
00710 typedef struct _hw_rcm
00711 {
00712     __I hw_rcm_srs0_t SRS0 ;                /*!< [0x0] System Reset Status Register 0 */
00713     __I hw_rcm_srs1_t SRS1 ;                /*!< [0x1] System Reset Status Register 1 */
00714     uint8_t _reserved0[2];
00715     __IO hw_rcm_rpfc_t RPFC ;               /*!< [0x4] Reset Pin Filter Control register */
00716     __IO hw_rcm_rpfw_t RPFW ;               /*!< [0x5] Reset Pin Filter Width register */
00717     uint8_t _reserved1[1];
00718     __I hw_rcm_mr_t MR ;                    /*!< [0x7] Mode Register */
00719 } hw_rcm_t;
00720 #pragma pack()
00721 
00722 /*! @brief Macro to access all RCM registers. */
00723 /*! @param x RCM module instance base address. */
00724 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00725  *     use the '&' operator, like <code>&HW_RCM(RCM_BASE)</code>. */
00726 #define HW_RCM(x)      (*(hw_rcm_t *)(x))
00727 
00728 #endif /* __HW_RCM_REGISTERS_H__ */
00729 /* EOF */