MK64F12_port.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_PORT_REGISTERS_H__
00088 #define __HW_PORT_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 PORT
00095  *
00096  * Pin Control and Interrupts
00097  *
00098  * Registers defined in this header file:
00099  * - HW_PORT_PCRn - Pin Control Register n
00100  * - HW_PORT_GPCLR - Global Pin Control Low Register
00101  * - HW_PORT_GPCHR - Global Pin Control High Register
00102  * - HW_PORT_ISFR - Interrupt Status Flag Register
00103  * - HW_PORT_DFER - Digital Filter Enable Register
00104  * - HW_PORT_DFCR - Digital Filter Clock Register
00105  * - HW_PORT_DFWR - Digital Filter Width Register
00106  *
00107  * - hw_port_t - Struct containing all module registers.
00108  */
00109 
00110 #define HW_PORT_INSTANCE_COUNT (5U) /*!< Number of instances of the PORT module. */
00111 #define HW_PORTA (0U) /*!< Instance number for PORTA. */
00112 #define HW_PORTB (1U) /*!< Instance number for PORTB. */
00113 #define HW_PORTC (2U) /*!< Instance number for PORTC. */
00114 #define HW_PORTD (3U) /*!< Instance number for PORTD. */
00115 #define HW_PORTE (4U) /*!< Instance number for PORTE. */
00116 
00117 /*******************************************************************************
00118  * HW_PORT_PCRn - Pin Control Register n
00119  ******************************************************************************/
00120 
00121 /*!
00122  * @brief HW_PORT_PCRn - Pin Control Register n (RW)
00123  *
00124  * Reset value: 0x00000742U
00125  *
00126  * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
00127  * this device. See the GPIO Configuration section for details on the available
00128  * functions for each pin. Do not modify pin configuration registers associated
00129  * with pins not available in your selected package. All unbonded pins not
00130  * available in your package will default to DISABLE state for lowest power consumption.
00131  */
00132 typedef union _hw_port_pcrn
00133 {
00134     uint32_t U;
00135     struct _hw_port_pcrn_bitfields
00136     {
00137         uint32_t PS : 1;               /*!< [0] Pull Select */
00138         uint32_t PE : 1;               /*!< [1] Pull Enable */
00139         uint32_t SRE : 1;              /*!< [2] Slew Rate Enable */
00140         uint32_t RESERVED0 : 1;        /*!< [3]  */
00141         uint32_t PFE : 1;              /*!< [4] Passive Filter Enable */
00142         uint32_t ODE : 1;              /*!< [5] Open Drain Enable */
00143         uint32_t DSE : 1;              /*!< [6] Drive Strength Enable */
00144         uint32_t RESERVED1 : 1;        /*!< [7]  */
00145         uint32_t MUX : 3;              /*!< [10:8] Pin Mux Control */
00146         uint32_t RESERVED2 : 4;        /*!< [14:11]  */
00147         uint32_t LK : 1;               /*!< [15] Lock Register */
00148         uint32_t IRQC : 4;             /*!< [19:16] Interrupt Configuration */
00149         uint32_t RESERVED3 : 4;        /*!< [23:20]  */
00150         uint32_t ISF : 1;              /*!< [24] Interrupt Status Flag */
00151         uint32_t RESERVED4 : 7;        /*!< [31:25]  */
00152     } B;
00153 } hw_port_pcrn_t;
00154 
00155 /*!
00156  * @name Constants and macros for entire PORT_PCRn register
00157  */
00158 /*@{*/
00159 #define HW_PORT_PCRn_COUNT (32U)
00160 
00161 #define HW_PORT_PCRn_ADDR(x, n)  ((x) + 0x0U + (0x4U * (n)))
00162 
00163 #define HW_PORT_PCRn(x, n)       (*(__IO hw_port_pcrn_t *) HW_PORT_PCRn_ADDR(x, n))
00164 #define HW_PORT_PCRn_RD(x, n)    (ADDRESS_READ(hw_port_pcrn_t, HW_PORT_PCRn_ADDR(x, n)))
00165 #define HW_PORT_PCRn_WR(x, n, v) (ADDRESS_WRITE(hw_port_pcrn_t, HW_PORT_PCRn_ADDR(x, n), v))
00166 #define HW_PORT_PCRn_SET(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) |  (v)))
00167 #define HW_PORT_PCRn_CLR(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) & ~(v)))
00168 #define HW_PORT_PCRn_TOG(x, n, v) (HW_PORT_PCRn_WR(x, n, HW_PORT_PCRn_RD(x, n) ^  (v)))
00169 /*@}*/
00170 
00171 /*
00172  * Constants & macros for individual PORT_PCRn bitfields
00173  */
00174 
00175 /*!
00176  * @name Register PORT_PCRn, field PS[0] (RW)
00177  *
00178  * Pull configuration is valid in all digital pin muxing modes.
00179  *
00180  * Values:
00181  * - 0 - Internal pulldown resistor is enabled on the corresponding pin, if the
00182  *     corresponding PE field is set.
00183  * - 1 - Internal pullup resistor is enabled on the corresponding pin, if the
00184  *     corresponding PE field is set.
00185  */
00186 /*@{*/
00187 #define BP_PORT_PCRn_PS      (0U)          /*!< Bit position for PORT_PCRn_PS. */
00188 #define BM_PORT_PCRn_PS      (0x00000001U) /*!< Bit mask for PORT_PCRn_PS. */
00189 #define BS_PORT_PCRn_PS      (1U)          /*!< Bit field size in bits for PORT_PCRn_PS. */
00190 
00191 /*! @brief Read current value of the PORT_PCRn_PS field. */
00192 #define BR_PORT_PCRn_PS(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS)))
00193 
00194 /*! @brief Format value for bitfield PORT_PCRn_PS. */
00195 #define BF_PORT_PCRn_PS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PS) & BM_PORT_PCRn_PS)
00196 
00197 /*! @brief Set the PS field to a new value. */
00198 #define BW_PORT_PCRn_PS(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PS), v))
00199 /*@}*/
00200 
00201 /*!
00202  * @name Register PORT_PCRn, field PE[1] (RW)
00203  *
00204  * Pull configuration is valid in all digital pin muxing modes.
00205  *
00206  * Values:
00207  * - 0 - Internal pullup or pulldown resistor is not enabled on the
00208  *     corresponding pin.
00209  * - 1 - Internal pullup or pulldown resistor is enabled on the corresponding
00210  *     pin, if the pin is configured as a digital input.
00211  */
00212 /*@{*/
00213 #define BP_PORT_PCRn_PE      (1U)          /*!< Bit position for PORT_PCRn_PE. */
00214 #define BM_PORT_PCRn_PE      (0x00000002U) /*!< Bit mask for PORT_PCRn_PE. */
00215 #define BS_PORT_PCRn_PE      (1U)          /*!< Bit field size in bits for PORT_PCRn_PE. */
00216 
00217 /*! @brief Read current value of the PORT_PCRn_PE field. */
00218 #define BR_PORT_PCRn_PE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE)))
00219 
00220 /*! @brief Format value for bitfield PORT_PCRn_PE. */
00221 #define BF_PORT_PCRn_PE(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PE) & BM_PORT_PCRn_PE)
00222 
00223 /*! @brief Set the PE field to a new value. */
00224 #define BW_PORT_PCRn_PE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PE), v))
00225 /*@}*/
00226 
00227 /*!
00228  * @name Register PORT_PCRn, field SRE[2] (RW)
00229  *
00230  * Slew rate configuration is valid in all digital pin muxing modes.
00231  *
00232  * Values:
00233  * - 0 - Fast slew rate is configured on the corresponding pin, if the pin is
00234  *     configured as a digital output.
00235  * - 1 - Slow slew rate is configured on the corresponding pin, if the pin is
00236  *     configured as a digital output.
00237  */
00238 /*@{*/
00239 #define BP_PORT_PCRn_SRE     (2U)          /*!< Bit position for PORT_PCRn_SRE. */
00240 #define BM_PORT_PCRn_SRE     (0x00000004U) /*!< Bit mask for PORT_PCRn_SRE. */
00241 #define BS_PORT_PCRn_SRE     (1U)          /*!< Bit field size in bits for PORT_PCRn_SRE. */
00242 
00243 /*! @brief Read current value of the PORT_PCRn_SRE field. */
00244 #define BR_PORT_PCRn_SRE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE)))
00245 
00246 /*! @brief Format value for bitfield PORT_PCRn_SRE. */
00247 #define BF_PORT_PCRn_SRE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_SRE) & BM_PORT_PCRn_SRE)
00248 
00249 /*! @brief Set the SRE field to a new value. */
00250 #define BW_PORT_PCRn_SRE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_SRE), v))
00251 /*@}*/
00252 
00253 /*!
00254  * @name Register PORT_PCRn, field PFE[4] (RW)
00255  *
00256  * Passive filter configuration is valid in all digital pin muxing modes.
00257  *
00258  * Values:
00259  * - 0 - Passive input filter is disabled on the corresponding pin.
00260  * - 1 - Passive input filter is enabled on the corresponding pin, if the pin is
00261  *     configured as a digital input. Refer to the device data sheet for filter
00262  *     characteristics.
00263  */
00264 /*@{*/
00265 #define BP_PORT_PCRn_PFE     (4U)          /*!< Bit position for PORT_PCRn_PFE. */
00266 #define BM_PORT_PCRn_PFE     (0x00000010U) /*!< Bit mask for PORT_PCRn_PFE. */
00267 #define BS_PORT_PCRn_PFE     (1U)          /*!< Bit field size in bits for PORT_PCRn_PFE. */
00268 
00269 /*! @brief Read current value of the PORT_PCRn_PFE field. */
00270 #define BR_PORT_PCRn_PFE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE)))
00271 
00272 /*! @brief Format value for bitfield PORT_PCRn_PFE. */
00273 #define BF_PORT_PCRn_PFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_PFE) & BM_PORT_PCRn_PFE)
00274 
00275 /*! @brief Set the PFE field to a new value. */
00276 #define BW_PORT_PCRn_PFE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_PFE), v))
00277 /*@}*/
00278 
00279 /*!
00280  * @name Register PORT_PCRn, field ODE[5] (RW)
00281  *
00282  * Open drain configuration is valid in all digital pin muxing modes.
00283  *
00284  * Values:
00285  * - 0 - Open drain output is disabled on the corresponding pin.
00286  * - 1 - Open drain output is enabled on the corresponding pin, if the pin is
00287  *     configured as a digital output.
00288  */
00289 /*@{*/
00290 #define BP_PORT_PCRn_ODE     (5U)          /*!< Bit position for PORT_PCRn_ODE. */
00291 #define BM_PORT_PCRn_ODE     (0x00000020U) /*!< Bit mask for PORT_PCRn_ODE. */
00292 #define BS_PORT_PCRn_ODE     (1U)          /*!< Bit field size in bits for PORT_PCRn_ODE. */
00293 
00294 /*! @brief Read current value of the PORT_PCRn_ODE field. */
00295 #define BR_PORT_PCRn_ODE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE)))
00296 
00297 /*! @brief Format value for bitfield PORT_PCRn_ODE. */
00298 #define BF_PORT_PCRn_ODE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ODE) & BM_PORT_PCRn_ODE)
00299 
00300 /*! @brief Set the ODE field to a new value. */
00301 #define BW_PORT_PCRn_ODE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ODE), v))
00302 /*@}*/
00303 
00304 /*!
00305  * @name Register PORT_PCRn, field DSE[6] (RW)
00306  *
00307  * Drive strength configuration is valid in all digital pin muxing modes.
00308  *
00309  * Values:
00310  * - 0 - Low drive strength is configured on the corresponding pin, if pin is
00311  *     configured as a digital output.
00312  * - 1 - High drive strength is configured on the corresponding pin, if pin is
00313  *     configured as a digital output.
00314  */
00315 /*@{*/
00316 #define BP_PORT_PCRn_DSE     (6U)          /*!< Bit position for PORT_PCRn_DSE. */
00317 #define BM_PORT_PCRn_DSE     (0x00000040U) /*!< Bit mask for PORT_PCRn_DSE. */
00318 #define BS_PORT_PCRn_DSE     (1U)          /*!< Bit field size in bits for PORT_PCRn_DSE. */
00319 
00320 /*! @brief Read current value of the PORT_PCRn_DSE field. */
00321 #define BR_PORT_PCRn_DSE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE)))
00322 
00323 /*! @brief Format value for bitfield PORT_PCRn_DSE. */
00324 #define BF_PORT_PCRn_DSE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_DSE) & BM_PORT_PCRn_DSE)
00325 
00326 /*! @brief Set the DSE field to a new value. */
00327 #define BW_PORT_PCRn_DSE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_DSE), v))
00328 /*@}*/
00329 
00330 /*!
00331  * @name Register PORT_PCRn, field MUX[10:8] (RW)
00332  *
00333  * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
00334  * reserved and may result in configuring the pin for a different pin muxing
00335  * slot. The corresponding pin is configured in the following pin muxing slot as
00336  * follows:
00337  *
00338  * Values:
00339  * - 000 - Pin disabled (analog).
00340  * - 001 - Alternative 1 (GPIO).
00341  * - 010 - Alternative 2 (chip-specific).
00342  * - 011 - Alternative 3 (chip-specific).
00343  * - 100 - Alternative 4 (chip-specific).
00344  * - 101 - Alternative 5 (chip-specific).
00345  * - 110 - Alternative 6 (chip-specific).
00346  * - 111 - Alternative 7 (chip-specific).
00347  */
00348 /*@{*/
00349 #define BP_PORT_PCRn_MUX     (8U)          /*!< Bit position for PORT_PCRn_MUX. */
00350 #define BM_PORT_PCRn_MUX     (0x00000700U) /*!< Bit mask for PORT_PCRn_MUX. */
00351 #define BS_PORT_PCRn_MUX     (3U)          /*!< Bit field size in bits for PORT_PCRn_MUX. */
00352 
00353 /*! @brief Read current value of the PORT_PCRn_MUX field. */
00354 #define BR_PORT_PCRn_MUX(x, n) (UNION_READ(hw_port_pcrn_t, HW_PORT_PCRn_ADDR(x, n), U, B.MUX))
00355 
00356 /*! @brief Format value for bitfield PORT_PCRn_MUX. */
00357 #define BF_PORT_PCRn_MUX(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_MUX) & BM_PORT_PCRn_MUX)
00358 
00359 /*! @brief Set the MUX field to a new value. */
00360 #define BW_PORT_PCRn_MUX(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_MUX) | BF_PORT_PCRn_MUX(v)))
00361 /*@}*/
00362 
00363 /*!
00364  * @name Register PORT_PCRn, field LK[15] (RW)
00365  *
00366  * Values:
00367  * - 0 - Pin Control Register fields [15:0] are not locked.
00368  * - 1 - Pin Control Register fields [15:0] are locked and cannot be updated
00369  *     until the next system reset.
00370  */
00371 /*@{*/
00372 #define BP_PORT_PCRn_LK      (15U)         /*!< Bit position for PORT_PCRn_LK. */
00373 #define BM_PORT_PCRn_LK      (0x00008000U) /*!< Bit mask for PORT_PCRn_LK. */
00374 #define BS_PORT_PCRn_LK      (1U)          /*!< Bit field size in bits for PORT_PCRn_LK. */
00375 
00376 /*! @brief Read current value of the PORT_PCRn_LK field. */
00377 #define BR_PORT_PCRn_LK(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK)))
00378 
00379 /*! @brief Format value for bitfield PORT_PCRn_LK. */
00380 #define BF_PORT_PCRn_LK(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_LK) & BM_PORT_PCRn_LK)
00381 
00382 /*! @brief Set the LK field to a new value. */
00383 #define BW_PORT_PCRn_LK(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_LK), v))
00384 /*@}*/
00385 
00386 /*!
00387  * @name Register PORT_PCRn, field IRQC[19:16] (RW)
00388  *
00389  * The pin interrupt configuration is valid in all digital pin muxing modes. The
00390  * corresponding pin is configured to generate interrupt/DMA request as follows:
00391  *
00392  * Values:
00393  * - 0000 - Interrupt/DMA request disabled.
00394  * - 0001 - DMA request on rising edge.
00395  * - 0010 - DMA request on falling edge.
00396  * - 0011 - DMA request on either edge.
00397  * - 1000 - Interrupt when logic 0.
00398  * - 1001 - Interrupt on rising-edge.
00399  * - 1010 - Interrupt on falling-edge.
00400  * - 1011 - Interrupt on either edge.
00401  * - 1100 - Interrupt when logic 1.
00402  */
00403 /*@{*/
00404 #define BP_PORT_PCRn_IRQC    (16U)         /*!< Bit position for PORT_PCRn_IRQC. */
00405 #define BM_PORT_PCRn_IRQC    (0x000F0000U) /*!< Bit mask for PORT_PCRn_IRQC. */
00406 #define BS_PORT_PCRn_IRQC    (4U)          /*!< Bit field size in bits for PORT_PCRn_IRQC. */
00407 
00408 /*! @brief Read current value of the PORT_PCRn_IRQC field. */
00409 #define BR_PORT_PCRn_IRQC(x, n) (UNION_READ(hw_port_pcrn_t, HW_PORT_PCRn_ADDR(x, n), U, B.IRQC))
00410 
00411 /*! @brief Format value for bitfield PORT_PCRn_IRQC. */
00412 #define BF_PORT_PCRn_IRQC(v) ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_IRQC) & BM_PORT_PCRn_IRQC)
00413 
00414 /*! @brief Set the IRQC field to a new value. */
00415 #define BW_PORT_PCRn_IRQC(x, n, v) (HW_PORT_PCRn_WR(x, n, (HW_PORT_PCRn_RD(x, n) & ~BM_PORT_PCRn_IRQC) | BF_PORT_PCRn_IRQC(v)))
00416 /*@}*/
00417 
00418 /*!
00419  * @name Register PORT_PCRn, field ISF[24] (W1C)
00420  *
00421  * The pin interrupt configuration is valid in all digital pin muxing modes.
00422  *
00423  * Values:
00424  * - 0 - Configured interrupt is not detected.
00425  * - 1 - Configured interrupt is detected. If the pin is configured to generate
00426  *     a DMA request, then the corresponding flag will be cleared automatically
00427  *     at the completion of the requested DMA transfer. Otherwise, the flag
00428  *     remains set until a logic 1 is written to the flag. If the pin is configured for
00429  *     a level sensitive interrupt and the pin remains asserted, then the flag
00430  *     is set again immediately after it is cleared.
00431  */
00432 /*@{*/
00433 #define BP_PORT_PCRn_ISF     (24U)         /*!< Bit position for PORT_PCRn_ISF. */
00434 #define BM_PORT_PCRn_ISF     (0x01000000U) /*!< Bit mask for PORT_PCRn_ISF. */
00435 #define BS_PORT_PCRn_ISF     (1U)          /*!< Bit field size in bits for PORT_PCRn_ISF. */
00436 
00437 /*! @brief Read current value of the PORT_PCRn_ISF field. */
00438 #define BR_PORT_PCRn_ISF(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF)))
00439 
00440 /*! @brief Format value for bitfield PORT_PCRn_ISF. */
00441 #define BF_PORT_PCRn_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_PCRn_ISF) & BM_PORT_PCRn_ISF)
00442 
00443 /*! @brief Set the ISF field to a new value. */
00444 #define BW_PORT_PCRn_ISF(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_PCRn_ADDR(x, n), BP_PORT_PCRn_ISF), v))
00445 /*@}*/
00446 
00447 /*******************************************************************************
00448  * HW_PORT_GPCLR - Global Pin Control Low Register
00449  ******************************************************************************/
00450 
00451 /*!
00452  * @brief HW_PORT_GPCLR - Global Pin Control Low Register (WORZ)
00453  *
00454  * Reset value: 0x00000000U
00455  *
00456  * Only 32-bit writes are supported to this register.
00457  */
00458 typedef union _hw_port_gpclr
00459 {
00460     uint32_t U;
00461     struct _hw_port_gpclr_bitfields
00462     {
00463         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
00464         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
00465     } B;
00466 } hw_port_gpclr_t;
00467 
00468 /*!
00469  * @name Constants and macros for entire PORT_GPCLR register
00470  */
00471 /*@{*/
00472 #define HW_PORT_GPCLR_ADDR(x)    ((x) + 0x80U)
00473 
00474 #define HW_PORT_GPCLR(x)         (*(__O hw_port_gpclr_t *) HW_PORT_GPCLR_ADDR(x))
00475 #define HW_PORT_GPCLR_RD(x)      (ADDRESS_READ(hw_port_gpclr_t, HW_PORT_GPCLR_ADDR(x)))
00476 #define HW_PORT_GPCLR_WR(x, v)   (ADDRESS_WRITE(hw_port_gpclr_t, HW_PORT_GPCLR_ADDR(x), v))
00477 /*@}*/
00478 
00479 /*
00480  * Constants & macros for individual PORT_GPCLR bitfields
00481  */
00482 
00483 /*!
00484  * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
00485  *
00486  * Write value that is written to all Pin Control Registers bits [15:0] that are
00487  * selected by GPWE.
00488  */
00489 /*@{*/
00490 #define BP_PORT_GPCLR_GPWD   (0U)          /*!< Bit position for PORT_GPCLR_GPWD. */
00491 #define BM_PORT_GPCLR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCLR_GPWD. */
00492 #define BS_PORT_GPCLR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWD. */
00493 
00494 /*! @brief Format value for bitfield PORT_GPCLR_GPWD. */
00495 #define BF_PORT_GPCLR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWD) & BM_PORT_GPCLR_GPWD)
00496 
00497 /*! @brief Set the GPWD field to a new value. */
00498 #define BW_PORT_GPCLR_GPWD(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWD) | BF_PORT_GPCLR_GPWD(v)))
00499 /*@}*/
00500 
00501 /*!
00502  * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
00503  *
00504  * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
00505  * the value in GPWD. If a selected Pin Control Register is locked then the write
00506  * to that register is ignored.
00507  *
00508  * Values:
00509  * - 0 - Corresponding Pin Control Register is not updated with the value in
00510  *     GPWD.
00511  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
00512  */
00513 /*@{*/
00514 #define BP_PORT_GPCLR_GPWE   (16U)         /*!< Bit position for PORT_GPCLR_GPWE. */
00515 #define BM_PORT_GPCLR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCLR_GPWE. */
00516 #define BS_PORT_GPCLR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCLR_GPWE. */
00517 
00518 /*! @brief Format value for bitfield PORT_GPCLR_GPWE. */
00519 #define BF_PORT_GPCLR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCLR_GPWE) & BM_PORT_GPCLR_GPWE)
00520 
00521 /*! @brief Set the GPWE field to a new value. */
00522 #define BW_PORT_GPCLR_GPWE(x, v) (HW_PORT_GPCLR_WR(x, (HW_PORT_GPCLR_RD(x) & ~BM_PORT_GPCLR_GPWE) | BF_PORT_GPCLR_GPWE(v)))
00523 /*@}*/
00524 
00525 /*******************************************************************************
00526  * HW_PORT_GPCHR - Global Pin Control High Register
00527  ******************************************************************************/
00528 
00529 /*!
00530  * @brief HW_PORT_GPCHR - Global Pin Control High Register (WORZ)
00531  *
00532  * Reset value: 0x00000000U
00533  *
00534  * Only 32-bit writes are supported to this register.
00535  */
00536 typedef union _hw_port_gpchr
00537 {
00538     uint32_t U;
00539     struct _hw_port_gpchr_bitfields
00540     {
00541         uint32_t GPWD : 16;            /*!< [15:0] Global Pin Write Data */
00542         uint32_t GPWE : 16;            /*!< [31:16] Global Pin Write Enable */
00543     } B;
00544 } hw_port_gpchr_t;
00545 
00546 /*!
00547  * @name Constants and macros for entire PORT_GPCHR register
00548  */
00549 /*@{*/
00550 #define HW_PORT_GPCHR_ADDR(x)    ((x) + 0x84U)
00551 
00552 #define HW_PORT_GPCHR(x)         (*(__O hw_port_gpchr_t *) HW_PORT_GPCHR_ADDR(x))
00553 #define HW_PORT_GPCHR_RD(x)      (ADDRESS_READ(hw_port_gpchr_t, HW_PORT_GPCHR_ADDR(x)))
00554 #define HW_PORT_GPCHR_WR(x, v)   (ADDRESS_WRITE(hw_port_gpchr_t, HW_PORT_GPCHR_ADDR(x), v))
00555 /*@}*/
00556 
00557 /*
00558  * Constants & macros for individual PORT_GPCHR bitfields
00559  */
00560 
00561 /*!
00562  * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
00563  *
00564  * Write value that is written to all Pin Control Registers bits [15:0] that are
00565  * selected by GPWE.
00566  */
00567 /*@{*/
00568 #define BP_PORT_GPCHR_GPWD   (0U)          /*!< Bit position for PORT_GPCHR_GPWD. */
00569 #define BM_PORT_GPCHR_GPWD   (0x0000FFFFU) /*!< Bit mask for PORT_GPCHR_GPWD. */
00570 #define BS_PORT_GPCHR_GPWD   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWD. */
00571 
00572 /*! @brief Format value for bitfield PORT_GPCHR_GPWD. */
00573 #define BF_PORT_GPCHR_GPWD(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWD) & BM_PORT_GPCHR_GPWD)
00574 
00575 /*! @brief Set the GPWD field to a new value. */
00576 #define BW_PORT_GPCHR_GPWD(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWD) | BF_PORT_GPCHR_GPWD(v)))
00577 /*@}*/
00578 
00579 /*!
00580  * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
00581  *
00582  * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
00583  * the value in GPWD. If a selected Pin Control Register is locked then the write
00584  * to that register is ignored.
00585  *
00586  * Values:
00587  * - 0 - Corresponding Pin Control Register is not updated with the value in
00588  *     GPWD.
00589  * - 1 - Corresponding Pin Control Register is updated with the value in GPWD.
00590  */
00591 /*@{*/
00592 #define BP_PORT_GPCHR_GPWE   (16U)         /*!< Bit position for PORT_GPCHR_GPWE. */
00593 #define BM_PORT_GPCHR_GPWE   (0xFFFF0000U) /*!< Bit mask for PORT_GPCHR_GPWE. */
00594 #define BS_PORT_GPCHR_GPWE   (16U)         /*!< Bit field size in bits for PORT_GPCHR_GPWE. */
00595 
00596 /*! @brief Format value for bitfield PORT_GPCHR_GPWE. */
00597 #define BF_PORT_GPCHR_GPWE(v) ((uint32_t)((uint32_t)(v) << BP_PORT_GPCHR_GPWE) & BM_PORT_GPCHR_GPWE)
00598 
00599 /*! @brief Set the GPWE field to a new value. */
00600 #define BW_PORT_GPCHR_GPWE(x, v) (HW_PORT_GPCHR_WR(x, (HW_PORT_GPCHR_RD(x) & ~BM_PORT_GPCHR_GPWE) | BF_PORT_GPCHR_GPWE(v)))
00601 /*@}*/
00602 
00603 /*******************************************************************************
00604  * HW_PORT_ISFR - Interrupt Status Flag Register
00605  ******************************************************************************/
00606 
00607 /*!
00608  * @brief HW_PORT_ISFR - Interrupt Status Flag Register (W1C)
00609  *
00610  * Reset value: 0x00000000U
00611  *
00612  * The pin interrupt configuration is valid in all digital pin muxing modes. The
00613  * Interrupt Status Flag for each pin is also visible in the corresponding Pin
00614  * Control Register, and each flag can be cleared in either location.
00615  */
00616 typedef union _hw_port_isfr
00617 {
00618     uint32_t U;
00619     struct _hw_port_isfr_bitfields
00620     {
00621         uint32_t ISF : 32;             /*!< [31:0] Interrupt Status Flag */
00622     } B;
00623 } hw_port_isfr_t;
00624 
00625 /*!
00626  * @name Constants and macros for entire PORT_ISFR register
00627  */
00628 /*@{*/
00629 #define HW_PORT_ISFR_ADDR(x)     ((x) + 0xA0U)
00630 
00631 #define HW_PORT_ISFR(x)          (*(__IO hw_port_isfr_t *) HW_PORT_ISFR_ADDR(x))
00632 #define HW_PORT_ISFR_RD(x)       (ADDRESS_READ(hw_port_isfr_t, HW_PORT_ISFR_ADDR(x)))
00633 #define HW_PORT_ISFR_WR(x, v)    (ADDRESS_WRITE(hw_port_isfr_t, HW_PORT_ISFR_ADDR(x), v))
00634 #define HW_PORT_ISFR_SET(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) |  (v)))
00635 #define HW_PORT_ISFR_CLR(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) & ~(v)))
00636 #define HW_PORT_ISFR_TOG(x, v)   (HW_PORT_ISFR_WR(x, HW_PORT_ISFR_RD(x) ^  (v)))
00637 /*@}*/
00638 
00639 /*
00640  * Constants & macros for individual PORT_ISFR bitfields
00641  */
00642 
00643 /*!
00644  * @name Register PORT_ISFR, field ISF[31:0] (W1C)
00645  *
00646  * Each bit in the field indicates the detection of the configured interrupt of
00647  * the same number as the field.
00648  *
00649  * Values:
00650  * - 0 - Configured interrupt is not detected.
00651  * - 1 - Configured interrupt is detected. If the pin is configured to generate
00652  *     a DMA request, then the corresponding flag will be cleared automatically
00653  *     at the completion of the requested DMA transfer. Otherwise, the flag
00654  *     remains set until a logic 1 is written to the flag. If the pin is configured for
00655  *     a level sensitive interrupt and the pin remains asserted, then the flag
00656  *     is set again immediately after it is cleared.
00657  */
00658 /*@{*/
00659 #define BP_PORT_ISFR_ISF     (0U)          /*!< Bit position for PORT_ISFR_ISF. */
00660 #define BM_PORT_ISFR_ISF     (0xFFFFFFFFU) /*!< Bit mask for PORT_ISFR_ISF. */
00661 #define BS_PORT_ISFR_ISF     (32U)         /*!< Bit field size in bits for PORT_ISFR_ISF. */
00662 
00663 /*! @brief Read current value of the PORT_ISFR_ISF field. */
00664 #define BR_PORT_ISFR_ISF(x)  (HW_PORT_ISFR(x).U)
00665 
00666 /*! @brief Format value for bitfield PORT_ISFR_ISF. */
00667 #define BF_PORT_ISFR_ISF(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_ISFR_ISF) & BM_PORT_ISFR_ISF)
00668 
00669 /*! @brief Set the ISF field to a new value. */
00670 #define BW_PORT_ISFR_ISF(x, v) (HW_PORT_ISFR_WR(x, v))
00671 /*@}*/
00672 
00673 /*******************************************************************************
00674  * HW_PORT_DFER - Digital Filter Enable Register
00675  ******************************************************************************/
00676 
00677 /*!
00678  * @brief HW_PORT_DFER - Digital Filter Enable Register (RW)
00679  *
00680  * Reset value: 0x00000000U
00681  *
00682  * The corresponding bit is read only for pins that do not support a digital
00683  * filter. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
00684  * the pins that support digital filter. The digital filter configuration is valid
00685  * in all digital pin muxing modes.
00686  */
00687 typedef union _hw_port_dfer
00688 {
00689     uint32_t U;
00690     struct _hw_port_dfer_bitfields
00691     {
00692         uint32_t DFE : 32;             /*!< [31:0] Digital Filter Enable */
00693     } B;
00694 } hw_port_dfer_t;
00695 
00696 /*!
00697  * @name Constants and macros for entire PORT_DFER register
00698  */
00699 /*@{*/
00700 #define HW_PORT_DFER_ADDR(x)     ((x) + 0xC0U)
00701 
00702 #define HW_PORT_DFER(x)          (*(__IO hw_port_dfer_t *) HW_PORT_DFER_ADDR(x))
00703 #define HW_PORT_DFER_RD(x)       (ADDRESS_READ(hw_port_dfer_t, HW_PORT_DFER_ADDR(x)))
00704 #define HW_PORT_DFER_WR(x, v)    (ADDRESS_WRITE(hw_port_dfer_t, HW_PORT_DFER_ADDR(x), v))
00705 #define HW_PORT_DFER_SET(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) |  (v)))
00706 #define HW_PORT_DFER_CLR(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) & ~(v)))
00707 #define HW_PORT_DFER_TOG(x, v)   (HW_PORT_DFER_WR(x, HW_PORT_DFER_RD(x) ^  (v)))
00708 /*@}*/
00709 
00710 /*
00711  * Constants & macros for individual PORT_DFER bitfields
00712  */
00713 
00714 /*!
00715  * @name Register PORT_DFER, field DFE[31:0] (RW)
00716  *
00717  * The digital filter configuration is valid in all digital pin muxing modes.
00718  * The output of each digital filter is reset to zero at system reset and whenever
00719  * the digital filter is disabled. Each bit in the field enables the digital
00720  * filter of the same number as the field.
00721  *
00722  * Values:
00723  * - 0 - Digital filter is disabled on the corresponding pin and output of the
00724  *     digital filter is reset to zero.
00725  * - 1 - Digital filter is enabled on the corresponding pin, if the pin is
00726  *     configured as a digital input.
00727  */
00728 /*@{*/
00729 #define BP_PORT_DFER_DFE     (0U)          /*!< Bit position for PORT_DFER_DFE. */
00730 #define BM_PORT_DFER_DFE     (0xFFFFFFFFU) /*!< Bit mask for PORT_DFER_DFE. */
00731 #define BS_PORT_DFER_DFE     (32U)         /*!< Bit field size in bits for PORT_DFER_DFE. */
00732 
00733 /*! @brief Read current value of the PORT_DFER_DFE field. */
00734 #define BR_PORT_DFER_DFE(x)  (HW_PORT_DFER(x).U)
00735 
00736 /*! @brief Format value for bitfield PORT_DFER_DFE. */
00737 #define BF_PORT_DFER_DFE(v)  ((uint32_t)((uint32_t)(v) << BP_PORT_DFER_DFE) & BM_PORT_DFER_DFE)
00738 
00739 /*! @brief Set the DFE field to a new value. */
00740 #define BW_PORT_DFER_DFE(x, v) (HW_PORT_DFER_WR(x, v))
00741 /*@}*/
00742 
00743 /*******************************************************************************
00744  * HW_PORT_DFCR - Digital Filter Clock Register
00745  ******************************************************************************/
00746 
00747 /*!
00748  * @brief HW_PORT_DFCR - Digital Filter Clock Register (RW)
00749  *
00750  * Reset value: 0x00000000U
00751  *
00752  * This register is read only for ports that do not support a digital filter.
00753  * The digital filter configuration is valid in all digital pin muxing modes.
00754  */
00755 typedef union _hw_port_dfcr
00756 {
00757     uint32_t U;
00758     struct _hw_port_dfcr_bitfields
00759     {
00760         uint32_t CS : 1;               /*!< [0] Clock Source */
00761         uint32_t RESERVED0 : 31;       /*!< [31:1]  */
00762     } B;
00763 } hw_port_dfcr_t;
00764 
00765 /*!
00766  * @name Constants and macros for entire PORT_DFCR register
00767  */
00768 /*@{*/
00769 #define HW_PORT_DFCR_ADDR(x)     ((x) + 0xC4U)
00770 
00771 #define HW_PORT_DFCR(x)          (*(__IO hw_port_dfcr_t *) HW_PORT_DFCR_ADDR(x))
00772 #define HW_PORT_DFCR_RD(x)       (ADDRESS_READ(hw_port_dfcr_t, HW_PORT_DFCR_ADDR(x)))
00773 #define HW_PORT_DFCR_WR(x, v)    (ADDRESS_WRITE(hw_port_dfcr_t, HW_PORT_DFCR_ADDR(x), v))
00774 #define HW_PORT_DFCR_SET(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) |  (v)))
00775 #define HW_PORT_DFCR_CLR(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) & ~(v)))
00776 #define HW_PORT_DFCR_TOG(x, v)   (HW_PORT_DFCR_WR(x, HW_PORT_DFCR_RD(x) ^  (v)))
00777 /*@}*/
00778 
00779 /*
00780  * Constants & macros for individual PORT_DFCR bitfields
00781  */
00782 
00783 /*!
00784  * @name Register PORT_DFCR, field CS[0] (RW)
00785  *
00786  * The digital filter configuration is valid in all digital pin muxing modes.
00787  * Configures the clock source for the digital input filters. Changing the filter
00788  * clock source must be done only when all digital filters are disabled.
00789  *
00790  * Values:
00791  * - 0 - Digital filters are clocked by the bus clock.
00792  * - 1 - Digital filters are clocked by the 1 kHz LPO clock.
00793  */
00794 /*@{*/
00795 #define BP_PORT_DFCR_CS      (0U)          /*!< Bit position for PORT_DFCR_CS. */
00796 #define BM_PORT_DFCR_CS      (0x00000001U) /*!< Bit mask for PORT_DFCR_CS. */
00797 #define BS_PORT_DFCR_CS      (1U)          /*!< Bit field size in bits for PORT_DFCR_CS. */
00798 
00799 /*! @brief Read current value of the PORT_DFCR_CS field. */
00800 #define BR_PORT_DFCR_CS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS)))
00801 
00802 /*! @brief Format value for bitfield PORT_DFCR_CS. */
00803 #define BF_PORT_DFCR_CS(v)   ((uint32_t)((uint32_t)(v) << BP_PORT_DFCR_CS) & BM_PORT_DFCR_CS)
00804 
00805 /*! @brief Set the CS field to a new value. */
00806 #define BW_PORT_DFCR_CS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PORT_DFCR_ADDR(x), BP_PORT_DFCR_CS), v))
00807 /*@}*/
00808 
00809 /*******************************************************************************
00810  * HW_PORT_DFWR - Digital Filter Width Register
00811  ******************************************************************************/
00812 
00813 /*!
00814  * @brief HW_PORT_DFWR - Digital Filter Width Register (RW)
00815  *
00816  * Reset value: 0x00000000U
00817  *
00818  * This register is read only for ports that do not support a digital filter.
00819  * The digital filter configuration is valid in all digital pin muxing modes.
00820  */
00821 typedef union _hw_port_dfwr
00822 {
00823     uint32_t U;
00824     struct _hw_port_dfwr_bitfields
00825     {
00826         uint32_t FILT : 5;             /*!< [4:0] Filter Length */
00827         uint32_t RESERVED0 : 27;       /*!< [31:5]  */
00828     } B;
00829 } hw_port_dfwr_t;
00830 
00831 /*!
00832  * @name Constants and macros for entire PORT_DFWR register
00833  */
00834 /*@{*/
00835 #define HW_PORT_DFWR_ADDR(x)     ((x) + 0xC8U)
00836 
00837 #define HW_PORT_DFWR(x)          (*(__IO hw_port_dfwr_t *) HW_PORT_DFWR_ADDR(x))
00838 #define HW_PORT_DFWR_RD(x)       (ADDRESS_READ(hw_port_dfwr_t, HW_PORT_DFWR_ADDR(x)))
00839 #define HW_PORT_DFWR_WR(x, v)    (ADDRESS_WRITE(hw_port_dfwr_t, HW_PORT_DFWR_ADDR(x), v))
00840 #define HW_PORT_DFWR_SET(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) |  (v)))
00841 #define HW_PORT_DFWR_CLR(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) & ~(v)))
00842 #define HW_PORT_DFWR_TOG(x, v)   (HW_PORT_DFWR_WR(x, HW_PORT_DFWR_RD(x) ^  (v)))
00843 /*@}*/
00844 
00845 /*
00846  * Constants & macros for individual PORT_DFWR bitfields
00847  */
00848 
00849 /*!
00850  * @name Register PORT_DFWR, field FILT[4:0] (RW)
00851  *
00852  * The digital filter configuration is valid in all digital pin muxing modes.
00853  * Configures the maximum size of the glitches, in clock cycles, that the digital
00854  * filter absorbs for the enabled digital filters. Glitches that are longer than
00855  * this register setting will pass through the digital filter, and glitches that
00856  * are equal to or less than this register setting are filtered. Changing the
00857  * filter length must be done only after all filters are disabled.
00858  */
00859 /*@{*/
00860 #define BP_PORT_DFWR_FILT    (0U)          /*!< Bit position for PORT_DFWR_FILT. */
00861 #define BM_PORT_DFWR_FILT    (0x0000001FU) /*!< Bit mask for PORT_DFWR_FILT. */
00862 #define BS_PORT_DFWR_FILT    (5U)          /*!< Bit field size in bits for PORT_DFWR_FILT. */
00863 
00864 /*! @brief Read current value of the PORT_DFWR_FILT field. */
00865 #define BR_PORT_DFWR_FILT(x) (UNION_READ(hw_port_dfwr_t, HW_PORT_DFWR_ADDR(x), U, B.FILT))
00866 
00867 /*! @brief Format value for bitfield PORT_DFWR_FILT. */
00868 #define BF_PORT_DFWR_FILT(v) ((uint32_t)((uint32_t)(v) << BP_PORT_DFWR_FILT) & BM_PORT_DFWR_FILT)
00869 
00870 /*! @brief Set the FILT field to a new value. */
00871 #define BW_PORT_DFWR_FILT(x, v) (HW_PORT_DFWR_WR(x, (HW_PORT_DFWR_RD(x) & ~BM_PORT_DFWR_FILT) | BF_PORT_DFWR_FILT(v)))
00872 /*@}*/
00873 
00874 /*******************************************************************************
00875  * hw_port_t - module struct
00876  ******************************************************************************/
00877 /*!
00878  * @brief All PORT module registers.
00879  */
00880 #pragma pack(1)
00881 typedef struct _hw_port
00882 {
00883     __IO hw_port_pcrn_t PCRn [32];          /*!< [0x0] Pin Control Register n */
00884     __O hw_port_gpclr_t GPCLR ;             /*!< [0x80] Global Pin Control Low Register */
00885     __O hw_port_gpchr_t GPCHR ;             /*!< [0x84] Global Pin Control High Register */
00886     uint8_t _reserved0[24];
00887     __IO hw_port_isfr_t ISFR ;              /*!< [0xA0] Interrupt Status Flag Register */
00888     uint8_t _reserved1[28];
00889     __IO hw_port_dfer_t DFER ;              /*!< [0xC0] Digital Filter Enable Register */
00890     __IO hw_port_dfcr_t DFCR ;              /*!< [0xC4] Digital Filter Clock Register */
00891     __IO hw_port_dfwr_t DFWR ;              /*!< [0xC8] Digital Filter Width Register */
00892 } hw_port_t;
00893 #pragma pack()
00894 
00895 /*! @brief Macro to access all PORT registers. */
00896 /*! @param x PORT module instance base address. */
00897 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00898  *     use the '&' operator, like <code>&HW_PORT(PORTA_BASE)</code>. */
00899 #define HW_PORT(x)     (*(hw_port_t *)(x))
00900 
00901 #endif /* __HW_PORT_REGISTERS_H__ */
00902 /* EOF */