MK64F12_pit.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_PIT_REGISTERS_H__
00088 #define __HW_PIT_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 PIT
00095  *
00096  * Periodic Interrupt Timer
00097  *
00098  * Registers defined in this header file:
00099  * - HW_PIT_MCR - PIT Module Control Register
00100  * - HW_PIT_LDVALn - Timer Load Value Register
00101  * - HW_PIT_CVALn - Current Timer Value Register
00102  * - HW_PIT_TCTRLn - Timer Control Register
00103  * - HW_PIT_TFLGn - Timer Flag Register
00104  *
00105  * - hw_pit_t - Struct containing all module registers.
00106  */
00107 
00108 #define HW_PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
00109 
00110 /*******************************************************************************
00111  * HW_PIT_MCR - PIT Module Control Register
00112  ******************************************************************************/
00113 
00114 /*!
00115  * @brief HW_PIT_MCR - PIT Module Control Register (RW)
00116  *
00117  * Reset value: 0x00000006U
00118  *
00119  * This register enables or disables the PIT timer clocks and controls the
00120  * timers when the PIT enters the Debug mode.
00121  */
00122 typedef union _hw_pit_mcr
00123 {
00124     uint32_t U;
00125     struct _hw_pit_mcr_bitfields
00126     {
00127         uint32_t FRZ : 1;              /*!< [0] Freeze */
00128         uint32_t MDIS : 1;             /*!< [1] Module Disable - (PIT section) */
00129         uint32_t RESERVED0 : 30;       /*!< [31:2]  */
00130     } B;
00131 } hw_pit_mcr_t;
00132 
00133 /*!
00134  * @name Constants and macros for entire PIT_MCR register
00135  */
00136 /*@{*/
00137 #define HW_PIT_MCR_ADDR(x)       ((x) + 0x0U)
00138 
00139 #define HW_PIT_MCR(x)            (*(__IO hw_pit_mcr_t *) HW_PIT_MCR_ADDR(x))
00140 #define HW_PIT_MCR_RD(x)         (ADDRESS_READ(hw_pit_mcr_t, HW_PIT_MCR_ADDR(x)))
00141 #define HW_PIT_MCR_WR(x, v)      (ADDRESS_WRITE(hw_pit_mcr_t, HW_PIT_MCR_ADDR(x), v))
00142 #define HW_PIT_MCR_SET(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) |  (v)))
00143 #define HW_PIT_MCR_CLR(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) & ~(v)))
00144 #define HW_PIT_MCR_TOG(x, v)     (HW_PIT_MCR_WR(x, HW_PIT_MCR_RD(x) ^  (v)))
00145 /*@}*/
00146 
00147 /*
00148  * Constants & macros for individual PIT_MCR bitfields
00149  */
00150 
00151 /*!
00152  * @name Register PIT_MCR, field FRZ[0] (RW)
00153  *
00154  * Allows the timers to be stopped when the device enters the Debug mode.
00155  *
00156  * Values:
00157  * - 0 - Timers continue to run in Debug mode.
00158  * - 1 - Timers are stopped in Debug mode.
00159  */
00160 /*@{*/
00161 #define BP_PIT_MCR_FRZ       (0U)          /*!< Bit position for PIT_MCR_FRZ. */
00162 #define BM_PIT_MCR_FRZ       (0x00000001U) /*!< Bit mask for PIT_MCR_FRZ. */
00163 #define BS_PIT_MCR_FRZ       (1U)          /*!< Bit field size in bits for PIT_MCR_FRZ. */
00164 
00165 /*! @brief Read current value of the PIT_MCR_FRZ field. */
00166 #define BR_PIT_MCR_FRZ(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ)))
00167 
00168 /*! @brief Format value for bitfield PIT_MCR_FRZ. */
00169 #define BF_PIT_MCR_FRZ(v)    ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_FRZ) & BM_PIT_MCR_FRZ)
00170 
00171 /*! @brief Set the FRZ field to a new value. */
00172 #define BW_PIT_MCR_FRZ(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_FRZ), v))
00173 /*@}*/
00174 
00175 /*!
00176  * @name Register PIT_MCR, field MDIS[1] (RW)
00177  *
00178  * Disables the standard timers. This field must be enabled before any other
00179  * setup is done.
00180  *
00181  * Values:
00182  * - 0 - Clock for standard PIT timers is enabled.
00183  * - 1 - Clock for standard PIT timers is disabled.
00184  */
00185 /*@{*/
00186 #define BP_PIT_MCR_MDIS      (1U)          /*!< Bit position for PIT_MCR_MDIS. */
00187 #define BM_PIT_MCR_MDIS      (0x00000002U) /*!< Bit mask for PIT_MCR_MDIS. */
00188 #define BS_PIT_MCR_MDIS      (1U)          /*!< Bit field size in bits for PIT_MCR_MDIS. */
00189 
00190 /*! @brief Read current value of the PIT_MCR_MDIS field. */
00191 #define BR_PIT_MCR_MDIS(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS)))
00192 
00193 /*! @brief Format value for bitfield PIT_MCR_MDIS. */
00194 #define BF_PIT_MCR_MDIS(v)   ((uint32_t)((uint32_t)(v) << BP_PIT_MCR_MDIS) & BM_PIT_MCR_MDIS)
00195 
00196 /*! @brief Set the MDIS field to a new value. */
00197 #define BW_PIT_MCR_MDIS(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_MCR_ADDR(x), BP_PIT_MCR_MDIS), v))
00198 /*@}*/
00199 
00200 /*******************************************************************************
00201  * HW_PIT_LDVALn - Timer Load Value Register
00202  ******************************************************************************/
00203 
00204 /*!
00205  * @brief HW_PIT_LDVALn - Timer Load Value Register (RW)
00206  *
00207  * Reset value: 0x00000000U
00208  *
00209  * These registers select the timeout period for the timer interrupts.
00210  */
00211 typedef union _hw_pit_ldvaln
00212 {
00213     uint32_t U;
00214     struct _hw_pit_ldvaln_bitfields
00215     {
00216         uint32_t TSV : 32;             /*!< [31:0] Timer Start Value */
00217     } B;
00218 } hw_pit_ldvaln_t;
00219 
00220 /*!
00221  * @name Constants and macros for entire PIT_LDVALn register
00222  */
00223 /*@{*/
00224 #define HW_PIT_LDVALn_COUNT (4U)
00225 
00226 #define HW_PIT_LDVALn_ADDR(x, n) ((x) + 0x100U + (0x10U * (n)))
00227 
00228 #define HW_PIT_LDVALn(x, n)      (*(__IO hw_pit_ldvaln_t *) HW_PIT_LDVALn_ADDR(x, n))
00229 #define HW_PIT_LDVALn_RD(x, n)   (ADDRESS_READ(hw_pit_ldvaln_t, HW_PIT_LDVALn_ADDR(x, n)))
00230 #define HW_PIT_LDVALn_WR(x, n, v) (ADDRESS_WRITE(hw_pit_ldvaln_t, HW_PIT_LDVALn_ADDR(x, n), v))
00231 #define HW_PIT_LDVALn_SET(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) |  (v)))
00232 #define HW_PIT_LDVALn_CLR(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) & ~(v)))
00233 #define HW_PIT_LDVALn_TOG(x, n, v) (HW_PIT_LDVALn_WR(x, n, HW_PIT_LDVALn_RD(x, n) ^  (v)))
00234 /*@}*/
00235 
00236 /*
00237  * Constants & macros for individual PIT_LDVALn bitfields
00238  */
00239 
00240 /*!
00241  * @name Register PIT_LDVALn, field TSV[31:0] (RW)
00242  *
00243  * Sets the timer start value. The timer will count down until it reaches 0,
00244  * then it will generate an interrupt and load this register value again. Writing a
00245  * new value to this register will not restart the timer; instead the value will
00246  * be loaded after the timer expires. To abort the current cycle and start a
00247  * timer period with the new value, the timer must be disabled and enabled again.
00248  */
00249 /*@{*/
00250 #define BP_PIT_LDVALn_TSV    (0U)          /*!< Bit position for PIT_LDVALn_TSV. */
00251 #define BM_PIT_LDVALn_TSV    (0xFFFFFFFFU) /*!< Bit mask for PIT_LDVALn_TSV. */
00252 #define BS_PIT_LDVALn_TSV    (32U)         /*!< Bit field size in bits for PIT_LDVALn_TSV. */
00253 
00254 /*! @brief Read current value of the PIT_LDVALn_TSV field. */
00255 #define BR_PIT_LDVALn_TSV(x, n) (HW_PIT_LDVALn(x, n).U)
00256 
00257 /*! @brief Format value for bitfield PIT_LDVALn_TSV. */
00258 #define BF_PIT_LDVALn_TSV(v) ((uint32_t)((uint32_t)(v) << BP_PIT_LDVALn_TSV) & BM_PIT_LDVALn_TSV)
00259 
00260 /*! @brief Set the TSV field to a new value. */
00261 #define BW_PIT_LDVALn_TSV(x, n, v) (HW_PIT_LDVALn_WR(x, n, v))
00262 /*@}*/
00263 /*******************************************************************************
00264  * HW_PIT_CVALn - Current Timer Value Register
00265  ******************************************************************************/
00266 
00267 /*!
00268  * @brief HW_PIT_CVALn - Current Timer Value Register (RO)
00269  *
00270  * Reset value: 0x00000000U
00271  *
00272  * These registers indicate the current timer position.
00273  */
00274 typedef union _hw_pit_cvaln
00275 {
00276     uint32_t U;
00277     struct _hw_pit_cvaln_bitfields
00278     {
00279         uint32_t TVL : 32;             /*!< [31:0] Current Timer Value */
00280     } B;
00281 } hw_pit_cvaln_t;
00282 
00283 /*!
00284  * @name Constants and macros for entire PIT_CVALn register
00285  */
00286 /*@{*/
00287 #define HW_PIT_CVALn_COUNT (4U)
00288 
00289 #define HW_PIT_CVALn_ADDR(x, n)  ((x) + 0x104U + (0x10U * (n)))
00290 
00291 #define HW_PIT_CVALn(x, n)       (*(__I hw_pit_cvaln_t *) HW_PIT_CVALn_ADDR(x, n))
00292 #define HW_PIT_CVALn_RD(x, n)    (ADDRESS_READ(hw_pit_cvaln_t, HW_PIT_CVALn_ADDR(x, n)))
00293 /*@}*/
00294 
00295 /*
00296  * Constants & macros for individual PIT_CVALn bitfields
00297  */
00298 
00299 /*!
00300  * @name Register PIT_CVALn, field TVL[31:0] (RO)
00301  *
00302  * Represents the current timer value, if the timer is enabled. If the timer is
00303  * disabled, do not use this field as its value is unreliable. The timer uses a
00304  * downcounter. The timer values are frozen in Debug mode if MCR[FRZ] is set.
00305  */
00306 /*@{*/
00307 #define BP_PIT_CVALn_TVL     (0U)          /*!< Bit position for PIT_CVALn_TVL. */
00308 #define BM_PIT_CVALn_TVL     (0xFFFFFFFFU) /*!< Bit mask for PIT_CVALn_TVL. */
00309 #define BS_PIT_CVALn_TVL     (32U)         /*!< Bit field size in bits for PIT_CVALn_TVL. */
00310 
00311 /*! @brief Read current value of the PIT_CVALn_TVL field. */
00312 #define BR_PIT_CVALn_TVL(x, n) (HW_PIT_CVALn(x, n).U)
00313 /*@}*/
00314 /*******************************************************************************
00315  * HW_PIT_TCTRLn - Timer Control Register
00316  ******************************************************************************/
00317 
00318 /*!
00319  * @brief HW_PIT_TCTRLn - Timer Control Register (RW)
00320  *
00321  * Reset value: 0x00000000U
00322  *
00323  * These registers contain the control bits for each timer.
00324  */
00325 typedef union _hw_pit_tctrln
00326 {
00327     uint32_t U;
00328     struct _hw_pit_tctrln_bitfields
00329     {
00330         uint32_t TEN : 1;              /*!< [0] Timer Enable */
00331         uint32_t TIE : 1;              /*!< [1] Timer Interrupt Enable */
00332         uint32_t CHN : 1;              /*!< [2] Chain Mode */
00333         uint32_t RESERVED0 : 29;       /*!< [31:3]  */
00334     } B;
00335 } hw_pit_tctrln_t;
00336 
00337 /*!
00338  * @name Constants and macros for entire PIT_TCTRLn register
00339  */
00340 /*@{*/
00341 #define HW_PIT_TCTRLn_COUNT (4U)
00342 
00343 #define HW_PIT_TCTRLn_ADDR(x, n) ((x) + 0x108U + (0x10U * (n)))
00344 
00345 #define HW_PIT_TCTRLn(x, n)      (*(__IO hw_pit_tctrln_t *) HW_PIT_TCTRLn_ADDR(x, n))
00346 #define HW_PIT_TCTRLn_RD(x, n)   (ADDRESS_READ(hw_pit_tctrln_t, HW_PIT_TCTRLn_ADDR(x, n)))
00347 #define HW_PIT_TCTRLn_WR(x, n, v) (ADDRESS_WRITE(hw_pit_tctrln_t, HW_PIT_TCTRLn_ADDR(x, n), v))
00348 #define HW_PIT_TCTRLn_SET(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) |  (v)))
00349 #define HW_PIT_TCTRLn_CLR(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) & ~(v)))
00350 #define HW_PIT_TCTRLn_TOG(x, n, v) (HW_PIT_TCTRLn_WR(x, n, HW_PIT_TCTRLn_RD(x, n) ^  (v)))
00351 /*@}*/
00352 
00353 /*
00354  * Constants & macros for individual PIT_TCTRLn bitfields
00355  */
00356 
00357 /*!
00358  * @name Register PIT_TCTRLn, field TEN[0] (RW)
00359  *
00360  * Enables or disables the timer.
00361  *
00362  * Values:
00363  * - 0 - Timer n is disabled.
00364  * - 1 - Timer n is enabled.
00365  */
00366 /*@{*/
00367 #define BP_PIT_TCTRLn_TEN    (0U)          /*!< Bit position for PIT_TCTRLn_TEN. */
00368 #define BM_PIT_TCTRLn_TEN    (0x00000001U) /*!< Bit mask for PIT_TCTRLn_TEN. */
00369 #define BS_PIT_TCTRLn_TEN    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_TEN. */
00370 
00371 /*! @brief Read current value of the PIT_TCTRLn_TEN field. */
00372 #define BR_PIT_TCTRLn_TEN(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN)))
00373 
00374 /*! @brief Format value for bitfield PIT_TCTRLn_TEN. */
00375 #define BF_PIT_TCTRLn_TEN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TEN) & BM_PIT_TCTRLn_TEN)
00376 
00377 /*! @brief Set the TEN field to a new value. */
00378 #define BW_PIT_TCTRLn_TEN(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TEN), v))
00379 /*@}*/
00380 
00381 /*!
00382  * @name Register PIT_TCTRLn, field TIE[1] (RW)
00383  *
00384  * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
00385  * will immediately cause an interrupt event. To avoid this, the associated
00386  * TFLGn[TIF] must be cleared first.
00387  *
00388  * Values:
00389  * - 0 - Interrupt requests from Timer n are disabled.
00390  * - 1 - Interrupt will be requested whenever TIF is set.
00391  */
00392 /*@{*/
00393 #define BP_PIT_TCTRLn_TIE    (1U)          /*!< Bit position for PIT_TCTRLn_TIE. */
00394 #define BM_PIT_TCTRLn_TIE    (0x00000002U) /*!< Bit mask for PIT_TCTRLn_TIE. */
00395 #define BS_PIT_TCTRLn_TIE    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_TIE. */
00396 
00397 /*! @brief Read current value of the PIT_TCTRLn_TIE field. */
00398 #define BR_PIT_TCTRLn_TIE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE)))
00399 
00400 /*! @brief Format value for bitfield PIT_TCTRLn_TIE. */
00401 #define BF_PIT_TCTRLn_TIE(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_TIE) & BM_PIT_TCTRLn_TIE)
00402 
00403 /*! @brief Set the TIE field to a new value. */
00404 #define BW_PIT_TCTRLn_TIE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_TIE), v))
00405 /*@}*/
00406 
00407 /*!
00408  * @name Register PIT_TCTRLn, field CHN[2] (RW)
00409  *
00410  * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
00411  * Timer 0 cannot be chained.
00412  *
00413  * Values:
00414  * - 0 - Timer is not chained.
00415  * - 1 - Timer is chained to previous timer. For example, for Channel 2, if this
00416  *     field is set, Timer 2 is chained to Timer 1.
00417  */
00418 /*@{*/
00419 #define BP_PIT_TCTRLn_CHN    (2U)          /*!< Bit position for PIT_TCTRLn_CHN. */
00420 #define BM_PIT_TCTRLn_CHN    (0x00000004U) /*!< Bit mask for PIT_TCTRLn_CHN. */
00421 #define BS_PIT_TCTRLn_CHN    (1U)          /*!< Bit field size in bits for PIT_TCTRLn_CHN. */
00422 
00423 /*! @brief Read current value of the PIT_TCTRLn_CHN field. */
00424 #define BR_PIT_TCTRLn_CHN(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN)))
00425 
00426 /*! @brief Format value for bitfield PIT_TCTRLn_CHN. */
00427 #define BF_PIT_TCTRLn_CHN(v) ((uint32_t)((uint32_t)(v) << BP_PIT_TCTRLn_CHN) & BM_PIT_TCTRLn_CHN)
00428 
00429 /*! @brief Set the CHN field to a new value. */
00430 #define BW_PIT_TCTRLn_CHN(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_TCTRLn_ADDR(x, n), BP_PIT_TCTRLn_CHN), v))
00431 /*@}*/
00432 /*******************************************************************************
00433  * HW_PIT_TFLGn - Timer Flag Register
00434  ******************************************************************************/
00435 
00436 /*!
00437  * @brief HW_PIT_TFLGn - Timer Flag Register (RW)
00438  *
00439  * Reset value: 0x00000000U
00440  *
00441  * These registers hold the PIT interrupt flags.
00442  */
00443 typedef union _hw_pit_tflgn
00444 {
00445     uint32_t U;
00446     struct _hw_pit_tflgn_bitfields
00447     {
00448         uint32_t TIF : 1;              /*!< [0] Timer Interrupt Flag */
00449         uint32_t RESERVED0 : 31;       /*!< [31:1]  */
00450     } B;
00451 } hw_pit_tflgn_t;
00452 
00453 /*!
00454  * @name Constants and macros for entire PIT_TFLGn register
00455  */
00456 /*@{*/
00457 #define HW_PIT_TFLGn_COUNT (4U)
00458 
00459 #define HW_PIT_TFLGn_ADDR(x, n)  ((x) + 0x10CU + (0x10U * (n)))
00460 
00461 #define HW_PIT_TFLGn(x, n)       (*(__IO hw_pit_tflgn_t *) HW_PIT_TFLGn_ADDR(x, n))
00462 #define HW_PIT_TFLGn_RD(x, n)    (ADDRESS_READ(hw_pit_tflgn_t, HW_PIT_TFLGn_ADDR(x, n)))
00463 #define HW_PIT_TFLGn_WR(x, n, v) (ADDRESS_WRITE(hw_pit_tflgn_t, HW_PIT_TFLGn_ADDR(x, n), v))
00464 #define HW_PIT_TFLGn_SET(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) |  (v)))
00465 #define HW_PIT_TFLGn_CLR(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) & ~(v)))
00466 #define HW_PIT_TFLGn_TOG(x, n, v) (HW_PIT_TFLGn_WR(x, n, HW_PIT_TFLGn_RD(x, n) ^  (v)))
00467 /*@}*/
00468 
00469 /*
00470  * Constants & macros for individual PIT_TFLGn bitfields
00471  */
00472 
00473 /*!
00474  * @name Register PIT_TFLGn, field TIF[0] (W1C)
00475  *
00476  * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
00477  * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
00478  * interrupt request.
00479  *
00480  * Values:
00481  * - 0 - Timeout has not yet occurred.
00482  * - 1 - Timeout has occurred.
00483  */
00484 /*@{*/
00485 #define BP_PIT_TFLGn_TIF     (0U)          /*!< Bit position for PIT_TFLGn_TIF. */
00486 #define BM_PIT_TFLGn_TIF     (0x00000001U) /*!< Bit mask for PIT_TFLGn_TIF. */
00487 #define BS_PIT_TFLGn_TIF     (1U)          /*!< Bit field size in bits for PIT_TFLGn_TIF. */
00488 
00489 /*! @brief Read current value of the PIT_TFLGn_TIF field. */
00490 #define BR_PIT_TFLGn_TIF(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF)))
00491 
00492 /*! @brief Format value for bitfield PIT_TFLGn_TIF. */
00493 #define BF_PIT_TFLGn_TIF(v)  ((uint32_t)((uint32_t)(v) << BP_PIT_TFLGn_TIF) & BM_PIT_TFLGn_TIF)
00494 
00495 /*! @brief Set the TIF field to a new value. */
00496 #define BW_PIT_TFLGn_TIF(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PIT_TFLGn_ADDR(x, n), BP_PIT_TFLGn_TIF), v))
00497 /*@}*/
00498 
00499 /*******************************************************************************
00500  * hw_pit_t - module struct
00501  ******************************************************************************/
00502 /*!
00503  * @brief All PIT module registers.
00504  */
00505 #pragma pack(1)
00506 typedef struct _hw_pit
00507 {
00508     __IO hw_pit_mcr_t MCR ;                 /*!< [0x0] PIT Module Control Register */
00509     uint8_t _reserved0[252];
00510     struct {
00511         __IO hw_pit_ldvaln_t LDVALn ;       /*!< [0x100] Timer Load Value Register */
00512         __I hw_pit_cvaln_t CVALn ;          /*!< [0x104] Current Timer Value Register */
00513         __IO hw_pit_tctrln_t TCTRLn ;       /*!< [0x108] Timer Control Register */
00514         __IO hw_pit_tflgn_t TFLGn ;         /*!< [0x10C] Timer Flag Register */
00515     } CHANNEL[4];
00516 } hw_pit_t;
00517 #pragma pack()
00518 
00519 /*! @brief Macro to access all PIT registers. */
00520 /*! @param x PIT module instance base address. */
00521 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
00522  *     use the '&' operator, like <code>&HW_PIT(PIT_BASE)</code>. */
00523 #define HW_PIT(x)      (*(hw_pit_t *)(x))
00524 
00525 #endif /* __HW_PIT_REGISTERS_H__ */
00526 /* EOF */