MK64F12_pdb.h

00001 /*
00002 ** ###################################################################
00003 **     Compilers:           Keil ARM C/C++ Compiler
00004 **                          Freescale C/C++ for Embedded ARM
00005 **                          GNU C Compiler
00006 **                          IAR ANSI C/C++ Compiler for ARM
00007 **
00008 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
00009 **     Version:             rev. 2.5, 2014-02-10
00010 **     Build:               b140604
00011 **
00012 **     Abstract:
00013 **         Extension to the CMSIS register access layer header.
00014 **
00015 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
00016 **     All rights reserved.
00017 **
00018 **     (C) COPYRIGHT 2015-2015 ARM Limited
00019 **     ALL RIGHTS RESERVED
00020 **
00021 **     Redistribution and use in source and binary forms, with or without modification,
00022 **     are permitted provided that the following conditions are met:
00023 **
00024 **     o Redistributions of source code must retain the above copyright notice, this list
00025 **       of conditions and the following disclaimer.
00026 **
00027 **     o Redistributions in binary form must reproduce the above copyright notice, this
00028 **       list of conditions and the following disclaimer in the documentation and/or
00029 **       other materials provided with the distribution.
00030 **
00031 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
00032 **       contributors may be used to endorse or promote products derived from this
00033 **       software without specific prior written permission.
00034 **
00035 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
00036 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
00037 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00038 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
00039 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
00040 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
00041 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
00042 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
00043 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
00044 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00045 **
00046 **     http:                 www.freescale.com
00047 **     mail:                 support@freescale.com
00048 **
00049 **     Revisions:
00050 **     - rev. 1.0 (2013-08-12)
00051 **         Initial version.
00052 **     - rev. 2.0 (2013-10-29)
00053 **         Register accessor macros added to the memory map.
00054 **         Symbols for Processor Expert memory map compatibility added to the memory map.
00055 **         Startup file for gcc has been updated according to CMSIS 3.2.
00056 **         System initialization updated.
00057 **         MCG - registers updated.
00058 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
00059 **     - rev. 2.1 (2013-10-30)
00060 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
00061 **     - rev. 2.2 (2013-12-09)
00062 **         DMA - EARS register removed.
00063 **         AIPS0, AIPS1 - MPRA register updated.
00064 **     - rev. 2.3 (2014-01-24)
00065 **         Update according to reference manual rev. 2
00066 **         ENET, MCG, MCM, SIM, USB - registers updated
00067 **     - rev. 2.4 (2014-02-10)
00068 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00069 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00070 **     - rev. 2.5 (2014-02-10)
00071 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
00072 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
00073 **         Module access macro module_BASES replaced by module_BASE_PTRS.
00074 **     - rev. 2.6 (2015-08-03) (ARM)
00075 **         All accesses to memory are replaced by equivalent macros; this allows
00076 **         memory read/write operations to be re-defined if needed (for example,
00077 **         to implement new security features
00078 **
00079 ** ###################################################################
00080 */
00081 
00082 /*
00083  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
00084  *
00085  * This file was generated automatically and any changes may be lost.
00086  */
00087 #ifndef __HW_PDB_REGISTERS_H__
00088 #define __HW_PDB_REGISTERS_H__
00089 
00090 #include "MK64F12.h"
00091 #include "fsl_bitaccess.h"
00092 
00093 /*
00094  * MK64F12 PDB
00095  *
00096  * Programmable Delay Block
00097  *
00098  * Registers defined in this header file:
00099  * - HW_PDB_SC - Status and Control register
00100  * - HW_PDB_MOD - Modulus register
00101  * - HW_PDB_CNT - Counter register
00102  * - HW_PDB_IDLY - Interrupt Delay register
00103  * - HW_PDB_CHnC1 - Channel n Control register 1
00104  * - HW_PDB_CHnS - Channel n Status register
00105  * - HW_PDB_CHnDLY0 - Channel n Delay 0 register
00106  * - HW_PDB_CHnDLY1 - Channel n Delay 1 register
00107  * - HW_PDB_DACINTCn - DAC Interval Trigger n Control register
00108  * - HW_PDB_DACINTn - DAC Interval n register
00109  * - HW_PDB_POEN - Pulse-Out n Enable register
00110  * - HW_PDB_POnDLY - Pulse-Out n Delay register
00111  *
00112  * - hw_pdb_t - Struct containing all module registers.
00113  */
00114 
00115 #define HW_PDB_INSTANCE_COUNT (1U) /*!< Number of instances of the PDB module. */
00116 
00117 /*******************************************************************************
00118  * HW_PDB_SC - Status and Control register
00119  ******************************************************************************/
00120 
00121 /*!
00122  * @brief HW_PDB_SC - Status and Control register (RW)
00123  *
00124  * Reset value: 0x00000000U
00125  */
00126 typedef union _hw_pdb_sc
00127 {
00128     uint32_t U;
00129     struct _hw_pdb_sc_bitfields
00130     {
00131         uint32_t LDOK : 1;             /*!< [0] Load OK */
00132         uint32_t CONT : 1;             /*!< [1] Continuous Mode Enable */
00133         uint32_t MULT : 2;             /*!< [3:2] Multiplication Factor Select for
00134                                         * Prescaler */
00135         uint32_t RESERVED0 : 1;        /*!< [4]  */
00136         uint32_t PDBIE : 1;            /*!< [5] PDB Interrupt Enable */
00137         uint32_t PDBIF : 1;            /*!< [6] PDB Interrupt Flag */
00138         uint32_t PDBEN : 1;            /*!< [7] PDB Enable */
00139         uint32_t TRGSEL : 4;           /*!< [11:8] Trigger Input Source Select */
00140         uint32_t PRESCALER : 3;        /*!< [14:12] Prescaler Divider Select */
00141         uint32_t DMAEN : 1;            /*!< [15] DMA Enable */
00142         uint32_t SWTRIG : 1;           /*!< [16] Software Trigger */
00143         uint32_t PDBEIE : 1;           /*!< [17] PDB Sequence Error Interrupt Enable */
00144         uint32_t LDMOD : 2;            /*!< [19:18] Load Mode Select */
00145         uint32_t RESERVED1 : 12;       /*!< [31:20]  */
00146     } B;
00147 } hw_pdb_sc_t;
00148 
00149 /*!
00150  * @name Constants and macros for entire PDB_SC register
00151  */
00152 /*@{*/
00153 #define HW_PDB_SC_ADDR(x)        ((x) + 0x0U)
00154 
00155 #define HW_PDB_SC(x)             (*(__IO hw_pdb_sc_t *) HW_PDB_SC_ADDR(x))
00156 #define HW_PDB_SC_RD(x)          (ADDRESS_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x)))
00157 #define HW_PDB_SC_WR(x, v)       (ADDRESS_WRITE(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), v))
00158 #define HW_PDB_SC_SET(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) |  (v)))
00159 #define HW_PDB_SC_CLR(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) & ~(v)))
00160 #define HW_PDB_SC_TOG(x, v)      (HW_PDB_SC_WR(x, HW_PDB_SC_RD(x) ^  (v)))
00161 /*@}*/
00162 
00163 /*
00164  * Constants & macros for individual PDB_SC bitfields
00165  */
00166 
00167 /*!
00168  * @name Register PDB_SC, field LDOK[0] (RW)
00169  *
00170  * Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm,
00171  * DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY,
00172  * CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD. After 1 is
00173  * written to the LDOK field, the values in the buffers of above registers are
00174  * not effective and the buffers cannot be written until the values in buffers are
00175  * loaded into their internal registers. LDOK can be written only when PDBEN is
00176  * set or it can be written at the same time with PDBEN being written to 1. It is
00177  * automatically cleared when the values in buffers are loaded into the internal
00178  * registers or the PDBEN is cleared. Writing 0 to it has no effect.
00179  */
00180 /*@{*/
00181 #define BP_PDB_SC_LDOK       (0U)          /*!< Bit position for PDB_SC_LDOK. */
00182 #define BM_PDB_SC_LDOK       (0x00000001U) /*!< Bit mask for PDB_SC_LDOK. */
00183 #define BS_PDB_SC_LDOK       (1U)          /*!< Bit field size in bits for PDB_SC_LDOK. */
00184 
00185 /*! @brief Read current value of the PDB_SC_LDOK field. */
00186 #define BR_PDB_SC_LDOK(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK)))
00187 
00188 /*! @brief Format value for bitfield PDB_SC_LDOK. */
00189 #define BF_PDB_SC_LDOK(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDOK) & BM_PDB_SC_LDOK)
00190 
00191 /*! @brief Set the LDOK field to a new value. */
00192 #define BW_PDB_SC_LDOK(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_LDOK), v))
00193 /*@}*/
00194 
00195 /*!
00196  * @name Register PDB_SC, field CONT[1] (RW)
00197  *
00198  * Enables the PDB operation in Continuous mode.
00199  *
00200  * Values:
00201  * - 0 - PDB operation in One-Shot mode
00202  * - 1 - PDB operation in Continuous mode
00203  */
00204 /*@{*/
00205 #define BP_PDB_SC_CONT       (1U)          /*!< Bit position for PDB_SC_CONT. */
00206 #define BM_PDB_SC_CONT       (0x00000002U) /*!< Bit mask for PDB_SC_CONT. */
00207 #define BS_PDB_SC_CONT       (1U)          /*!< Bit field size in bits for PDB_SC_CONT. */
00208 
00209 /*! @brief Read current value of the PDB_SC_CONT field. */
00210 #define BR_PDB_SC_CONT(x)    (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT)))
00211 
00212 /*! @brief Format value for bitfield PDB_SC_CONT. */
00213 #define BF_PDB_SC_CONT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_CONT) & BM_PDB_SC_CONT)
00214 
00215 /*! @brief Set the CONT field to a new value. */
00216 #define BW_PDB_SC_CONT(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_CONT), v))
00217 /*@}*/
00218 
00219 /*!
00220  * @name Register PDB_SC, field MULT[3:2] (RW)
00221  *
00222  * Selects the multiplication factor of the prescaler divider for the counter
00223  * clock.
00224  *
00225  * Values:
00226  * - 00 - Multiplication factor is 1.
00227  * - 01 - Multiplication factor is 10.
00228  * - 10 - Multiplication factor is 20.
00229  * - 11 - Multiplication factor is 40.
00230  */
00231 /*@{*/
00232 #define BP_PDB_SC_MULT       (2U)          /*!< Bit position for PDB_SC_MULT. */
00233 #define BM_PDB_SC_MULT       (0x0000000CU) /*!< Bit mask for PDB_SC_MULT. */
00234 #define BS_PDB_SC_MULT       (2U)          /*!< Bit field size in bits for PDB_SC_MULT. */
00235 
00236 /*! @brief Read current value of the PDB_SC_MULT field. */
00237 #define BR_PDB_SC_MULT(x)    (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.MULT))
00238 
00239 /*! @brief Format value for bitfield PDB_SC_MULT. */
00240 #define BF_PDB_SC_MULT(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_SC_MULT) & BM_PDB_SC_MULT)
00241 
00242 /*! @brief Set the MULT field to a new value. */
00243 #define BW_PDB_SC_MULT(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_MULT) | BF_PDB_SC_MULT(v)))
00244 /*@}*/
00245 
00246 /*!
00247  * @name Register PDB_SC, field PDBIE[5] (RW)
00248  *
00249  * Enables the PDB interrupt. When this field is set and DMAEN is cleared, PDBIF
00250  * generates a PDB interrupt.
00251  *
00252  * Values:
00253  * - 0 - PDB interrupt disabled.
00254  * - 1 - PDB interrupt enabled.
00255  */
00256 /*@{*/
00257 #define BP_PDB_SC_PDBIE      (5U)          /*!< Bit position for PDB_SC_PDBIE. */
00258 #define BM_PDB_SC_PDBIE      (0x00000020U) /*!< Bit mask for PDB_SC_PDBIE. */
00259 #define BS_PDB_SC_PDBIE      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIE. */
00260 
00261 /*! @brief Read current value of the PDB_SC_PDBIE field. */
00262 #define BR_PDB_SC_PDBIE(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE)))
00263 
00264 /*! @brief Format value for bitfield PDB_SC_PDBIE. */
00265 #define BF_PDB_SC_PDBIE(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIE) & BM_PDB_SC_PDBIE)
00266 
00267 /*! @brief Set the PDBIE field to a new value. */
00268 #define BW_PDB_SC_PDBIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIE), v))
00269 /*@}*/
00270 
00271 /*!
00272  * @name Register PDB_SC, field PDBIF[6] (RW)
00273  *
00274  * This field is set when the counter value is equal to the IDLY register.
00275  * Writing zero clears this field.
00276  */
00277 /*@{*/
00278 #define BP_PDB_SC_PDBIF      (6U)          /*!< Bit position for PDB_SC_PDBIF. */
00279 #define BM_PDB_SC_PDBIF      (0x00000040U) /*!< Bit mask for PDB_SC_PDBIF. */
00280 #define BS_PDB_SC_PDBIF      (1U)          /*!< Bit field size in bits for PDB_SC_PDBIF. */
00281 
00282 /*! @brief Read current value of the PDB_SC_PDBIF field. */
00283 #define BR_PDB_SC_PDBIF(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF)))
00284 
00285 /*! @brief Format value for bitfield PDB_SC_PDBIF. */
00286 #define BF_PDB_SC_PDBIF(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBIF) & BM_PDB_SC_PDBIF)
00287 
00288 /*! @brief Set the PDBIF field to a new value. */
00289 #define BW_PDB_SC_PDBIF(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBIF), v))
00290 /*@}*/
00291 
00292 /*!
00293  * @name Register PDB_SC, field PDBEN[7] (RW)
00294  *
00295  * Values:
00296  * - 0 - PDB disabled. Counter is off.
00297  * - 1 - PDB enabled.
00298  */
00299 /*@{*/
00300 #define BP_PDB_SC_PDBEN      (7U)          /*!< Bit position for PDB_SC_PDBEN. */
00301 #define BM_PDB_SC_PDBEN      (0x00000080U) /*!< Bit mask for PDB_SC_PDBEN. */
00302 #define BS_PDB_SC_PDBEN      (1U)          /*!< Bit field size in bits for PDB_SC_PDBEN. */
00303 
00304 /*! @brief Read current value of the PDB_SC_PDBEN field. */
00305 #define BR_PDB_SC_PDBEN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN)))
00306 
00307 /*! @brief Format value for bitfield PDB_SC_PDBEN. */
00308 #define BF_PDB_SC_PDBEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEN) & BM_PDB_SC_PDBEN)
00309 
00310 /*! @brief Set the PDBEN field to a new value. */
00311 #define BW_PDB_SC_PDBEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEN), v))
00312 /*@}*/
00313 
00314 /*!
00315  * @name Register PDB_SC, field TRGSEL[11:8] (RW)
00316  *
00317  * Selects the trigger input source for the PDB. The trigger input source can be
00318  * internal or external (EXTRG pin), or the software trigger. Refer to chip
00319  * configuration details for the actual PDB input trigger connections.
00320  *
00321  * Values:
00322  * - 0000 - Trigger-In 0 is selected.
00323  * - 0001 - Trigger-In 1 is selected.
00324  * - 0010 - Trigger-In 2 is selected.
00325  * - 0011 - Trigger-In 3 is selected.
00326  * - 0100 - Trigger-In 4 is selected.
00327  * - 0101 - Trigger-In 5 is selected.
00328  * - 0110 - Trigger-In 6 is selected.
00329  * - 0111 - Trigger-In 7 is selected.
00330  * - 1000 - Trigger-In 8 is selected.
00331  * - 1001 - Trigger-In 9 is selected.
00332  * - 1010 - Trigger-In 10 is selected.
00333  * - 1011 - Trigger-In 11 is selected.
00334  * - 1100 - Trigger-In 12 is selected.
00335  * - 1101 - Trigger-In 13 is selected.
00336  * - 1110 - Trigger-In 14 is selected.
00337  * - 1111 - Software trigger is selected.
00338  */
00339 /*@{*/
00340 #define BP_PDB_SC_TRGSEL     (8U)          /*!< Bit position for PDB_SC_TRGSEL. */
00341 #define BM_PDB_SC_TRGSEL     (0x00000F00U) /*!< Bit mask for PDB_SC_TRGSEL. */
00342 #define BS_PDB_SC_TRGSEL     (4U)          /*!< Bit field size in bits for PDB_SC_TRGSEL. */
00343 
00344 /*! @brief Read current value of the PDB_SC_TRGSEL field. */
00345 #define BR_PDB_SC_TRGSEL(x)  (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.TRGSEL))
00346 
00347 /*! @brief Format value for bitfield PDB_SC_TRGSEL. */
00348 #define BF_PDB_SC_TRGSEL(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_TRGSEL) & BM_PDB_SC_TRGSEL)
00349 
00350 /*! @brief Set the TRGSEL field to a new value. */
00351 #define BW_PDB_SC_TRGSEL(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_TRGSEL) | BF_PDB_SC_TRGSEL(v)))
00352 /*@}*/
00353 
00354 /*!
00355  * @name Register PDB_SC, field PRESCALER[14:12] (RW)
00356  *
00357  * Values:
00358  * - 000 - Counting uses the peripheral clock divided by multiplication factor
00359  *     selected by MULT.
00360  * - 001 - Counting uses the peripheral clock divided by twice of the
00361  *     multiplication factor selected by MULT.
00362  * - 010 - Counting uses the peripheral clock divided by four times of the
00363  *     multiplication factor selected by MULT.
00364  * - 011 - Counting uses the peripheral clock divided by eight times of the
00365  *     multiplication factor selected by MULT.
00366  * - 100 - Counting uses the peripheral clock divided by 16 times of the
00367  *     multiplication factor selected by MULT.
00368  * - 101 - Counting uses the peripheral clock divided by 32 times of the
00369  *     multiplication factor selected by MULT.
00370  * - 110 - Counting uses the peripheral clock divided by 64 times of the
00371  *     multiplication factor selected by MULT.
00372  * - 111 - Counting uses the peripheral clock divided by 128 times of the
00373  *     multiplication factor selected by MULT.
00374  */
00375 /*@{*/
00376 #define BP_PDB_SC_PRESCALER  (12U)         /*!< Bit position for PDB_SC_PRESCALER. */
00377 #define BM_PDB_SC_PRESCALER  (0x00007000U) /*!< Bit mask for PDB_SC_PRESCALER. */
00378 #define BS_PDB_SC_PRESCALER  (3U)          /*!< Bit field size in bits for PDB_SC_PRESCALER. */
00379 
00380 /*! @brief Read current value of the PDB_SC_PRESCALER field. */
00381 #define BR_PDB_SC_PRESCALER(x) (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.PRESCALER))
00382 
00383 /*! @brief Format value for bitfield PDB_SC_PRESCALER. */
00384 #define BF_PDB_SC_PRESCALER(v) ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PRESCALER) & BM_PDB_SC_PRESCALER)
00385 
00386 /*! @brief Set the PRESCALER field to a new value. */
00387 #define BW_PDB_SC_PRESCALER(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_PRESCALER) | BF_PDB_SC_PRESCALER(v)))
00388 /*@}*/
00389 
00390 /*!
00391  * @name Register PDB_SC, field DMAEN[15] (RW)
00392  *
00393  * When DMA is enabled, the PDBIF flag generates a DMA request instead of an
00394  * interrupt.
00395  *
00396  * Values:
00397  * - 0 - DMA disabled.
00398  * - 1 - DMA enabled.
00399  */
00400 /*@{*/
00401 #define BP_PDB_SC_DMAEN      (15U)         /*!< Bit position for PDB_SC_DMAEN. */
00402 #define BM_PDB_SC_DMAEN      (0x00008000U) /*!< Bit mask for PDB_SC_DMAEN. */
00403 #define BS_PDB_SC_DMAEN      (1U)          /*!< Bit field size in bits for PDB_SC_DMAEN. */
00404 
00405 /*! @brief Read current value of the PDB_SC_DMAEN field. */
00406 #define BR_PDB_SC_DMAEN(x)   (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN)))
00407 
00408 /*! @brief Format value for bitfield PDB_SC_DMAEN. */
00409 #define BF_PDB_SC_DMAEN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_DMAEN) & BM_PDB_SC_DMAEN)
00410 
00411 /*! @brief Set the DMAEN field to a new value. */
00412 #define BW_PDB_SC_DMAEN(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_DMAEN), v))
00413 /*@}*/
00414 
00415 /*!
00416  * @name Register PDB_SC, field SWTRIG[16] (WORZ)
00417  *
00418  * When PDB is enabled and the software trigger is selected as the trigger input
00419  * source, writing 1 to this field resets and restarts the counter. Writing 0 to
00420  * this field has no effect. Reading this field results 0.
00421  */
00422 /*@{*/
00423 #define BP_PDB_SC_SWTRIG     (16U)         /*!< Bit position for PDB_SC_SWTRIG. */
00424 #define BM_PDB_SC_SWTRIG     (0x00010000U) /*!< Bit mask for PDB_SC_SWTRIG. */
00425 #define BS_PDB_SC_SWTRIG     (1U)          /*!< Bit field size in bits for PDB_SC_SWTRIG. */
00426 
00427 /*! @brief Format value for bitfield PDB_SC_SWTRIG. */
00428 #define BF_PDB_SC_SWTRIG(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_SWTRIG) & BM_PDB_SC_SWTRIG)
00429 
00430 /*! @brief Set the SWTRIG field to a new value. */
00431 #define BW_PDB_SC_SWTRIG(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_SWTRIG), v))
00432 /*@}*/
00433 
00434 /*!
00435  * @name Register PDB_SC, field PDBEIE[17] (RW)
00436  *
00437  * Enables the PDB sequence error interrupt. When this field is set, any of the
00438  * PDB channel sequence error flags generates a PDB sequence error interrupt.
00439  *
00440  * Values:
00441  * - 0 - PDB sequence error interrupt disabled.
00442  * - 1 - PDB sequence error interrupt enabled.
00443  */
00444 /*@{*/
00445 #define BP_PDB_SC_PDBEIE     (17U)         /*!< Bit position for PDB_SC_PDBEIE. */
00446 #define BM_PDB_SC_PDBEIE     (0x00020000U) /*!< Bit mask for PDB_SC_PDBEIE. */
00447 #define BS_PDB_SC_PDBEIE     (1U)          /*!< Bit field size in bits for PDB_SC_PDBEIE. */
00448 
00449 /*! @brief Read current value of the PDB_SC_PDBEIE field. */
00450 #define BR_PDB_SC_PDBEIE(x)  (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE)))
00451 
00452 /*! @brief Format value for bitfield PDB_SC_PDBEIE. */
00453 #define BF_PDB_SC_PDBEIE(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_SC_PDBEIE) & BM_PDB_SC_PDBEIE)
00454 
00455 /*! @brief Set the PDBEIE field to a new value. */
00456 #define BW_PDB_SC_PDBEIE(x, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_SC_ADDR(x), BP_PDB_SC_PDBEIE), v))
00457 /*@}*/
00458 
00459 /*!
00460  * @name Register PDB_SC, field LDMOD[19:18] (RW)
00461  *
00462  * Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers,
00463  * after 1 is written to LDOK.
00464  *
00465  * Values:
00466  * - 00 - The internal registers are loaded with the values from their buffers
00467  *     immediately after 1 is written to LDOK.
00468  * - 01 - The internal registers are loaded with the values from their buffers
00469  *     when the PDB counter reaches the MOD register value after 1 is written to
00470  *     LDOK.
00471  * - 10 - The internal registers are loaded with the values from their buffers
00472  *     when a trigger input event is detected after 1 is written to LDOK.
00473  * - 11 - The internal registers are loaded with the values from their buffers
00474  *     when either the PDB counter reaches the MOD register value or a trigger
00475  *     input event is detected, after 1 is written to LDOK.
00476  */
00477 /*@{*/
00478 #define BP_PDB_SC_LDMOD      (18U)         /*!< Bit position for PDB_SC_LDMOD. */
00479 #define BM_PDB_SC_LDMOD      (0x000C0000U) /*!< Bit mask for PDB_SC_LDMOD. */
00480 #define BS_PDB_SC_LDMOD      (2U)          /*!< Bit field size in bits for PDB_SC_LDMOD. */
00481 
00482 /*! @brief Read current value of the PDB_SC_LDMOD field. */
00483 #define BR_PDB_SC_LDMOD(x)   (UNION_READ(hw_pdb_sc_t, HW_PDB_SC_ADDR(x), U, B.LDMOD))
00484 
00485 /*! @brief Format value for bitfield PDB_SC_LDMOD. */
00486 #define BF_PDB_SC_LDMOD(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_SC_LDMOD) & BM_PDB_SC_LDMOD)
00487 
00488 /*! @brief Set the LDMOD field to a new value. */
00489 #define BW_PDB_SC_LDMOD(x, v) (HW_PDB_SC_WR(x, (HW_PDB_SC_RD(x) & ~BM_PDB_SC_LDMOD) | BF_PDB_SC_LDMOD(v)))
00490 /*@}*/
00491 
00492 /*******************************************************************************
00493  * HW_PDB_MOD - Modulus register
00494  ******************************************************************************/
00495 
00496 /*!
00497  * @brief HW_PDB_MOD - Modulus register (RW)
00498  *
00499  * Reset value: 0x0000FFFFU
00500  */
00501 typedef union _hw_pdb_mod
00502 {
00503     uint32_t U;
00504     struct _hw_pdb_mod_bitfields
00505     {
00506         uint32_t MOD : 16;             /*!< [15:0] PDB Modulus */
00507         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00508     } B;
00509 } hw_pdb_mod_t;
00510 
00511 /*!
00512  * @name Constants and macros for entire PDB_MOD register
00513  */
00514 /*@{*/
00515 #define HW_PDB_MOD_ADDR(x)       ((x) + 0x4U)
00516 
00517 #define HW_PDB_MOD(x)            (*(__IO hw_pdb_mod_t *) HW_PDB_MOD_ADDR(x))
00518 #define HW_PDB_MOD_RD(x)         (ADDRESS_READ(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x)))
00519 #define HW_PDB_MOD_WR(x, v)      (ADDRESS_WRITE(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x), v))
00520 #define HW_PDB_MOD_SET(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) |  (v)))
00521 #define HW_PDB_MOD_CLR(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) & ~(v)))
00522 #define HW_PDB_MOD_TOG(x, v)     (HW_PDB_MOD_WR(x, HW_PDB_MOD_RD(x) ^  (v)))
00523 /*@}*/
00524 
00525 /*
00526  * Constants & macros for individual PDB_MOD bitfields
00527  */
00528 
00529 /*!
00530  * @name Register PDB_MOD, field MOD[15:0] (RW)
00531  *
00532  * Specifies the period of the counter. When the counter reaches this value, it
00533  * will be reset back to zero. If the PDB is in Continuous mode, the count begins
00534  * anew. Reading this field returns the value of the internal register that is
00535  * effective for the current cycle of PDB.
00536  */
00537 /*@{*/
00538 #define BP_PDB_MOD_MOD       (0U)          /*!< Bit position for PDB_MOD_MOD. */
00539 #define BM_PDB_MOD_MOD       (0x0000FFFFU) /*!< Bit mask for PDB_MOD_MOD. */
00540 #define BS_PDB_MOD_MOD       (16U)         /*!< Bit field size in bits for PDB_MOD_MOD. */
00541 
00542 /*! @brief Read current value of the PDB_MOD_MOD field. */
00543 #define BR_PDB_MOD_MOD(x)    (UNION_READ(hw_pdb_mod_t, HW_PDB_MOD_ADDR(x), U, B.MOD))
00544 
00545 /*! @brief Format value for bitfield PDB_MOD_MOD. */
00546 #define BF_PDB_MOD_MOD(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_MOD_MOD) & BM_PDB_MOD_MOD)
00547 
00548 /*! @brief Set the MOD field to a new value. */
00549 #define BW_PDB_MOD_MOD(x, v) (HW_PDB_MOD_WR(x, (HW_PDB_MOD_RD(x) & ~BM_PDB_MOD_MOD) | BF_PDB_MOD_MOD(v)))
00550 /*@}*/
00551 
00552 /*******************************************************************************
00553  * HW_PDB_CNT - Counter register
00554  ******************************************************************************/
00555 
00556 /*!
00557  * @brief HW_PDB_CNT - Counter register (RO)
00558  *
00559  * Reset value: 0x00000000U
00560  */
00561 typedef union _hw_pdb_cnt
00562 {
00563     uint32_t U;
00564     struct _hw_pdb_cnt_bitfields
00565     {
00566         uint32_t CNT : 16;             /*!< [15:0] PDB Counter */
00567         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00568     } B;
00569 } hw_pdb_cnt_t;
00570 
00571 /*!
00572  * @name Constants and macros for entire PDB_CNT register
00573  */
00574 /*@{*/
00575 #define HW_PDB_CNT_ADDR(x)       ((x) + 0x8U)
00576 
00577 #define HW_PDB_CNT(x)            (*(__I hw_pdb_cnt_t *) HW_PDB_CNT_ADDR(x))
00578 #define HW_PDB_CNT_RD(x)         (ADDRESS_READ(hw_pdb_cnt_t, HW_PDB_CNT_ADDR(x)))
00579 /*@}*/
00580 
00581 /*
00582  * Constants & macros for individual PDB_CNT bitfields
00583  */
00584 
00585 /*!
00586  * @name Register PDB_CNT, field CNT[15:0] (RO)
00587  *
00588  * Contains the current value of the counter.
00589  */
00590 /*@{*/
00591 #define BP_PDB_CNT_CNT       (0U)          /*!< Bit position for PDB_CNT_CNT. */
00592 #define BM_PDB_CNT_CNT       (0x0000FFFFU) /*!< Bit mask for PDB_CNT_CNT. */
00593 #define BS_PDB_CNT_CNT       (16U)         /*!< Bit field size in bits for PDB_CNT_CNT. */
00594 
00595 /*! @brief Read current value of the PDB_CNT_CNT field. */
00596 #define BR_PDB_CNT_CNT(x)    (UNION_READ(hw_pdb_cnt_t, HW_PDB_CNT_ADDR(x), U, B.CNT))
00597 /*@}*/
00598 
00599 /*******************************************************************************
00600  * HW_PDB_IDLY - Interrupt Delay register
00601  ******************************************************************************/
00602 
00603 /*!
00604  * @brief HW_PDB_IDLY - Interrupt Delay register (RW)
00605  *
00606  * Reset value: 0x0000FFFFU
00607  */
00608 typedef union _hw_pdb_idly
00609 {
00610     uint32_t U;
00611     struct _hw_pdb_idly_bitfields
00612     {
00613         uint32_t IDLY : 16;            /*!< [15:0] PDB Interrupt Delay */
00614         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00615     } B;
00616 } hw_pdb_idly_t;
00617 
00618 /*!
00619  * @name Constants and macros for entire PDB_IDLY register
00620  */
00621 /*@{*/
00622 #define HW_PDB_IDLY_ADDR(x)      ((x) + 0xCU)
00623 
00624 #define HW_PDB_IDLY(x)           (*(__IO hw_pdb_idly_t *) HW_PDB_IDLY_ADDR(x))
00625 #define HW_PDB_IDLY_RD(x)        (ADDRESS_READ(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x)))
00626 #define HW_PDB_IDLY_WR(x, v)     (ADDRESS_WRITE(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x), v))
00627 #define HW_PDB_IDLY_SET(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) |  (v)))
00628 #define HW_PDB_IDLY_CLR(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) & ~(v)))
00629 #define HW_PDB_IDLY_TOG(x, v)    (HW_PDB_IDLY_WR(x, HW_PDB_IDLY_RD(x) ^  (v)))
00630 /*@}*/
00631 
00632 /*
00633  * Constants & macros for individual PDB_IDLY bitfields
00634  */
00635 
00636 /*!
00637  * @name Register PDB_IDLY, field IDLY[15:0] (RW)
00638  *
00639  * Specifies the delay value to schedule the PDB interrupt. It can be used to
00640  * schedule an independent interrupt at some point in the PDB cycle. If enabled, a
00641  * PDB interrupt is generated, when the counter is equal to the IDLY. Reading
00642  * this field returns the value of internal register that is effective for the
00643  * current cycle of the PDB.
00644  */
00645 /*@{*/
00646 #define BP_PDB_IDLY_IDLY     (0U)          /*!< Bit position for PDB_IDLY_IDLY. */
00647 #define BM_PDB_IDLY_IDLY     (0x0000FFFFU) /*!< Bit mask for PDB_IDLY_IDLY. */
00648 #define BS_PDB_IDLY_IDLY     (16U)         /*!< Bit field size in bits for PDB_IDLY_IDLY. */
00649 
00650 /*! @brief Read current value of the PDB_IDLY_IDLY field. */
00651 #define BR_PDB_IDLY_IDLY(x)  (UNION_READ(hw_pdb_idly_t, HW_PDB_IDLY_ADDR(x), U, B.IDLY))
00652 
00653 /*! @brief Format value for bitfield PDB_IDLY_IDLY. */
00654 #define BF_PDB_IDLY_IDLY(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_IDLY_IDLY) & BM_PDB_IDLY_IDLY)
00655 
00656 /*! @brief Set the IDLY field to a new value. */
00657 #define BW_PDB_IDLY_IDLY(x, v) (HW_PDB_IDLY_WR(x, (HW_PDB_IDLY_RD(x) & ~BM_PDB_IDLY_IDLY) | BF_PDB_IDLY_IDLY(v)))
00658 /*@}*/
00659 
00660 /*******************************************************************************
00661  * HW_PDB_CHnC1 - Channel n Control register 1
00662  ******************************************************************************/
00663 
00664 /*!
00665  * @brief HW_PDB_CHnC1 - Channel n Control register 1 (RW)
00666  *
00667  * Reset value: 0x00000000U
00668  *
00669  * Each PDB channel has one control register, CHnC1. The bits in this register
00670  * control the functionality of each PDB channel operation.
00671  */
00672 typedef union _hw_pdb_chnc1
00673 {
00674     uint32_t U;
00675     struct _hw_pdb_chnc1_bitfields
00676     {
00677         uint32_t EN : 8;               /*!< [7:0] PDB Channel Pre-Trigger Enable */
00678         uint32_t TOS : 8;              /*!< [15:8] PDB Channel Pre-Trigger Output Select */
00679         uint32_t BB : 8;               /*!< [23:16] PDB Channel Pre-Trigger Back-to-Back
00680                                         * Operation Enable */
00681         uint32_t RESERVED0 : 8;        /*!< [31:24]  */
00682     } B;
00683 } hw_pdb_chnc1_t;
00684 
00685 /*!
00686  * @name Constants and macros for entire PDB_CHnC1 register
00687  */
00688 /*@{*/
00689 #define HW_PDB_CHnC1_COUNT (2U)
00690 
00691 #define HW_PDB_CHnC1_ADDR(x, n)  ((x) + 0x10U + (0x28U * (n)))
00692 
00693 #define HW_PDB_CHnC1(x, n)       (*(__IO hw_pdb_chnc1_t *) HW_PDB_CHnC1_ADDR(x, n))
00694 #define HW_PDB_CHnC1_RD(x, n)    (ADDRESS_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n)))
00695 #define HW_PDB_CHnC1_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), v))
00696 #define HW_PDB_CHnC1_SET(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) |  (v)))
00697 #define HW_PDB_CHnC1_CLR(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) & ~(v)))
00698 #define HW_PDB_CHnC1_TOG(x, n, v) (HW_PDB_CHnC1_WR(x, n, HW_PDB_CHnC1_RD(x, n) ^  (v)))
00699 /*@}*/
00700 
00701 /*
00702  * Constants & macros for individual PDB_CHnC1 bitfields
00703  */
00704 
00705 /*!
00706  * @name Register PDB_CHnC1, field EN[7:0] (RW)
00707  *
00708  * These bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger
00709  * bits are implemented in this MCU.
00710  *
00711  * Values:
00712  * - 0 - PDB channel's corresponding pre-trigger disabled.
00713  * - 1 - PDB channel's corresponding pre-trigger enabled.
00714  */
00715 /*@{*/
00716 #define BP_PDB_CHnC1_EN      (0U)          /*!< Bit position for PDB_CHnC1_EN. */
00717 #define BM_PDB_CHnC1_EN      (0x000000FFU) /*!< Bit mask for PDB_CHnC1_EN. */
00718 #define BS_PDB_CHnC1_EN      (8U)          /*!< Bit field size in bits for PDB_CHnC1_EN. */
00719 
00720 /*! @brief Read current value of the PDB_CHnC1_EN field. */
00721 #define BR_PDB_CHnC1_EN(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.EN))
00722 
00723 /*! @brief Format value for bitfield PDB_CHnC1_EN. */
00724 #define BF_PDB_CHnC1_EN(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_EN) & BM_PDB_CHnC1_EN)
00725 
00726 /*! @brief Set the EN field to a new value. */
00727 #define BW_PDB_CHnC1_EN(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_EN) | BF_PDB_CHnC1_EN(v)))
00728 /*@}*/
00729 
00730 /*!
00731  * @name Register PDB_CHnC1, field TOS[15:8] (RW)
00732  *
00733  * Selects the PDB ADC pre-trigger outputs. Only lower M pre-trigger fields are
00734  * implemented in this MCU.
00735  *
00736  * Values:
00737  * - 0 - PDB channel's corresponding pre-trigger is in bypassed mode. The
00738  *     pre-trigger asserts one peripheral clock cycle after a rising edge is detected
00739  *     on selected trigger input source or software trigger is selected and SWTRIG
00740  *     is written with 1.
00741  * - 1 - PDB channel's corresponding pre-trigger asserts when the counter
00742  *     reaches the channel delay register and one peripheral clock cycle after a rising
00743  *     edge is detected on selected trigger input source or software trigger is
00744  *     selected and SETRIG is written with 1.
00745  */
00746 /*@{*/
00747 #define BP_PDB_CHnC1_TOS     (8U)          /*!< Bit position for PDB_CHnC1_TOS. */
00748 #define BM_PDB_CHnC1_TOS     (0x0000FF00U) /*!< Bit mask for PDB_CHnC1_TOS. */
00749 #define BS_PDB_CHnC1_TOS     (8U)          /*!< Bit field size in bits for PDB_CHnC1_TOS. */
00750 
00751 /*! @brief Read current value of the PDB_CHnC1_TOS field. */
00752 #define BR_PDB_CHnC1_TOS(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.TOS))
00753 
00754 /*! @brief Format value for bitfield PDB_CHnC1_TOS. */
00755 #define BF_PDB_CHnC1_TOS(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_TOS) & BM_PDB_CHnC1_TOS)
00756 
00757 /*! @brief Set the TOS field to a new value. */
00758 #define BW_PDB_CHnC1_TOS(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_TOS) | BF_PDB_CHnC1_TOS(v)))
00759 /*@}*/
00760 
00761 /*!
00762  * @name Register PDB_CHnC1, field BB[23:16] (RW)
00763  *
00764  * These bits enable the PDB ADC pre-trigger operation as back-to-back mode.
00765  * Only lower M pre-trigger bits are implemented in this MCU. Back-to-back operation
00766  * enables the ADC conversions complete to trigger the next PDB channel
00767  * pre-trigger and trigger output, so that the ADC conversions can be triggered on next
00768  * set of configuration and results registers. Application code must only enable
00769  * the back-to-back operation of the PDB pre-triggers at the leading of the
00770  * back-to-back connection chain.
00771  *
00772  * Values:
00773  * - 0 - PDB channel's corresponding pre-trigger back-to-back operation disabled.
00774  * - 1 - PDB channel's corresponding pre-trigger back-to-back operation enabled.
00775  */
00776 /*@{*/
00777 #define BP_PDB_CHnC1_BB      (16U)         /*!< Bit position for PDB_CHnC1_BB. */
00778 #define BM_PDB_CHnC1_BB      (0x00FF0000U) /*!< Bit mask for PDB_CHnC1_BB. */
00779 #define BS_PDB_CHnC1_BB      (8U)          /*!< Bit field size in bits for PDB_CHnC1_BB. */
00780 
00781 /*! @brief Read current value of the PDB_CHnC1_BB field. */
00782 #define BR_PDB_CHnC1_BB(x, n) (UNION_READ(hw_pdb_chnc1_t, HW_PDB_CHnC1_ADDR(x, n), U, B.BB))
00783 
00784 /*! @brief Format value for bitfield PDB_CHnC1_BB. */
00785 #define BF_PDB_CHnC1_BB(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnC1_BB) & BM_PDB_CHnC1_BB)
00786 
00787 /*! @brief Set the BB field to a new value. */
00788 #define BW_PDB_CHnC1_BB(x, n, v) (HW_PDB_CHnC1_WR(x, n, (HW_PDB_CHnC1_RD(x, n) & ~BM_PDB_CHnC1_BB) | BF_PDB_CHnC1_BB(v)))
00789 /*@}*/
00790 /*******************************************************************************
00791  * HW_PDB_CHnS - Channel n Status register
00792  ******************************************************************************/
00793 
00794 /*!
00795  * @brief HW_PDB_CHnS - Channel n Status register (RW)
00796  *
00797  * Reset value: 0x00000000U
00798  */
00799 typedef union _hw_pdb_chns
00800 {
00801     uint32_t U;
00802     struct _hw_pdb_chns_bitfields
00803     {
00804         uint32_t ERR : 8;              /*!< [7:0] PDB Channel Sequence Error Flags */
00805         uint32_t RESERVED0 : 8;        /*!< [15:8]  */
00806         uint32_t CF : 8;               /*!< [23:16] PDB Channel Flags */
00807         uint32_t RESERVED1 : 8;        /*!< [31:24]  */
00808     } B;
00809 } hw_pdb_chns_t;
00810 
00811 /*!
00812  * @name Constants and macros for entire PDB_CHnS register
00813  */
00814 /*@{*/
00815 #define HW_PDB_CHnS_COUNT (2U)
00816 
00817 #define HW_PDB_CHnS_ADDR(x, n)   ((x) + 0x14U + (0x28U * (n)))
00818 
00819 #define HW_PDB_CHnS(x, n)        (*(__IO hw_pdb_chns_t *) HW_PDB_CHnS_ADDR(x, n))
00820 #define HW_PDB_CHnS_RD(x, n)     (ADDRESS_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n)))
00821 #define HW_PDB_CHnS_WR(x, n, v)  (ADDRESS_WRITE(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), v))
00822 #define HW_PDB_CHnS_SET(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) |  (v)))
00823 #define HW_PDB_CHnS_CLR(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) & ~(v)))
00824 #define HW_PDB_CHnS_TOG(x, n, v) (HW_PDB_CHnS_WR(x, n, HW_PDB_CHnS_RD(x, n) ^  (v)))
00825 /*@}*/
00826 
00827 /*
00828  * Constants & macros for individual PDB_CHnS bitfields
00829  */
00830 
00831 /*!
00832  * @name Register PDB_CHnS, field ERR[7:0] (RW)
00833  *
00834  * Only the lower M bits are implemented in this MCU.
00835  *
00836  * Values:
00837  * - 0 - Sequence error not detected on PDB channel's corresponding pre-trigger.
00838  * - 1 - Sequence error detected on PDB channel's corresponding pre-trigger.
00839  *     ADCn block can be triggered for a conversion by one pre-trigger from PDB
00840  *     channel n. When one conversion, which is triggered by one of the pre-triggers
00841  *     from PDB channel n, is in progress, new trigger from PDB channel's
00842  *     corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set.
00843  *     Writing 0's to clear the sequence error flags.
00844  */
00845 /*@{*/
00846 #define BP_PDB_CHnS_ERR      (0U)          /*!< Bit position for PDB_CHnS_ERR. */
00847 #define BM_PDB_CHnS_ERR      (0x000000FFU) /*!< Bit mask for PDB_CHnS_ERR. */
00848 #define BS_PDB_CHnS_ERR      (8U)          /*!< Bit field size in bits for PDB_CHnS_ERR. */
00849 
00850 /*! @brief Read current value of the PDB_CHnS_ERR field. */
00851 #define BR_PDB_CHnS_ERR(x, n) (UNION_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), U, B.ERR))
00852 
00853 /*! @brief Format value for bitfield PDB_CHnS_ERR. */
00854 #define BF_PDB_CHnS_ERR(v)   ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_ERR) & BM_PDB_CHnS_ERR)
00855 
00856 /*! @brief Set the ERR field to a new value. */
00857 #define BW_PDB_CHnS_ERR(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_ERR) | BF_PDB_CHnS_ERR(v)))
00858 /*@}*/
00859 
00860 /*!
00861  * @name Register PDB_CHnS, field CF[23:16] (RW)
00862  *
00863  * The CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to
00864  * clear these bits.
00865  */
00866 /*@{*/
00867 #define BP_PDB_CHnS_CF       (16U)         /*!< Bit position for PDB_CHnS_CF. */
00868 #define BM_PDB_CHnS_CF       (0x00FF0000U) /*!< Bit mask for PDB_CHnS_CF. */
00869 #define BS_PDB_CHnS_CF       (8U)          /*!< Bit field size in bits for PDB_CHnS_CF. */
00870 
00871 /*! @brief Read current value of the PDB_CHnS_CF field. */
00872 #define BR_PDB_CHnS_CF(x, n) (UNION_READ(hw_pdb_chns_t, HW_PDB_CHnS_ADDR(x, n), U, B.CF))
00873 
00874 /*! @brief Format value for bitfield PDB_CHnS_CF. */
00875 #define BF_PDB_CHnS_CF(v)    ((uint32_t)((uint32_t)(v) << BP_PDB_CHnS_CF) & BM_PDB_CHnS_CF)
00876 
00877 /*! @brief Set the CF field to a new value. */
00878 #define BW_PDB_CHnS_CF(x, n, v) (HW_PDB_CHnS_WR(x, n, (HW_PDB_CHnS_RD(x, n) & ~BM_PDB_CHnS_CF) | BF_PDB_CHnS_CF(v)))
00879 /*@}*/
00880 /*******************************************************************************
00881  * HW_PDB_CHnDLY0 - Channel n Delay 0 register
00882  ******************************************************************************/
00883 
00884 /*!
00885  * @brief HW_PDB_CHnDLY0 - Channel n Delay 0 register (RW)
00886  *
00887  * Reset value: 0x00000000U
00888  */
00889 typedef union _hw_pdb_chndly0
00890 {
00891     uint32_t U;
00892     struct _hw_pdb_chndly0_bitfields
00893     {
00894         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
00895         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00896     } B;
00897 } hw_pdb_chndly0_t;
00898 
00899 /*!
00900  * @name Constants and macros for entire PDB_CHnDLY0 register
00901  */
00902 /*@{*/
00903 #define HW_PDB_CHnDLY0_COUNT (2U)
00904 
00905 #define HW_PDB_CHnDLY0_ADDR(x, n) ((x) + 0x18U + (0x28U * (n)))
00906 
00907 #define HW_PDB_CHnDLY0(x, n)     (*(__IO hw_pdb_chndly0_t *) HW_PDB_CHnDLY0_ADDR(x, n))
00908 #define HW_PDB_CHnDLY0_RD(x, n)  (ADDRESS_READ(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n)))
00909 #define HW_PDB_CHnDLY0_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n), v))
00910 #define HW_PDB_CHnDLY0_SET(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) |  (v)))
00911 #define HW_PDB_CHnDLY0_CLR(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) & ~(v)))
00912 #define HW_PDB_CHnDLY0_TOG(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, HW_PDB_CHnDLY0_RD(x, n) ^  (v)))
00913 /*@}*/
00914 
00915 /*
00916  * Constants & macros for individual PDB_CHnDLY0 bitfields
00917  */
00918 
00919 /*!
00920  * @name Register PDB_CHnDLY0, field DLY[15:0] (RW)
00921  *
00922  * Specifies the delay value for the channel's corresponding pre-trigger. The
00923  * pre-trigger asserts when the counter is equal to DLY. Reading this field returns
00924  * the value of internal register that is effective for the current PDB cycle.
00925  */
00926 /*@{*/
00927 #define BP_PDB_CHnDLY0_DLY   (0U)          /*!< Bit position for PDB_CHnDLY0_DLY. */
00928 #define BM_PDB_CHnDLY0_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY0_DLY. */
00929 #define BS_PDB_CHnDLY0_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY0_DLY. */
00930 
00931 /*! @brief Read current value of the PDB_CHnDLY0_DLY field. */
00932 #define BR_PDB_CHnDLY0_DLY(x, n) (UNION_READ(hw_pdb_chndly0_t, HW_PDB_CHnDLY0_ADDR(x, n), U, B.DLY))
00933 
00934 /*! @brief Format value for bitfield PDB_CHnDLY0_DLY. */
00935 #define BF_PDB_CHnDLY0_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY0_DLY) & BM_PDB_CHnDLY0_DLY)
00936 
00937 /*! @brief Set the DLY field to a new value. */
00938 #define BW_PDB_CHnDLY0_DLY(x, n, v) (HW_PDB_CHnDLY0_WR(x, n, (HW_PDB_CHnDLY0_RD(x, n) & ~BM_PDB_CHnDLY0_DLY) | BF_PDB_CHnDLY0_DLY(v)))
00939 /*@}*/
00940 /*******************************************************************************
00941  * HW_PDB_CHnDLY1 - Channel n Delay 1 register
00942  ******************************************************************************/
00943 
00944 /*!
00945  * @brief HW_PDB_CHnDLY1 - Channel n Delay 1 register (RW)
00946  *
00947  * Reset value: 0x00000000U
00948  */
00949 typedef union _hw_pdb_chndly1
00950 {
00951     uint32_t U;
00952     struct _hw_pdb_chndly1_bitfields
00953     {
00954         uint32_t DLY : 16;             /*!< [15:0] PDB Channel Delay */
00955         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
00956     } B;
00957 } hw_pdb_chndly1_t;
00958 
00959 /*!
00960  * @name Constants and macros for entire PDB_CHnDLY1 register
00961  */
00962 /*@{*/
00963 #define HW_PDB_CHnDLY1_COUNT (2U)
00964 
00965 #define HW_PDB_CHnDLY1_ADDR(x, n) ((x) + 0x1CU + (0x28U * (n)))
00966 
00967 #define HW_PDB_CHnDLY1(x, n)     (*(__IO hw_pdb_chndly1_t *) HW_PDB_CHnDLY1_ADDR(x, n))
00968 #define HW_PDB_CHnDLY1_RD(x, n)  (ADDRESS_READ(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n)))
00969 #define HW_PDB_CHnDLY1_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n), v))
00970 #define HW_PDB_CHnDLY1_SET(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) |  (v)))
00971 #define HW_PDB_CHnDLY1_CLR(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) & ~(v)))
00972 #define HW_PDB_CHnDLY1_TOG(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, HW_PDB_CHnDLY1_RD(x, n) ^  (v)))
00973 /*@}*/
00974 
00975 /*
00976  * Constants & macros for individual PDB_CHnDLY1 bitfields
00977  */
00978 
00979 /*!
00980  * @name Register PDB_CHnDLY1, field DLY[15:0] (RW)
00981  *
00982  * These bits specify the delay value for the channel's corresponding
00983  * pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading these
00984  * bits returns the value of internal register that is effective for the current PDB
00985  * cycle.
00986  */
00987 /*@{*/
00988 #define BP_PDB_CHnDLY1_DLY   (0U)          /*!< Bit position for PDB_CHnDLY1_DLY. */
00989 #define BM_PDB_CHnDLY1_DLY   (0x0000FFFFU) /*!< Bit mask for PDB_CHnDLY1_DLY. */
00990 #define BS_PDB_CHnDLY1_DLY   (16U)         /*!< Bit field size in bits for PDB_CHnDLY1_DLY. */
00991 
00992 /*! @brief Read current value of the PDB_CHnDLY1_DLY field. */
00993 #define BR_PDB_CHnDLY1_DLY(x, n) (UNION_READ(hw_pdb_chndly1_t, HW_PDB_CHnDLY1_ADDR(x, n), U, B.DLY))
00994 
00995 /*! @brief Format value for bitfield PDB_CHnDLY1_DLY. */
00996 #define BF_PDB_CHnDLY1_DLY(v) ((uint32_t)((uint32_t)(v) << BP_PDB_CHnDLY1_DLY) & BM_PDB_CHnDLY1_DLY)
00997 
00998 /*! @brief Set the DLY field to a new value. */
00999 #define BW_PDB_CHnDLY1_DLY(x, n, v) (HW_PDB_CHnDLY1_WR(x, n, (HW_PDB_CHnDLY1_RD(x, n) & ~BM_PDB_CHnDLY1_DLY) | BF_PDB_CHnDLY1_DLY(v)))
01000 /*@}*/
01001 
01002 /*******************************************************************************
01003  * HW_PDB_DACINTCn - DAC Interval Trigger n Control register
01004  ******************************************************************************/
01005 
01006 /*!
01007  * @brief HW_PDB_DACINTCn - DAC Interval Trigger n Control register (RW)
01008  *
01009  * Reset value: 0x00000000U
01010  */
01011 typedef union _hw_pdb_dacintcn
01012 {
01013     uint32_t U;
01014     struct _hw_pdb_dacintcn_bitfields
01015     {
01016         uint32_t TOE : 1;              /*!< [0] DAC Interval Trigger Enable */
01017         uint32_t EXT : 1;              /*!< [1] DAC External Trigger Input Enable */
01018         uint32_t RESERVED0 : 30;       /*!< [31:2]  */
01019     } B;
01020 } hw_pdb_dacintcn_t;
01021 
01022 /*!
01023  * @name Constants and macros for entire PDB_DACINTCn register
01024  */
01025 /*@{*/
01026 #define HW_PDB_DACINTCn_COUNT (2U)
01027 
01028 #define HW_PDB_DACINTCn_ADDR(x, n) ((x) + 0x150U + (0x8U * (n)))
01029 
01030 #define HW_PDB_DACINTCn(x, n)    (*(__IO hw_pdb_dacintcn_t *) HW_PDB_DACINTCn_ADDR(x, n))
01031 #define HW_PDB_DACINTCn_RD(x, n) (ADDRESS_READ(hw_pdb_dacintcn_t, HW_PDB_DACINTCn_ADDR(x, n)))
01032 #define HW_PDB_DACINTCn_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_dacintcn_t, HW_PDB_DACINTCn_ADDR(x, n), v))
01033 #define HW_PDB_DACINTCn_SET(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) |  (v)))
01034 #define HW_PDB_DACINTCn_CLR(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) & ~(v)))
01035 #define HW_PDB_DACINTCn_TOG(x, n, v) (HW_PDB_DACINTCn_WR(x, n, HW_PDB_DACINTCn_RD(x, n) ^  (v)))
01036 /*@}*/
01037 
01038 /*
01039  * Constants & macros for individual PDB_DACINTCn bitfields
01040  */
01041 
01042 /*!
01043  * @name Register PDB_DACINTCn, field TOE[0] (RW)
01044  *
01045  * This bit enables the DAC interval trigger.
01046  *
01047  * Values:
01048  * - 0 - DAC interval trigger disabled.
01049  * - 1 - DAC interval trigger enabled.
01050  */
01051 /*@{*/
01052 #define BP_PDB_DACINTCn_TOE  (0U)          /*!< Bit position for PDB_DACINTCn_TOE. */
01053 #define BM_PDB_DACINTCn_TOE  (0x00000001U) /*!< Bit mask for PDB_DACINTCn_TOE. */
01054 #define BS_PDB_DACINTCn_TOE  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_TOE. */
01055 
01056 /*! @brief Read current value of the PDB_DACINTCn_TOE field. */
01057 #define BR_PDB_DACINTCn_TOE(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE)))
01058 
01059 /*! @brief Format value for bitfield PDB_DACINTCn_TOE. */
01060 #define BF_PDB_DACINTCn_TOE(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_TOE) & BM_PDB_DACINTCn_TOE)
01061 
01062 /*! @brief Set the TOE field to a new value. */
01063 #define BW_PDB_DACINTCn_TOE(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_TOE), v))
01064 /*@}*/
01065 
01066 /*!
01067  * @name Register PDB_DACINTCn, field EXT[1] (RW)
01068  *
01069  * Enables the external trigger for DAC interval counter.
01070  *
01071  * Values:
01072  * - 0 - DAC external trigger input disabled. DAC interval counter is reset and
01073  *     counting starts when a rising edge is detected on selected trigger input
01074  *     source or software trigger is selected and SWTRIG is written with 1.
01075  * - 1 - DAC external trigger input enabled. DAC interval counter is bypassed
01076  *     and DAC external trigger input triggers the DAC interval trigger.
01077  */
01078 /*@{*/
01079 #define BP_PDB_DACINTCn_EXT  (1U)          /*!< Bit position for PDB_DACINTCn_EXT. */
01080 #define BM_PDB_DACINTCn_EXT  (0x00000002U) /*!< Bit mask for PDB_DACINTCn_EXT. */
01081 #define BS_PDB_DACINTCn_EXT  (1U)          /*!< Bit field size in bits for PDB_DACINTCn_EXT. */
01082 
01083 /*! @brief Read current value of the PDB_DACINTCn_EXT field. */
01084 #define BR_PDB_DACINTCn_EXT(x, n) (ADDRESS_READ(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT)))
01085 
01086 /*! @brief Format value for bitfield PDB_DACINTCn_EXT. */
01087 #define BF_PDB_DACINTCn_EXT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTCn_EXT) & BM_PDB_DACINTCn_EXT)
01088 
01089 /*! @brief Set the EXT field to a new value. */
01090 #define BW_PDB_DACINTCn_EXT(x, n, v) (ADDRESS_WRITE(uint32_t, BITBAND_ADDRESS32(HW_PDB_DACINTCn_ADDR(x, n), BP_PDB_DACINTCn_EXT), v))
01091 /*@}*/
01092 /*******************************************************************************
01093  * HW_PDB_DACINTn - DAC Interval n register
01094  ******************************************************************************/
01095 
01096 /*!
01097  * @brief HW_PDB_DACINTn - DAC Interval n register (RW)
01098  *
01099  * Reset value: 0x00000000U
01100  */
01101 typedef union _hw_pdb_dacintn
01102 {
01103     uint32_t U;
01104     struct _hw_pdb_dacintn_bitfields
01105     {
01106         uint32_t INT : 16;             /*!< [15:0] DAC Interval */
01107         uint32_t RESERVED0 : 16;       /*!< [31:16]  */
01108     } B;
01109 } hw_pdb_dacintn_t;
01110 
01111 /*!
01112  * @name Constants and macros for entire PDB_DACINTn register
01113  */
01114 /*@{*/
01115 #define HW_PDB_DACINTn_COUNT (2U)
01116 
01117 #define HW_PDB_DACINTn_ADDR(x, n) ((x) + 0x154U + (0x8U * (n)))
01118 
01119 #define HW_PDB_DACINTn(x, n)     (*(__IO hw_pdb_dacintn_t *) HW_PDB_DACINTn_ADDR(x, n))
01120 #define HW_PDB_DACINTn_RD(x, n)  (ADDRESS_READ(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n)))
01121 #define HW_PDB_DACINTn_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n), v))
01122 #define HW_PDB_DACINTn_SET(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) |  (v)))
01123 #define HW_PDB_DACINTn_CLR(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) & ~(v)))
01124 #define HW_PDB_DACINTn_TOG(x, n, v) (HW_PDB_DACINTn_WR(x, n, HW_PDB_DACINTn_RD(x, n) ^  (v)))
01125 /*@}*/
01126 
01127 /*
01128  * Constants & macros for individual PDB_DACINTn bitfields
01129  */
01130 
01131 /*!
01132  * @name Register PDB_DACINTn, field INT[15:0] (RW)
01133  *
01134  * Specifies the interval value for DAC interval trigger. DAC interval trigger
01135  * triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT.
01136  * Reading this field returns the value of internal register that is effective
01137  * for the current PDB cycle.
01138  */
01139 /*@{*/
01140 #define BP_PDB_DACINTn_INT   (0U)          /*!< Bit position for PDB_DACINTn_INT. */
01141 #define BM_PDB_DACINTn_INT   (0x0000FFFFU) /*!< Bit mask for PDB_DACINTn_INT. */
01142 #define BS_PDB_DACINTn_INT   (16U)         /*!< Bit field size in bits for PDB_DACINTn_INT. */
01143 
01144 /*! @brief Read current value of the PDB_DACINTn_INT field. */
01145 #define BR_PDB_DACINTn_INT(x, n) (UNION_READ(hw_pdb_dacintn_t, HW_PDB_DACINTn_ADDR(x, n), U, B.INT))
01146 
01147 /*! @brief Format value for bitfield PDB_DACINTn_INT. */
01148 #define BF_PDB_DACINTn_INT(v) ((uint32_t)((uint32_t)(v) << BP_PDB_DACINTn_INT) & BM_PDB_DACINTn_INT)
01149 
01150 /*! @brief Set the INT field to a new value. */
01151 #define BW_PDB_DACINTn_INT(x, n, v) (HW_PDB_DACINTn_WR(x, n, (HW_PDB_DACINTn_RD(x, n) & ~BM_PDB_DACINTn_INT) | BF_PDB_DACINTn_INT(v)))
01152 /*@}*/
01153 
01154 /*******************************************************************************
01155  * HW_PDB_POEN - Pulse-Out n Enable register
01156  ******************************************************************************/
01157 
01158 /*!
01159  * @brief HW_PDB_POEN - Pulse-Out n Enable register (RW)
01160  *
01161  * Reset value: 0x00000000U
01162  */
01163 typedef union _hw_pdb_poen
01164 {
01165     uint32_t U;
01166     struct _hw_pdb_poen_bitfields
01167     {
01168         uint32_t POEN : 8;             /*!< [7:0] PDB Pulse-Out Enable */
01169         uint32_t RESERVED0 : 24;       /*!< [31:8]  */
01170     } B;
01171 } hw_pdb_poen_t;
01172 
01173 /*!
01174  * @name Constants and macros for entire PDB_POEN register
01175  */
01176 /*@{*/
01177 #define HW_PDB_POEN_ADDR(x)      ((x) + 0x190U)
01178 
01179 #define HW_PDB_POEN(x)           (*(__IO hw_pdb_poen_t *) HW_PDB_POEN_ADDR(x))
01180 #define HW_PDB_POEN_RD(x)        (ADDRESS_READ(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x)))
01181 #define HW_PDB_POEN_WR(x, v)     (ADDRESS_WRITE(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x), v))
01182 #define HW_PDB_POEN_SET(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) |  (v)))
01183 #define HW_PDB_POEN_CLR(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) & ~(v)))
01184 #define HW_PDB_POEN_TOG(x, v)    (HW_PDB_POEN_WR(x, HW_PDB_POEN_RD(x) ^  (v)))
01185 /*@}*/
01186 
01187 /*
01188  * Constants & macros for individual PDB_POEN bitfields
01189  */
01190 
01191 /*!
01192  * @name Register PDB_POEN, field POEN[7:0] (RW)
01193  *
01194  * Enables the pulse output. Only lower Y bits are implemented in this MCU.
01195  *
01196  * Values:
01197  * - 0 - PDB Pulse-Out disabled
01198  * - 1 - PDB Pulse-Out enabled
01199  */
01200 /*@{*/
01201 #define BP_PDB_POEN_POEN     (0U)          /*!< Bit position for PDB_POEN_POEN. */
01202 #define BM_PDB_POEN_POEN     (0x000000FFU) /*!< Bit mask for PDB_POEN_POEN. */
01203 #define BS_PDB_POEN_POEN     (8U)          /*!< Bit field size in bits for PDB_POEN_POEN. */
01204 
01205 /*! @brief Read current value of the PDB_POEN_POEN field. */
01206 #define BR_PDB_POEN_POEN(x)  (UNION_READ(hw_pdb_poen_t, HW_PDB_POEN_ADDR(x), U, B.POEN))
01207 
01208 /*! @brief Format value for bitfield PDB_POEN_POEN. */
01209 #define BF_PDB_POEN_POEN(v)  ((uint32_t)((uint32_t)(v) << BP_PDB_POEN_POEN) & BM_PDB_POEN_POEN)
01210 
01211 /*! @brief Set the POEN field to a new value. */
01212 #define BW_PDB_POEN_POEN(x, v) (HW_PDB_POEN_WR(x, (HW_PDB_POEN_RD(x) & ~BM_PDB_POEN_POEN) | BF_PDB_POEN_POEN(v)))
01213 /*@}*/
01214 
01215 /*******************************************************************************
01216  * HW_PDB_POnDLY - Pulse-Out n Delay register
01217  ******************************************************************************/
01218 
01219 /*!
01220  * @brief HW_PDB_POnDLY - Pulse-Out n Delay register (RW)
01221  *
01222  * Reset value: 0x00000000U
01223  */
01224 typedef union _hw_pdb_pondly
01225 {
01226     uint32_t U;
01227     struct _hw_pdb_pondly_bitfields
01228     {
01229         uint32_t DLY2 : 16;            /*!< [15:0] PDB Pulse-Out Delay 2 */
01230         uint32_t DLY1 : 16;            /*!< [31:16] PDB Pulse-Out Delay 1 */
01231     } B;
01232 } hw_pdb_pondly_t;
01233 
01234 /*!
01235  * @name Constants and macros for entire PDB_POnDLY register
01236  */
01237 /*@{*/
01238 #define HW_PDB_POnDLY_COUNT (3U)
01239 
01240 #define HW_PDB_POnDLY_ADDR(x, n) ((x) + 0x194U + (0x4U * (n)))
01241 
01242 #define HW_PDB_POnDLY(x, n)      (*(__IO hw_pdb_pondly_t *) HW_PDB_POnDLY_ADDR(x, n))
01243 #define HW_PDB_POnDLY_RD(x, n)   (ADDRESS_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n)))
01244 #define HW_PDB_POnDLY_WR(x, n, v) (ADDRESS_WRITE(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), v))
01245 #define HW_PDB_POnDLY_SET(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) |  (v)))
01246 #define HW_PDB_POnDLY_CLR(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) & ~(v)))
01247 #define HW_PDB_POnDLY_TOG(x, n, v) (HW_PDB_POnDLY_WR(x, n, HW_PDB_POnDLY_RD(x, n) ^  (v)))
01248 /*@}*/
01249 
01250 /*
01251  * Constants & macros for individual PDB_POnDLY bitfields
01252  */
01253 
01254 /*!
01255  * @name Register PDB_POnDLY, field DLY2[15:0] (RW)
01256  *
01257  * These bits specify the delay 2 value for the PDB Pulse-Out. Pulse-Out goes
01258  * low when the PDB counter is equal to the DLY2. Reading these bits returns the
01259  * value of internal register that is effective for the current PDB cycle.
01260  */
01261 /*@{*/
01262 #define BP_PDB_POnDLY_DLY2   (0U)          /*!< Bit position for PDB_POnDLY_DLY2. */
01263 #define BM_PDB_POnDLY_DLY2   (0x0000FFFFU) /*!< Bit mask for PDB_POnDLY_DLY2. */
01264 #define BS_PDB_POnDLY_DLY2   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY2. */
01265 
01266 /*! @brief Read current value of the PDB_POnDLY_DLY2 field. */
01267 #define BR_PDB_POnDLY_DLY2(x, n) (UNION_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), U, B.DLY2))
01268 
01269 /*! @brief Format value for bitfield PDB_POnDLY_DLY2. */
01270 #define BF_PDB_POnDLY_DLY2(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY2) & BM_PDB_POnDLY_DLY2)
01271 
01272 /*! @brief Set the DLY2 field to a new value. */
01273 #define BW_PDB_POnDLY_DLY2(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY2) | BF_PDB_POnDLY_DLY2(v)))
01274 /*@}*/
01275 
01276 /*!
01277  * @name Register PDB_POnDLY, field DLY1[31:16] (RW)
01278  *
01279  * These bits specify the delay 1 value for the PDB Pulse-Out. Pulse-Out goes
01280  * high when the PDB counter is equal to the DLY1. Reading these bits returns the
01281  * value of internal register that is effective for the current PDB cycle.
01282  */
01283 /*@{*/
01284 #define BP_PDB_POnDLY_DLY1   (16U)         /*!< Bit position for PDB_POnDLY_DLY1. */
01285 #define BM_PDB_POnDLY_DLY1   (0xFFFF0000U) /*!< Bit mask for PDB_POnDLY_DLY1. */
01286 #define BS_PDB_POnDLY_DLY1   (16U)         /*!< Bit field size in bits for PDB_POnDLY_DLY1. */
01287 
01288 /*! @brief Read current value of the PDB_POnDLY_DLY1 field. */
01289 #define BR_PDB_POnDLY_DLY1(x, n) (UNION_READ(hw_pdb_pondly_t, HW_PDB_POnDLY_ADDR(x, n), U, B.DLY1))
01290 
01291 /*! @brief Format value for bitfield PDB_POnDLY_DLY1. */
01292 #define BF_PDB_POnDLY_DLY1(v) ((uint32_t)((uint32_t)(v) << BP_PDB_POnDLY_DLY1) & BM_PDB_POnDLY_DLY1)
01293 
01294 /*! @brief Set the DLY1 field to a new value. */
01295 #define BW_PDB_POnDLY_DLY1(x, n, v) (HW_PDB_POnDLY_WR(x, n, (HW_PDB_POnDLY_RD(x, n) & ~BM_PDB_POnDLY_DLY1) | BF_PDB_POnDLY_DLY1(v)))
01296 /*@}*/
01297 
01298 /*******************************************************************************
01299  * hw_pdb_t - module struct
01300  ******************************************************************************/
01301 /*!
01302  * @brief All PDB module registers.
01303  */
01304 #pragma pack(1)
01305 typedef struct _hw_pdb
01306 {
01307     __IO hw_pdb_sc_t SC ;                   /*!< [0x0] Status and Control register */
01308     __IO hw_pdb_mod_t MOD ;                 /*!< [0x4] Modulus register */
01309     __I hw_pdb_cnt_t CNT ;                  /*!< [0x8] Counter register */
01310     __IO hw_pdb_idly_t IDLY ;               /*!< [0xC] Interrupt Delay register */
01311     struct {
01312         __IO hw_pdb_chnc1_t CHnC1 ;         /*!< [0x10] Channel n Control register 1 */
01313         __IO hw_pdb_chns_t CHnS ;           /*!< [0x14] Channel n Status register */
01314         __IO hw_pdb_chndly0_t CHnDLY0 ;     /*!< [0x18] Channel n Delay 0 register */
01315         __IO hw_pdb_chndly1_t CHnDLY1 ;     /*!< [0x1C] Channel n Delay 1 register */
01316         uint8_t _reserved0[24];
01317     } CH[2];
01318     uint8_t _reserved0[240];
01319     struct {
01320         __IO hw_pdb_dacintcn_t DACINTCn ;   /*!< [0x150] DAC Interval Trigger n Control register */
01321         __IO hw_pdb_dacintn_t DACINTn ;     /*!< [0x154] DAC Interval n register */
01322     } DAC[2];
01323     uint8_t _reserved1[48];
01324     __IO hw_pdb_poen_t POEN ;               /*!< [0x190] Pulse-Out n Enable register */
01325     __IO hw_pdb_pondly_t POnDLY [3];        /*!< [0x194] Pulse-Out n Delay register */
01326 } hw_pdb_t;
01327 #pragma pack()
01328 
01329 /*! @brief Macro to access all PDB registers. */
01330 /*! @param x PDB module instance base address. */
01331 /*! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
01332  *     use the '&' operator, like <code>&HW_PDB(PDB0_BASE)</code>. */
01333 #define HW_PDB(x)      (*(hw_pdb_t *)(x))
01334 
01335 #endif /* __HW_PDB_REGISTERS_H__ */
01336 /* EOF */